Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T46,T163,T98
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T44
1	0	Covered	T30,T48,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	172391425	8153	0	0
GateOpen_A	172391425	14531	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172391425	8153	0	0
T1	42166	0	0	0
T4	11276	4	0	0
T5	9196	0	0	0
T6	5699	4	0	0
T20	0	4	0	0
T21	0	4	0	0
T29	7058	0	0	0
T30	4489	10	0	0
T31	20245	0	0	0
T32	2536	0	0	0
T33	4546	0	0	0
T34	8273	0	0	0
T44	0	4	0	0
T48	0	6	0	0
T96	0	4	0	0
T98	0	23	0	0
T163	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	172391425	14531	0	0
T1	42166	0	0	0
T4	11276	4	0	0
T5	9196	0	0	0
T6	5699	8	0	0
T29	7058	4	0	0
T30	4489	14	0	0
T31	20245	0	0	0
T32	2536	4	0	0
T33	4546	0	0	0
T34	8273	0	0	0
T37	0	4	0	0
T42	0	4	0	0
T44	0	8	0	0
T45	0	200	0	0
T48	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T46,T163,T98
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T44
1	0	Covered	T30,T48,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	18570547	1953	0	0
GateOpen_A	18570547	3545	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570547	1953	0	0
T1	4668	0	0	0
T4	1233	1	0	0
T5	1090	0	0	0
T6	618	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	771	0	0	0
T30	476	2	0	0
T31	2232	0	0	0
T32	269	0	0	0
T33	714	0	0	0
T34	952	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T96	0	1	0	0
T98	0	5	0	0
T163	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570547	3545	0	0
T1	4668	0	0	0
T4	1233	1	0	0
T5	1090	0	0	0
T6	618	2	0	0
T29	771	1	0	0
T30	476	3	0	0
T31	2232	0	0	0
T32	269	1	0	0
T33	714	0	0	0
T34	952	0	0	0
T37	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	50	0	0
T48	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T46,T163,T98
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T44
1	0	Covered	T30,T48,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	37141547	2084	0	0
GateOpen_A	37141547	3676	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141547	2084	0	0
T1	9335	0	0	0
T4	2466	1	0	0
T5	2181	0	0	0
T6	1235	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	1542	0	0	0
T30	952	2	0	0
T31	4463	0	0	0
T32	537	0	0	0
T33	1426	0	0	0
T34	1903	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T96	0	1	0	0
T98	0	5	0	0
T163	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141547	3676	0	0
T1	9335	0	0	0
T4	2466	1	0	0
T5	2181	0	0	0
T6	1235	2	0	0
T29	1542	1	0	0
T30	952	3	0	0
T31	4463	0	0	0
T32	537	1	0	0
T33	1426	0	0	0
T34	1903	0	0	0
T37	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	50	0	0
T48	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T46,T163,T98
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T44
1	0	Covered	T30,T48,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	76186096	2071	0	0
GateOpen_A	76186096	3668	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76186096	2071	0	0
T1	18775	0	0	0
T4	5051	1	0	0
T5	3950	0	0	0
T6	2564	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	3163	0	0	0
T30	1995	2	0	0
T31	9033	0	0	0
T32	1153	0	0	0
T33	1604	0	0	0
T34	3612	0	0	0
T44	0	1	0	0
T48	0	1	0	0
T96	0	1	0	0
T98	0	7	0	0
T163	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76186096	3668	0	0
T1	18775	0	0	0
T4	5051	1	0	0
T5	3950	0	0	0
T6	2564	2	0	0
T29	3163	1	0	0
T30	1995	3	0	0
T31	9033	0	0	0
T32	1153	1	0	0
T33	1604	0	0	0
T34	3612	0	0	0
T37	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	50	0	0
T48	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T46,T163,T98
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T44
1	0	Covered	T30,T48,T21
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	40493235	2045	0	0
GateOpen_A	40493235	3642	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40493235	2045	0	0
T1	9388	0	0	0
T4	2526	1	0	0
T5	1975	0	0	0
T6	1282	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	1582	0	0	0
T30	1066	4	0	0
T31	4517	0	0	0
T32	577	0	0	0
T33	802	0	0	0
T34	1806	0	0	0
T44	0	1	0	0
T48	0	3	0	0
T96	0	1	0	0
T98	0	6	0	0
T163	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40493235	3642	0	0
T1	9388	0	0	0
T4	2526	1	0	0
T5	1975	0	0	0
T6	1282	2	0	0
T29	1582	1	0	0
T30	1066	5	0	0
T31	4517	0	0	0
T32	577	1	0	0
T33	802	0	0	0
T34	1806	0	0	0
T37	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T45	0	50	0	0
T48	0	4	0	0