Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	178669535	30504	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178669535	30504	0	0
T10	940770	407	0	0
T11	0	189	0	0
T12	0	116	0	0
T13	0	39	0	0
T14	0	151	0	0
T15	0	203	0	0
T16	0	208	0	0
T17	0	112	0	0
T18	0	165	0	0
T19	0	858	0	0
T20	8100	0	0	0
T21	4195	0	0	0
T22	7580	0	0	0
T23	7595	0	0	0
T24	25190	0	0	0
T25	10815	0	0	0
T26	9930	0	0	0
T27	10900	0	0	0
T28	10365	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35733907	4487	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	4487	0	0
T10	188154	52	0	0
T11	0	30	0	0
T12	0	17	0	0
T13	0	6	0	0
T14	0	24	0	0
T15	0	30	0	0
T16	0	26	0	0
T17	0	15	0	0
T18	0	28	0	0
T19	0	115	0	0
T20	1620	0	0	0
T21	839	0	0	0
T22	1516	0	0	0
T23	1519	0	0	0
T24	5038	0	0	0
T25	2163	0	0	0
T26	1986	0	0	0
T27	2180	0	0	0
T28	2073	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35733907	4460	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	4460	0	0
T10	188154	59	0	0
T11	0	30	0	0
T12	0	17	0	0
T13	0	6	0	0
T14	0	23	0	0
T15	0	29	0	0
T16	0	29	0	0
T17	0	16	0	0
T18	0	28	0	0
T19	0	112	0	0
T20	1620	0	0	0
T21	839	0	0	0
T22	1516	0	0	0
T23	1519	0	0	0
T24	5038	0	0	0
T25	2163	0	0	0
T26	1986	0	0	0
T27	2180	0	0	0
T28	2073	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35733907	6136	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	6136	0	0
T10	188154	82	0	0
T11	0	38	0	0
T12	0	23	0	0
T13	0	8	0	0
T14	0	29	0	0
T15	0	41	0	0
T16	0	41	0	0
T17	0	22	0	0
T18	0	33	0	0
T19	0	176	0	0
T20	1620	0	0	0
T21	839	0	0	0
T22	1516	0	0	0
T23	1519	0	0	0
T24	5038	0	0	0
T25	2163	0	0	0
T26	1986	0	0	0
T27	2180	0	0	0
T28	2073	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35733907	6131	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	6131	0	0
T10	188154	80	0	0
T11	0	38	0	0
T12	0	23	0	0
T13	0	8	0	0
T14	0	32	0	0
T15	0	41	0	0
T16	0	41	0	0
T17	0	22	0	0
T18	0	33	0	0
T19	0	171	0	0
T20	1620	0	0	0
T21	839	0	0	0
T22	1516	0	0	0
T23	1519	0	0	0
T24	5038	0	0	0
T25	2163	0	0	0
T26	1986	0	0	0
T27	2180	0	0	0
T28	2073	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	35733907	9290	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	9290	0	0
T10	188154	134	0	0
T11	0	53	0	0
T12	0	36	0	0
T13	0	11	0	0
T14	0	43	0	0
T15	0	62	0	0
T16	0	71	0	0
T17	0	37	0	0
T18	0	43	0	0
T19	0	284	0	0
T20	1620	0	0	0
T21	839	0	0	0
T22	1516	0	0	0
T23	1519	0	0	0
T24	5038	0	0	0
T25	2163	0	0	0
T26	1986	0	0	0
T27	2180	0	0	0
T28	2073	0	0	0