Unified Coverage Report :: Module

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	22512	22512	0	0
OutputsKnown_A	1507328899	1422129197	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	214403442	199119558	0	14472
gen_flops.gen_stable_chks.OutputDelay_A	484755160	455443548	0	16884
gen_flops.gen_stable_chks.OutputIfUnstable_A	484755160	129804	0	0
gen_no_flops.OutputDelay_A	808170297	767474774	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	22512	22512
T1	28	28
T4	28	28
T5	28	28
T6	28	28
T29	28	28
T30	28	28
T31	28	28
T32	28	28
T33	28	28
T34	28	28

OutputsKnown_A

Name	Attempts	Real Successes
Total	1507328899	1422129197
T1	505298	499908
T4	82094	78607
T5	78394	75340
T6	41249	38755
T29	55529	52237
T30	41494	39308
T31	145552	142855
T32	30622	27920
T33	35206	31754
T34	58366	55504

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	214403442	199119558	14472
T1	115002	113658	18
T4	7890	7488	18
T5	12096	11544	18
T6	3840	3558	18
T29	6714	6240	18
T30	6450	6084	18
T31	13542	13242	18
T32	6912	6252	18
T33	6012	5334	18
T34	5412	5094	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	484755160	455443548	16884
T1	135341	133757	21
T4	28729	27316	21
T5	24438	23331	21
T6	14523	13506	21
T29	18576	17282	21
T30	13017	12251	21
T31	51182	50089	21
T32	8260	7470	21
T33	10288	9139	21
T34	20463	19295	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	484755160	129804
T1	135341	4
T4	21048	20
T5	24438	147
T6	14523	8
T22	0	10
T26	0	35
T27	0	47
T29	18576	8
T30	13017	56
T31	51182	178
T32	8260	8
T33	10288	14
T34	20463	27
T37	6527	77
T43	0	57
T60	0	28
T61	0	43
T62	0	35
T63	0	194

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	808170297	767474774
T1	254955	252454
T4	45475	43764
T5	41860	40426
T6	22886	21652
T29	30239	28676
T30	22027	20934
T31	80828	79485
T32	15450	14159
T33	18906	17242
T34	32491	31076

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	76185638	71589975	0	0
gen_flops.gen_stable_chks.OutputDelay_A	76185638	71583054	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	76185638	18997	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	76185638	71589975
T1	18775	18558
T4	5051	4807
T5	3950	3774
T6	2563	2387
T29	3162	2945
T30	1995	1874
T31	9032	8842
T32	1152	1045
T33	1604	1428
T34	3611	3408

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	76185638	71583054	2412
T1	18775	18555	3
T4	5051	4804	3
T5	3950	3771	3
T6	2563	2384	3
T29	3162	2942	3
T30	1995	1871	3
T31	9032	8839	3
T32	1152	1042	3
T33	1604	1425	3
T34	3611	3405	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	76185638	18997
T1	18775	0
T5	3950	39
T6	2563	0
T29	3162	0
T30	1995	0
T31	9032	0
T32	1152	1
T33	1604	2
T34	3611	14
T37	2117	32
T43	0	29
T60	0	11
T61	0	21
T62	0	18
T63	0	116

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_no_flops.OutputDelay_A	35733907	33193662	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_no_flops.OutputDelay_A	35733907	33193662	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T34 T37  | T5 T34 T37  | T5 T34 T37  | T5 T34 T37 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T34 T37

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T34,T37

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T34,T37

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T34,T37

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T34,T37

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T34,T37
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T34,T37
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T34,T37
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T34,T37
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_stable_chks.OutputDelay_A	35733907	33186593	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	35733907	11656	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	35733907	11656
T1	19167	0
T5	2016	23
T6	640	0
T22	0	10
T26	0	35
T27	0	47
T29	1119	0
T30	1075	0
T31	2257	0
T32	1152	0
T33	1002	0
T34	902	2
T37	2205	27
T43	0	14
T60	0	10
T61	0	14
T63	0	42

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_stable_chks.OutputDelay_A	35733907	33186593	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	35733907	13160	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	35733907	13160
T1	19167	0
T5	2016	31
T6	640	0
T29	1119	0
T30	1075	0
T31	2257	0
T32	1152	1
T33	1002	2
T34	902	3
T37	2205	18
T43	0	14
T60	0	7
T61	0	8
T62	0	17
T63	0	36

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	81853782	0	0
gen_no_flops.OutputDelay_A	84275427	81853782	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	81853782
T1	19558	19447
T4	5262	5136
T5	4114	4045
T6	2670	2572
T29	3294	3211
T30	2218	2120
T31	9409	9297
T32	1201	1118
T33	1670	1558
T34	3762	3651

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	84275427	81853782
T1	19558	19447
T4	5262	5136
T5	4114	4045
T6	2670	2572
T29	3294	3211
T30	2218	2120
T31	9409	9297
T32	1201	1118
T33	1670	1558
T34	3762	3651

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	76185638	73903823	0	0
gen_no_flops.OutputDelay_A	76185638	73903823	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	76185638	73903823
T1	18775	18668
T4	5051	4930
T5	3950	3884
T6	2563	2469
T29	3162	3082
T30	1995	1902
T31	9032	8924
T32	1152	1073
T33	1604	1497
T34	3611	3504

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	76185638	73903823
T1	18775	18668
T4	5051	4930
T5	3950	3884
T6	2563	2469
T29	3162	3082
T30	1995	1902
T31	9032	8924
T32	1152	1073
T33	1604	1497
T34	3611	3504

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	37141130	37141130	0	0
gen_no_flops.OutputDelay_A	37141130	37141130	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37141130	37141130
T1	9334	9334
T4	2465	2465
T5	2180	2180
T6	1235	1235
T29	1541	1541
T30	951	951
T31	4462	4462
T32	537	537
T33	1426	1426
T34	1902	1902

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37141130	37141130
T1	9334	9334
T4	2465	2465
T5	2180	2180
T6	1235	1235
T29	1541	1541
T30	951	951
T31	4462	4462
T32	537	537
T33	1426	1426
T34	1902	1902

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	18570137	18570137	0	0
gen_no_flops.OutputDelay_A	18570137	18570137	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	18570137	18570137
T1	4667	4667
T4	1233	1233
T5	1089	1089
T6	617	617
T29	771	771
T30	476	476
T31	2231	2231
T32	268	268
T33	713	713
T34	951	951

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	18570137	18570137
T1	4667	4667
T4	1233	1233
T5	1089	1089
T6	617	617
T29	771	771
T30	476	476
T31	2231	2231
T32	268	268
T33	713	713
T34	951	951

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	40492815	39328778	0	0
gen_no_flops.OutputDelay_A	40492815	39328778	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	40492815	39328778
T1	9387	9334
T4	2526	2466
T5	1975	1942
T6	1281	1235
T29	1581	1541
T30	1065	1019
T31	4516	4463
T32	576	537
T33	801	748
T34	1805	1752

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	40492815	39328778
T1	9387	9334
T4	2526	2466
T5	1975	1942
T6	1281	1235
T29	1581	1541
T30	1065	1019
T31	4516	4463
T32	576	537
T33	801	748
T34	1805	1752

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35733907	33186593	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35733907	33186593	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35733907	33186593	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35733907	33186593	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35733907	33186593	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	35733907	33186593	0	2412

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	35733907	33186593	2412
T1	19167	18943	3
T4	1315	1248	3
T5	2016	1924	3
T6	640	593	3
T29	1119	1040	3
T30	1075	1014	3
T31	2257	2207	3
T32	1152	1042	3
T33	1002	889	3
T34	902	849	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_no_flops.OutputDelay_A	35733907	33193662	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_no_flops.OutputDelay_A	35733907	33193662	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_no_flops.OutputDelay_A	35733907	33193662	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	35733907	33193662	0	0
gen_no_flops.OutputDelay_A	35733907	33193662	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	35733907	33193662
T1	19167	18946
T4	1315	1251
T5	2016	1927
T6	640	596
T29	1119	1043
T30	1075	1017
T31	2257	2210
T32	1152	1045
T33	1002	892
T34	902	852

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_flops.gen_stable_chks.OutputDelay_A	84275427	79371827	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	84275427	21589	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	84275427	79371827	2412
T1	19558	19329	3
T4	5262	5004	3
T5	4114	3928	3
T6	2670	2484	3
T29	3294	3065	3
T30	2218	2088	3
T31	9409	9209	3
T32	1201	1086	3
T33	1670	1484	3
T34	3762	3548	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	84275427	21589
T1	19558	1
T4	5262	5
T5	4114	10
T6	2670	3
T29	3294	1
T30	2218	17
T31	9409	42
T32	1201	2
T33	1670	1
T34	3762	2

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_no_flops.OutputDelay_A	84275427	79378788	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_flops.gen_stable_chks.OutputDelay_A	84275427	79371827	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	84275427	21560	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	84275427	79371827	2412
T1	19558	19329	3
T4	5262	5004	3
T5	4114	3928	3
T6	2670	2484	3
T29	3294	3065	3
T30	2218	2088	3
T31	9409	9209	3
T32	1201	1086	3
T33	1670	1484	3
T34	3762	3548	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	84275427	21560
T1	19558	1
T4	5262	5
T5	4114	15
T6	2670	1
T29	3294	1
T30	2218	17
T31	9409	45
T32	1201	1
T33	1670	3
T34	3762	2

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_no_flops.OutputDelay_A	84275427	79378788	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_flops.gen_stable_chks.OutputDelay_A	84275427	79371827	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	84275427	21368	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	84275427	79371827	2412
T1	19558	19329	3
T4	5262	5004	3
T5	4114	3928	3
T6	2670	2484	3
T29	3294	3065	3
T30	2218	2088	3
T31	9409	9209	3
T32	1201	1086	3
T33	1670	1484	3
T34	3762	3548	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	84275427	21368
T1	19558	1
T4	5262	5
T5	4114	15
T6	2670	1
T29	3294	1
T30	2218	13
T31	9409	46
T32	1201	1
T33	1670	3
T34	3762	3

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_no_flops.OutputDelay_A	84275427	79378788	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_flops.gen_stable_chks.OutputDelay_A	84275427	79371827	0	2412
gen_flops.gen_stable_chks.OutputIfUnstable_A	84275427	21474	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	84275427	79371827	2412
T1	19558	19329	3
T4	5262	5004	3
T5	4114	3928	3
T6	2670	2484	3
T29	3294	3065	3
T30	2218	2088	3
T31	9409	9209	3
T32	1201	1086	3
T33	1670	1484	3
T34	3762	3548	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	84275427	21474
T1	19558	1
T4	5262	5
T5	4114	14
T6	2670	3
T29	3294	5
T30	2218	9
T31	9409	45
T32	1201	2
T33	1670	3
T34	3762	1

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T29 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T29

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	804	804	0	0
OutputsKnown_A	84275427	79378788	0	0
gen_no_flops.OutputDelay_A	84275427	79378788	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	804	804
T1	1	1
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	84275427	79378788
T1	19558	19332
T4	5262	5007
T5	4114	3931
T6	2670	2487
T29	3294	3068
T30	2218	2091
T31	9409	9212
T32	1201	1089
T33	1670	1487
T34	3762	3551

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl