Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T45,T3,T49

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	35733907	33105800	0	0
AllClkBypReqTrue_A	35733907	85555	0	0
IoClkBypReqFalse_A	35733907	33048209	0	2412
IoClkBypReqTrue_A	35733907	138532	0	0
LcClkBypAckFalse_A	35733907	33110146	0	0
LcClkBypAckTrue_A	35733907	81209	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	33105800	0	0
T1	19167	18945	0	0
T4	1315	1250	0	0
T5	2016	1704	0	0
T6	640	595	0	0
T29	1119	1042	0	0
T30	1075	1016	0	0
T31	2257	2209	0	0
T32	1152	1044	0	0
T33	1002	887	0	0
T34	902	833	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	85555	0	0
T1	19167	0	0	0
T5	2016	222	0	0
T6	640	0	0	0
T22	0	158	0	0
T26	0	16	0	0
T29	1119	0	0	0
T30	1075	0	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	4	0	0
T34	902	18	0	0
T37	2205	32	0	0
T43	0	78	0	0
T60	0	31	0	0
T62	0	76	0	0
T63	0	447	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	33048209	0	2412
T1	19167	18943	0	3
T4	1315	1248	0	3
T5	2016	1541	0	3
T6	640	593	0	3
T29	1119	1040	0	3
T30	1075	1014	0	3
T31	2257	2207	0	3
T32	1152	1042	0	3
T33	1002	889	0	3
T34	902	804	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	138532	0	0
T1	19167	0	0	0
T5	2016	383	0	0
T6	640	0	0	0
T22	0	106	0	0
T26	0	427	0	0
T27	0	285	0	0
T29	1119	0	0	0
T30	1075	0	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	45	0	0
T37	2205	201	0	0
T43	0	175	0	0
T60	0	93	0	0
T61	0	166	0	0
T63	0	646	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	33110146	0	0
T1	19167	18945	0	0
T4	1315	1250	0	0
T5	2016	1732	0	0
T6	640	595	0	0
T29	1119	1042	0	0
T30	1075	1016	0	0
T31	2257	2209	0	0
T32	1152	1044	0	0
T33	1002	891	0	0
T34	902	823	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	81209	0	0
T1	19167	0	0	0
T5	2016	194	0	0
T6	640	0	0	0
T22	0	99	0	0
T26	0	164	0	0
T27	0	195	0	0
T29	1119	0	0	0
T30	1075	0	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	28	0	0
T37	2205	123	0	0
T43	0	119	0	0
T60	0	71	0	0
T61	0	47	0	0
T63	0	317	0	0