Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	337103364	9040	0	0
TransStop_A	337103364	4730	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337103364	9040	0	0
T1	78232	0	0	0
T4	21048	4	0	0
T5	16460	0	0	0
T6	10680	0	0	0
T20	0	4	0	0
T23	0	15	0	0
T25	0	13	0	0
T29	13176	4	0	0
T30	8872	0	0	0
T31	37636	26	0	0
T32	4808	0	0	0
T33	6684	0	0	0
T34	15048	0	0	0
T44	0	4	0	0
T47	0	44	0	0
T59	0	20	0	0
T96	0	4	0	0
T97	0	18	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	337103364	4730	0	0
T1	78232	0	0	0
T4	21048	4	0	0
T5	16460	0	0	0
T6	10680	0	0	0
T11	0	10	0	0
T20	0	4	0	0
T23	0	10	0	0
T25	0	6	0	0
T29	13176	2	0	0
T30	8872	0	0	0
T31	37636	14	0	0
T32	4808	0	0	0
T33	6684	0	0	0
T34	15048	0	0	0
T44	0	4	0	0
T47	0	23	0	0
T59	0	9	0	0
T96	0	4	0	0
T97	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84275841	2254	0	0
TransStop_A	84275841	1181	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	2254	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	4	0	0
T25	0	3	0	0
T29	3294	2	0	0
T30	2218	0	0	0
T31	9409	7	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	10	0	0
T59	0	5	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	1181	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T25	0	2	0	0
T29	3294	1	0	0
T30	2218	0	0	0
T31	9409	3	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	6	0	0
T59	0	3	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84275841	2236	0	0
TransStop_A	84275841	1169	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	2236	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	5	0	0
T25	0	3	0	0
T29	3294	2	0	0
T30	2218	0	0	0
T31	9409	6	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	8	0	0
T59	0	2	0	0
T96	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	1169	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T25	0	1	0	0
T29	3294	1	0	0
T30	2218	0	0	0
T31	9409	2	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	4	0	0
T59	0	1	0	0
T96	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84275841	2268	0	0
TransStop_A	84275841	1188	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	2268	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	4	0	0
T25	0	5	0	0
T29	3294	0	0	0
T30	2218	0	0	0
T31	9409	5	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	14	0	0
T59	0	6	0	0
T96	0	1	0	0
T97	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	1188	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	3	0	0
T25	0	3	0	0
T29	3294	0	0	0
T30	2218	0	0	0
T31	9409	4	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	7	0	0
T59	0	2	0	0
T96	0	1	0	0
T97	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	84275841	2282	0	0
TransStop_A	84275841	1192	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	2282	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T23	0	2	0	0
T25	0	2	0	0
T29	3294	0	0	0
T30	2218	0	0	0
T31	9409	8	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	12	0	0
T59	0	7	0	0
T96	0	1	0	0
T97	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275841	1192	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4115	0	0	0
T6	2670	0	0	0
T11	0	10	0	0
T20	0	1	0	0
T23	0	1	0	0
T29	3294	0	0	0
T30	2218	0	0	0
T31	9409	5	0	0
T32	1202	0	0	0
T33	1671	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	6	0	0
T59	0	3	0	0
T96	0	1	0	0
T97	0	4	0	0