Line Coverage for Module :
prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T5 T32 T33
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T5 T32 T33
Line Coverage for Module :
prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
994773997 |
939259438 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
994773997 |
939259438 |
0 |
0 |
| T1 |
268509 |
265618 |
0 |
0 |
| T4 |
60533 |
57831 |
0 |
0 |
| T5 |
51298 |
49183 |
0 |
0 |
| T6 |
30566 |
28642 |
0 |
0 |
| T29 |
38773 |
36263 |
0 |
0 |
| T30 |
26459 |
25105 |
0 |
0 |
| T31 |
108169 |
106110 |
0 |
0 |
| T32 |
16264 |
14895 |
0 |
0 |
| T33 |
23540 |
21448 |
0 |
0 |
| T34 |
43718 |
41502 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T5 T34 T37
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T5 T34 T37
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
35733907 |
33193662 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
35733907 |
33193662 |
0 |
0 |
| T1 |
19167 |
18946 |
0 |
0 |
| T4 |
1315 |
1251 |
0 |
0 |
| T5 |
2016 |
1927 |
0 |
0 |
| T6 |
640 |
596 |
0 |
0 |
| T29 |
1119 |
1043 |
0 |
0 |
| T30 |
1075 |
1017 |
0 |
0 |
| T31 |
2257 |
2210 |
0 |
0 |
| T32 |
1152 |
1045 |
0 |
0 |
| T33 |
1002 |
892 |
0 |
0 |
| T34 |
902 |
852 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T5 T32 T33
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T5 T32 T33
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
35733907 |
33193662 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
35733907 |
33193662 |
0 |
0 |
| T1 |
19167 |
18946 |
0 |
0 |
| T4 |
1315 |
1251 |
0 |
0 |
| T5 |
2016 |
1927 |
0 |
0 |
| T6 |
640 |
596 |
0 |
0 |
| T29 |
1119 |
1043 |
0 |
0 |
| T30 |
1075 |
1017 |
0 |
0 |
| T31 |
2257 |
2210 |
0 |
0 |
| T32 |
1152 |
1045 |
0 |
0 |
| T33 |
1002 |
892 |
0 |
0 |
| T34 |
902 |
852 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T5 T32 T33
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
35733907 |
33193662 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
35733907 |
33193662 |
0 |
0 |
| T1 |
19167 |
18946 |
0 |
0 |
| T4 |
1315 |
1251 |
0 |
0 |
| T5 |
2016 |
1927 |
0 |
0 |
| T6 |
640 |
596 |
0 |
0 |
| T29 |
1119 |
1043 |
0 |
0 |
| T30 |
1075 |
1017 |
0 |
0 |
| T31 |
2257 |
2210 |
0 |
0 |
| T32 |
1152 |
1045 |
0 |
0 |
| T33 |
1002 |
892 |
0 |
0 |
| T34 |
902 |
852 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18570137 |
17991526 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18570137 |
17991526 |
0 |
0 |
| T1 |
4667 |
4639 |
0 |
0 |
| T4 |
1233 |
1202 |
0 |
0 |
| T5 |
1089 |
1061 |
0 |
0 |
| T6 |
617 |
596 |
0 |
0 |
| T29 |
771 |
737 |
0 |
0 |
| T30 |
476 |
469 |
0 |
0 |
| T31 |
2231 |
2210 |
0 |
0 |
| T32 |
268 |
261 |
0 |
0 |
| T33 |
713 |
696 |
0 |
0 |
| T34 |
951 |
927 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
84275427 |
79378788 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84275427 |
79378788 |
0 |
0 |
| T1 |
19558 |
19332 |
0 |
0 |
| T4 |
5262 |
5007 |
0 |
0 |
| T5 |
4114 |
3931 |
0 |
0 |
| T6 |
2670 |
2487 |
0 |
0 |
| T29 |
3294 |
3068 |
0 |
0 |
| T30 |
2218 |
2091 |
0 |
0 |
| T31 |
9409 |
9212 |
0 |
0 |
| T32 |
1201 |
1089 |
0 |
0 |
| T33 |
1670 |
1487 |
0 |
0 |
| T34 |
3762 |
3551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
40492815 |
38146087 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
40492815 |
38146087 |
0 |
0 |
| T1 |
9387 |
9279 |
0 |
0 |
| T4 |
2526 |
2404 |
0 |
0 |
| T5 |
1975 |
1887 |
0 |
0 |
| T6 |
1281 |
1193 |
0 |
0 |
| T29 |
1581 |
1472 |
0 |
0 |
| T30 |
1065 |
1005 |
0 |
0 |
| T31 |
4516 |
4421 |
0 |
0 |
| T32 |
576 |
523 |
0 |
0 |
| T33 |
801 |
714 |
0 |
0 |
| T34 |
1805 |
1704 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
76185638 |
71589975 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
76185638 |
71589975 |
0 |
0 |
| T1 |
18775 |
18558 |
0 |
0 |
| T4 |
5051 |
4807 |
0 |
0 |
| T5 |
3950 |
3774 |
0 |
0 |
| T6 |
2563 |
2387 |
0 |
0 |
| T29 |
3162 |
2945 |
0 |
0 |
| T30 |
1995 |
1874 |
0 |
0 |
| T31 |
9032 |
8842 |
0 |
0 |
| T32 |
1152 |
1045 |
0 |
0 |
| T33 |
1604 |
1428 |
0 |
0 |
| T34 |
3611 |
3408 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
37141130 |
35983748 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
37141130 |
35983748 |
0 |
0 |
| T1 |
9334 |
9279 |
0 |
0 |
| T4 |
2465 |
2403 |
0 |
0 |
| T5 |
2180 |
2125 |
0 |
0 |
| T6 |
1235 |
1194 |
0 |
0 |
| T29 |
1541 |
1472 |
0 |
0 |
| T30 |
951 |
937 |
0 |
0 |
| T31 |
4462 |
4421 |
0 |
0 |
| T32 |
537 |
523 |
0 |
0 |
| T33 |
1426 |
1391 |
0 |
0 |
| T34 |
1902 |
1854 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18570137 |
17991526 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18570137 |
17991526 |
0 |
0 |
| T1 |
4667 |
4639 |
0 |
0 |
| T4 |
1233 |
1202 |
0 |
0 |
| T5 |
1089 |
1061 |
0 |
0 |
| T6 |
617 |
596 |
0 |
0 |
| T29 |
771 |
737 |
0 |
0 |
| T30 |
476 |
469 |
0 |
0 |
| T31 |
2231 |
2210 |
0 |
0 |
| T32 |
268 |
261 |
0 |
0 |
| T33 |
713 |
696 |
0 |
0 |
| T34 |
951 |
927 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
84275427 |
79378788 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84275427 |
79378788 |
0 |
0 |
| T1 |
19558 |
19332 |
0 |
0 |
| T4 |
5262 |
5007 |
0 |
0 |
| T5 |
4114 |
3931 |
0 |
0 |
| T6 |
2670 |
2487 |
0 |
0 |
| T29 |
3294 |
3068 |
0 |
0 |
| T30 |
2218 |
2091 |
0 |
0 |
| T31 |
9409 |
9212 |
0 |
0 |
| T32 |
1201 |
1089 |
0 |
0 |
| T33 |
1670 |
1487 |
0 |
0 |
| T34 |
3762 |
3551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18570137 |
17991526 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18570137 |
17991526 |
0 |
0 |
| T1 |
4667 |
4639 |
0 |
0 |
| T4 |
1233 |
1202 |
0 |
0 |
| T5 |
1089 |
1061 |
0 |
0 |
| T6 |
617 |
596 |
0 |
0 |
| T29 |
771 |
737 |
0 |
0 |
| T30 |
476 |
469 |
0 |
0 |
| T31 |
2231 |
2210 |
0 |
0 |
| T32 |
268 |
261 |
0 |
0 |
| T33 |
713 |
696 |
0 |
0 |
| T34 |
951 |
927 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18570137 |
17991526 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18570137 |
17991526 |
0 |
0 |
| T1 |
4667 |
4639 |
0 |
0 |
| T4 |
1233 |
1202 |
0 |
0 |
| T5 |
1089 |
1061 |
0 |
0 |
| T6 |
617 |
596 |
0 |
0 |
| T29 |
771 |
737 |
0 |
0 |
| T30 |
476 |
469 |
0 |
0 |
| T31 |
2231 |
2210 |
0 |
0 |
| T32 |
268 |
261 |
0 |
0 |
| T33 |
713 |
696 |
0 |
0 |
| T34 |
951 |
927 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
37141130 |
35983748 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
37141130 |
35983748 |
0 |
0 |
| T1 |
9334 |
9279 |
0 |
0 |
| T4 |
2465 |
2403 |
0 |
0 |
| T5 |
2180 |
2125 |
0 |
0 |
| T6 |
1235 |
1194 |
0 |
0 |
| T29 |
1541 |
1472 |
0 |
0 |
| T30 |
951 |
937 |
0 |
0 |
| T31 |
4462 |
4421 |
0 |
0 |
| T32 |
537 |
523 |
0 |
0 |
| T33 |
1426 |
1391 |
0 |
0 |
| T34 |
1902 |
1854 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
76185638 |
71589975 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
76185638 |
71589975 |
0 |
0 |
| T1 |
18775 |
18558 |
0 |
0 |
| T4 |
5051 |
4807 |
0 |
0 |
| T5 |
3950 |
3774 |
0 |
0 |
| T6 |
2563 |
2387 |
0 |
0 |
| T29 |
3162 |
2945 |
0 |
0 |
| T30 |
1995 |
1874 |
0 |
0 |
| T31 |
9032 |
8842 |
0 |
0 |
| T32 |
1152 |
1045 |
0 |
0 |
| T33 |
1604 |
1428 |
0 |
0 |
| T34 |
3611 |
3408 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
40492815 |
38146087 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
40492815 |
38146087 |
0 |
0 |
| T1 |
9387 |
9279 |
0 |
0 |
| T4 |
2526 |
2404 |
0 |
0 |
| T5 |
1975 |
1887 |
0 |
0 |
| T6 |
1281 |
1193 |
0 |
0 |
| T29 |
1581 |
1472 |
0 |
0 |
| T30 |
1065 |
1005 |
0 |
0 |
| T31 |
4516 |
4421 |
0 |
0 |
| T32 |
576 |
523 |
0 |
0 |
| T33 |
801 |
714 |
0 |
0 |
| T34 |
1805 |
1704 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
84275427 |
79378788 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84275427 |
79378788 |
0 |
0 |
| T1 |
19558 |
19332 |
0 |
0 |
| T4 |
5262 |
5007 |
0 |
0 |
| T5 |
4114 |
3931 |
0 |
0 |
| T6 |
2670 |
2487 |
0 |
0 |
| T29 |
3294 |
3068 |
0 |
0 |
| T30 |
2218 |
2091 |
0 |
0 |
| T31 |
9409 |
9212 |
0 |
0 |
| T32 |
1201 |
1089 |
0 |
0 |
| T33 |
1670 |
1487 |
0 |
0 |
| T34 |
3762 |
3551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
84275427 |
79378788 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84275427 |
79378788 |
0 |
0 |
| T1 |
19558 |
19332 |
0 |
0 |
| T4 |
5262 |
5007 |
0 |
0 |
| T5 |
4114 |
3931 |
0 |
0 |
| T6 |
2670 |
2487 |
0 |
0 |
| T29 |
3294 |
3068 |
0 |
0 |
| T30 |
2218 |
2091 |
0 |
0 |
| T31 |
9409 |
9212 |
0 |
0 |
| T32 |
1201 |
1089 |
0 |
0 |
| T33 |
1670 |
1487 |
0 |
0 |
| T34 |
3762 |
3551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
84275427 |
79378788 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84275427 |
79378788 |
0 |
0 |
| T1 |
19558 |
19332 |
0 |
0 |
| T4 |
5262 |
5007 |
0 |
0 |
| T5 |
4114 |
3931 |
0 |
0 |
| T6 |
2670 |
2487 |
0 |
0 |
| T29 |
3294 |
3068 |
0 |
0 |
| T30 |
2218 |
2091 |
0 |
0 |
| T31 |
9409 |
9212 |
0 |
0 |
| T32 |
1201 |
1089 |
0 |
0 |
| T33 |
1670 |
1487 |
0 |
0 |
| T34 |
3762 |
3551 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
84275427 |
79378788 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
84275427 |
79378788 |
0 |
0 |
| T1 |
19558 |
19332 |
0 |
0 |
| T4 |
5262 |
5007 |
0 |
0 |
| T5 |
4114 |
3931 |
0 |
0 |
| T6 |
2670 |
2487 |
0 |
0 |
| T29 |
3294 |
3068 |
0 |
0 |
| T30 |
2218 |
2091 |
0 |
0 |
| T31 |
9409 |
9212 |
0 |
0 |
| T32 |
1201 |
1089 |
0 |
0 |
| T33 |
1670 |
1487 |
0 |
0 |
| T34 |
3762 |
3551 |
0 |
0 |