Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	36655700	542290	0	0
clk_enables_rd_A	36655700	8823	0	0
clk_hints_rd_A	36655700	8515	0	0
extclk_ctrl_rd_A	36655700	12154	0	0
extclk_ctrl_regwen_rd_A	36655700	6895	0	0
jitter_enable_rd_A	36655700	16746	0	0
jitter_regwen_rd_A	36655700	6860	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	542290	0	0
T17	307304	12298	0	0
T18	136043	0	0	0
T19	518505	0	0	0
T41	176879	4127	0	0
T56	201094	11006	0	0
T73	218921	9700	0	0
T74	215491	5687	0	0
T75	0	12065	0	0
T76	0	7387	0	0
T77	0	3640	0	0
T78	0	3666	0	0
T79	0	5673	0	0
T80	1390	0	0	0
T81	1967	0	0	0
T82	1472	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	8823	0	0
T8	118866	0	0	0
T12	46096	0	0	0
T15	0	4	0	0
T41	0	188	0	0
T74	0	298	0	0
T76	0	339	0	0
T77	0	177	0	0
T83	25366	0	0	0
T136	2058	1	0	0
T137	0	4	0	0
T138	0	8	0	0
T139	0	4	0	0
T140	0	3	0	0
T141	1816	0	0	0
T142	859	0	0	0
T143	1981	0	0	0
T144	1714	0	0	0
T145	1958	0	0	0
T146	3632	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	8515	0	0
T11	119505	3	0	0
T15	0	1	0	0
T41	0	260	0	0
T50	15208	0	0	0
T74	0	194	0	0
T76	0	254	0	0
T77	0	169	0	0
T111	1946	0	0	0
T136	0	6	0	0
T137	0	5	0	0
T138	0	6	0	0
T147	0	3	0	0
T148	884	0	0	0
T149	1868	0	0	0
T150	1829	0	0	0
T151	1710	0	0	0
T152	1434	0	0	0
T153	1130	0	0	0
T154	1648	0	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	12154	0	0
T2	19643	0	0	0
T3	0	150	0	0
T11	0	24	0	0
T28	0	47	0	0
T34	902	11	0	0
T37	2205	11	0	0
T42	634	0	0	0
T43	1920	0	0	0
T44	1269	0	0	0
T45	8285	0	0	0
T46	825	0	0	0
T47	3448	0	0	0
T48	1339	0	0	0
T61	0	20	0	0
T63	0	71	0	0
T94	0	43	0	0
T155	0	22	0	0
T156	0	25	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	6895	0	0
T3	125433	48	0	0
T7	118132	0	0	0
T10	188154	0	0	0
T20	1620	0	0	0
T21	839	0	0	0
T22	1516	0	0	0
T38	107045	0	0	0
T41	0	174	0	0
T49	29703	0	0	0
T51	958	0	0	0
T74	0	194	0	0
T76	0	338	0	0
T157	0	50	0	0
T158	0	7	0	0
T159	0	12	0	0
T160	0	26	0	0
T161	0	61	0	0
T162	0	51	0	0
T163	1488	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	16746	0	0
T11	0	75	0	0
T15	0	103	0	0
T20	1620	117	0	0
T21	839	0	0	0
T22	1516	0	0	0
T23	1519	0	0	0
T24	5038	0	0	0
T25	2163	0	0	0
T26	1986	0	0	0
T27	2180	0	0	0
T28	2073	0	0	0
T41	0	460	0	0
T74	0	725	0	0
T94	2342	0	0	0
T96	0	53	0	0
T136	0	105	0	0
T137	0	122	0	0
T138	0	131	0	0
T147	0	67	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36655700	6860	0	0
T17	307304	0	0	0
T18	136043	0	0	0
T19	518505	0	0	0
T41	176879	277	0	0
T55	0	475	0	0
T56	201094	0	0	0
T73	218921	0	0	0
T74	215491	202	0	0
T76	0	230	0	0
T77	0	133	0	0
T80	1390	0	0	0
T81	1967	0	0	0
T82	1472	0	0	0
T164	0	138	0	0
T165	0	540	0	0
T166	0	293	0	0
T167	0	149	0	0
T168	0	413	0	0