Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T29 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T5 T33 T34 

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T37,T43,T61
1	1	Covered	T5,T33,T34

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	76186096	3004	0	0
g_div2.Div2Whole_A	76186096	3577	0	0
g_div4.Div4Stepped_A	37141547	2935	0	0
g_div4.Div4Whole_A	37141547	3391	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76186096	3004	0	0
T1	18775	0	0	0
T5	3950	8	0	0
T6	2564	0	0	0
T22	0	4	0	0
T29	3163	0	0	0
T30	1995	0	0	0
T31	9033	0	0	0
T32	1153	0	0	0
T33	1604	1	0	0
T34	3612	2	0	0
T37	2118	6	0	0
T43	0	5	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76186096	3577	0	0
T1	18775	0	0	0
T5	3950	11	0	0
T6	2564	0	0	0
T22	0	6	0	0
T26	0	11	0	0
T29	3163	0	0	0
T30	1995	0	0	0
T31	9033	0	0	0
T32	1153	0	0	0
T33	1604	0	0	0
T34	3612	2	0	0
T37	2118	6	0	0
T43	0	5	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	0	4	0	0
T63	0	10	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141547	2935	0	0
T1	9335	0	0	0
T5	2181	8	0	0
T6	1235	0	0	0
T22	0	4	0	0
T29	1542	0	0	0
T30	952	0	0	0
T31	4463	0	0	0
T32	537	0	0	0
T33	1426	1	0	0
T34	1903	2	0	0
T37	1115	6	0	0
T43	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	8	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141547	3391	0	0
T1	9335	0	0	0
T5	2181	11	0	0
T6	1235	0	0	0
T22	0	6	0	0
T26	0	11	0	0
T29	1542	0	0	0
T30	952	0	0	0
T31	4463	0	0	0
T32	537	0	0	0
T33	1426	0	0	0
T34	1903	2	0	0
T37	1115	6	0	0
T43	0	5	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	0	4	0	0
T63	0	9	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T29 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T5 T33 T34 

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T37,T43,T61
1	1	Covered	T5,T33,T34

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	76186096	3004	0	0
g_div2.Div2Whole_A	76186096	3577	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76186096	3004	0	0
T1	18775	0	0	0
T5	3950	8	0	0
T6	2564	0	0	0
T22	0	4	0	0
T29	3163	0	0	0
T30	1995	0	0	0
T31	9033	0	0	0
T32	1153	0	0	0
T33	1604	1	0	0
T34	3612	2	0	0
T37	2118	6	0	0
T43	0	5	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T63	0	9	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76186096	3577	0	0
T1	18775	0	0	0
T5	3950	11	0	0
T6	2564	0	0	0
T22	0	6	0	0
T26	0	11	0	0
T29	3163	0	0	0
T30	1995	0	0	0
T31	9033	0	0	0
T32	1153	0	0	0
T33	1604	0	0	0
T34	3612	2	0	0
T37	2118	6	0	0
T43	0	5	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	0	4	0	0
T63	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

24                        logic step_down;
25         1/1            always_comb step_down = div_step_down_req_i && !scanmode;
           Tests:       T4 T5 T29 
26                      
27                        logic step_up;
28         1/1            always_comb step_up = !step_down;
           Tests:       T5 T33 T34 

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T31
1	0	Covered	T37,T43,T61
1	1	Covered	T5,T33,T34

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	37141547	2935	0	0
g_div4.Div4Whole_A	37141547	3391	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141547	2935	0	0
T1	9335	0	0	0
T5	2181	8	0	0
T6	1235	0	0	0
T22	0	4	0	0
T29	1542	0	0	0
T30	952	0	0	0
T31	4463	0	0	0
T32	537	0	0	0
T33	1426	1	0	0
T34	1903	2	0	0
T37	1115	6	0	0
T43	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	1	0	0
T63	0	8	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141547	3391	0	0
T1	9335	0	0	0
T5	2181	11	0	0
T6	1235	0	0	0
T22	0	6	0	0
T26	0	11	0	0
T29	1542	0	0	0
T30	952	0	0	0
T31	4463	0	0	0
T32	537	0	0	0
T33	1426	0	0	0
T34	1903	2	0	0
T37	1115	6	0	0
T43	0	5	0	0
T60	0	2	0	0
T61	0	3	0	0
T62	0	4	0	0
T63	0	9	0	0