Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	107201721	446	0	0
StatusRise_A	107201721	446	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107201721	446	0	0
T1	57501	0	0	0
T2	58929	0	0	0
T21	0	3	0	0
T30	3225	10	0	0
T31	6771	0	0	0
T32	3456	0	0	0
T33	3006	0	0	0
T34	2706	0	0	0
T37	6615	0	0	0
T42	1902	0	0	0
T43	5760	0	0	0
T48	0	6	0	0
T148	0	2	0	0
T169	0	4	0	0
T170	0	13	0	0
T171	0	16	0	0
T172	0	6	0	0
T173	0	9	0	0
T174	0	5	0	0
T175	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	107201721	446	0	0
T1	57501	0	0	0
T2	58929	0	0	0
T21	0	3	0	0
T30	3225	10	0	0
T31	6771	0	0	0
T32	3456	0	0	0
T33	3006	0	0	0
T34	2706	0	0	0
T37	6615	0	0	0
T42	1902	0	0	0
T43	5760	0	0	0
T48	0	6	0	0
T148	0	2	0	0
T169	0	4	0	0
T170	0	13	0	0
T171	0	16	0	0
T172	0	6	0	0
T173	0	9	0	0
T174	0	5	0	0
T175	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35733907	154	0	0
StatusRise_A	35733907	154	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	154	0	0
T1	19167	0	0	0
T2	19643	0	0	0
T21	0	1	0	0
T30	1075	4	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	0	0	0
T37	2205	0	0	0
T42	634	0	0	0
T43	1920	0	0	0
T48	0	2	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	154	0	0
T1	19167	0	0	0
T2	19643	0	0	0
T21	0	1	0	0
T30	1075	4	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	0	0	0
T37	2205	0	0	0
T42	634	0	0	0
T43	1920	0	0	0
T48	0	2	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35733907	144	0	0
StatusRise_A	35733907	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	144	0	0
T1	19167	0	0	0
T2	19643	0	0	0
T21	0	1	0	0
T30	1075	2	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	0	0	0
T37	2205	0	0	0
T42	634	0	0	0
T43	1920	0	0	0
T48	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	144	0	0
T1	19167	0	0	0
T2	19643	0	0	0
T21	0	1	0	0
T30	1075	2	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	0	0	0
T37	2205	0	0	0
T42	634	0	0	0
T43	1920	0	0	0
T48	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	35733907	148	0	0
StatusRise_A	35733907	148	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	148	0	0
T1	19167	0	0	0
T2	19643	0	0	0
T21	0	1	0	0
T30	1075	4	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	0	0	0
T37	2205	0	0	0
T42	634	0	0	0
T43	1920	0	0	0
T48	0	3	0	0
T148	0	1	0	0
T169	0	2	0	0
T170	0	4	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	4	0	0
T174	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	35733907	148	0	0
T1	19167	0	0	0
T2	19643	0	0	0
T21	0	1	0	0
T30	1075	4	0	0
T31	2257	0	0	0
T32	1152	0	0	0
T33	1002	0	0	0
T34	902	0	0	0
T37	2205	0	0	0
T42	634	0	0	0
T43	1920	0	0	0
T48	0	3	0	0
T148	0	1	0	0
T169	0	2	0	0
T170	0	4	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	4	0	0
T174	0	2	0	0