Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	887572276	32282	0	0
CgEnOn_A	887572276	23062	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	887572276	32282	0	0
T1	211008	3	0	0
T2	149833	0	0	0
T4	32323	7	0	0
T5	25650	3	0	0
T6	16376	6	0	0
T21	0	6	0	0
T29	20231	5	0	0
T30	23234	23	0	0
T31	101398	10	0	0
T32	12808	3	0	0
T33	20534	3	0	0
T34	41012	3	0	0
T37	10371	0	0	0
T41	0	5	0	0
T42	16291	0	0	0
T43	10552	0	0	0
T44	0	1	0	0
T47	0	10	0	0
T48	0	7	0	0
T74	0	5	0	0
T148	0	5	0	0
T169	0	5	0	0
T170	0	25	0	0
T171	0	25	0	0
T172	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	887572276	23062	0	0
T1	211008	0	0	0
T2	149833	0	0	0
T4	32323	4	0	0
T5	25650	0	0	0
T6	16376	3	0	0
T20	0	4	0	0
T21	0	9	0	0
T29	20231	2	0	0
T30	23234	20	0	0
T31	101398	7	0	0
T32	12808	0	0	0
T33	20534	0	0	0
T34	41012	0	0	0
T37	10371	0	0	0
T41	0	4	0	0
T42	16291	0	0	0
T43	10552	0	0	0
T44	0	4	0	0
T46	0	5	0	0
T48	0	10	0	0
T74	0	4	0	0
T96	0	3	0	0
T148	0	5	0	0
T163	0	10	0	0
T169	0	5	0	0
T170	0	25	0	0
T171	0	25	0	0
T172	0	10	0	0
T173	0	2	0	0
T174	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	37141130	161	0	0
CgEnOn_A	37141130	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141130	161	0	0
T1	9334	0	0	0
T2	12695	0	0	0
T21	0	1	0	0
T30	951	2	0	0
T31	4462	0	0	0
T32	537	0	0	0
T33	1426	0	0	0
T34	1902	0	0	0
T37	1115	0	0	0
T41	0	1	0	0
T42	1666	0	0	0
T43	1112	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141130	161	0	0
T1	9334	0	0	0
T2	12695	0	0	0
T21	0	1	0	0
T30	951	2	0	0
T31	4462	0	0	0
T32	537	0	0	0
T33	1426	0	0	0
T34	1902	0	0	0
T37	1115	0	0	0
T41	0	1	0	0
T42	1666	0	0	0
T43	1112	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18570137	161	0	0
CgEnOn_A	18570137	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	161	0	0
T1	4667	0	0	0
T2	6347	0	0	0
T21	0	1	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T37	557	0	0	0
T41	0	1	0	0
T42	833	0	0	0
T43	555	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	161	0	0
T1	4667	0	0	0
T2	6347	0	0	0
T21	0	1	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T37	557	0	0	0
T41	0	1	0	0
T42	833	0	0	0
T43	555	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18570137	161	0	0
CgEnOn_A	18570137	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	161	0	0
T1	4667	0	0	0
T2	6347	0	0	0
T21	0	1	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T37	557	0	0	0
T41	0	1	0	0
T42	833	0	0	0
T43	555	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	161	0	0
T1	4667	0	0	0
T2	6347	0	0	0
T21	0	1	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T37	557	0	0	0
T41	0	1	0	0
T42	833	0	0	0
T43	555	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18570137	161	0	0
CgEnOn_A	18570137	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	161	0	0
T1	4667	0	0	0
T2	6347	0	0	0
T21	0	1	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T37	557	0	0	0
T41	0	1	0	0
T42	833	0	0	0
T43	555	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	161	0	0
T1	4667	0	0	0
T2	6347	0	0	0
T21	0	1	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T37	557	0	0	0
T41	0	1	0	0
T42	833	0	0	0
T43	555	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76185638	161	0	0
CgEnOn_A	76185638	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76185638	161	0	0
T1	18775	0	0	0
T2	25455	0	0	0
T21	0	1	0	0
T30	1995	2	0	0
T31	9032	0	0	0
T32	1152	0	0	0
T33	1604	0	0	0
T34	3611	0	0	0
T37	2117	0	0	0
T41	0	1	0	0
T42	3384	0	0	0
T43	2170	0	0	0
T48	0	1	0	0
T74	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76185638	146	0	0
T1	18775	0	0	0
T2	25455	0	0	0
T21	0	1	0	0
T30	1995	2	0	0
T31	9032	0	0	0
T32	1152	0	0	0
T33	1604	0	0	0
T34	3611	0	0	0
T37	2117	0	0	0
T42	3384	0	0	0
T43	2170	0	0	0
T48	0	1	0	0
T148	0	1	0	0
T169	0	1	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84275427	157	0	0
CgEnOn_A	84275427	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	157	0	0
T1	19558	0	0	0
T2	38517	0	0	0
T21	0	1	0	0
T30	2218	4	0	0
T31	9409	0	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T37	2205	0	0	0
T42	3525	0	0	0
T43	2260	0	0	0
T48	0	2	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	156	0	0
T1	19558	0	0	0
T2	38517	0	0	0
T21	0	1	0	0
T30	2218	4	0	0
T31	9409	0	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T37	2205	0	0	0
T42	3525	0	0	0
T43	2260	0	0	0
T48	0	2	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84275427	157	0	0
CgEnOn_A	84275427	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	157	0	0
T1	19558	0	0	0
T2	38517	0	0	0
T21	0	1	0	0
T30	2218	4	0	0
T31	9409	0	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T37	2205	0	0	0
T42	3525	0	0	0
T43	2260	0	0	0
T48	0	2	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	156	0	0
T1	19558	0	0	0
T2	38517	0	0	0
T21	0	1	0	0
T30	2218	4	0	0
T31	9409	0	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T37	2205	0	0	0
T42	3525	0	0	0
T43	2260	0	0	0
T48	0	2	0	0
T169	0	1	0	0
T170	0	4	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40492815	155	0	0
CgEnOn_A	40492815	148	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40492815	155	0	0
T1	9387	0	0	0
T2	15608	0	0	0
T21	0	1	0	0
T30	1065	4	0	0
T31	4516	0	0	0
T32	576	0	0	0
T33	801	0	0	0
T34	1805	0	0	0
T37	1058	0	0	0
T42	1692	0	0	0
T43	1085	0	0	0
T48	0	3	0	0
T56	0	1	0	0
T148	0	1	0	0
T169	0	2	0	0
T170	0	4	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40492815	148	0	0
T1	9387	0	0	0
T2	15608	0	0	0
T21	0	1	0	0
T30	1065	4	0	0
T31	4516	0	0	0
T32	576	0	0	0
T33	801	0	0	0
T34	1805	0	0	0
T37	1058	0	0	0
T42	1692	0	0	0
T43	1085	0	0	0
T48	0	3	0	0
T148	0	1	0	0
T169	0	2	0	0
T170	0	4	0	0
T171	0	5	0	0
T172	0	2	0	0
T173	0	4	0	0
T174	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T48,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18570137	5305	0	0
CgEnOn_A	18570137	3015	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	5305	0	0
T1	4667	1	0	0
T4	1233	2	0	0
T5	1089	1	0	0
T6	617	2	0	0
T29	771	1	0	0
T30	476	3	0	0
T31	2231	1	0	0
T32	268	1	0	0
T33	713	1	0	0
T34	951	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18570137	3015	0	0
T1	4667	0	0	0
T4	1233	1	0	0
T5	1089	0	0	0
T6	617	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	771	0	0	0
T30	476	2	0	0
T31	2231	0	0	0
T32	268	0	0	0
T33	713	0	0	0
T34	951	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T96	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T48,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	37141130	5350	0	0
CgEnOn_A	37141130	3060	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141130	5350	0	0
T1	9334	1	0	0
T4	2465	2	0	0
T5	2180	1	0	0
T6	1235	2	0	0
T29	1541	1	0	0
T30	951	3	0	0
T31	4462	1	0	0
T32	537	1	0	0
T33	1426	1	0	0
T34	1902	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37141130	3060	0	0
T1	9334	0	0	0
T4	2465	1	0	0
T5	2180	0	0	0
T6	1235	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	1541	0	0	0
T30	951	2	0	0
T31	4462	0	0	0
T32	537	0	0	0
T33	1426	0	0	0
T34	1902	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T96	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T48,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	76185638	5360	0	0
CgEnOn_A	76185638	3055	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76185638	5360	0	0
T1	18775	1	0	0
T4	5051	2	0	0
T5	3950	1	0	0
T6	2563	2	0	0
T29	3162	1	0	0
T30	1995	3	0	0
T31	9032	1	0	0
T32	1152	1	0	0
T33	1604	1	0	0
T34	3611	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	76185638	3055	0	0
T1	18775	0	0	0
T4	5051	1	0	0
T5	3950	0	0	0
T6	2563	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	3162	0	0	0
T30	1995	2	0	0
T31	9032	0	0	0
T32	1152	0	0	0
T33	1604	0	0	0
T34	3611	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T96	0	1	0	0
T163	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T48,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	40492815	5325	0	0
CgEnOn_A	40492815	3018	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40492815	5325	0	0
T1	9387	1	0	0
T4	2526	2	0	0
T5	1975	1	0	0
T6	1281	2	0	0
T29	1581	1	0	0
T30	1065	5	0	0
T31	4516	1	0	0
T32	576	1	0	0
T33	801	1	0	0
T34	1805	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	40492815	3018	0	0
T1	9387	0	0	0
T4	2526	1	0	0
T5	1975	0	0	0
T6	1281	1	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	1581	0	0	0
T30	1065	4	0	0
T31	4516	0	0	0
T32	576	0	0	0
T33	801	0	0	0
T34	1805	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	3	0	0
T96	0	1	0	0
T163	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84275427	2411	0	0
CgEnOn_A	84275427	2410	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2411	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	3294	2	0	0
T30	2218	4	0	0
T31	9409	7	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	10	0	0
T48	0	2	0	0
T59	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2410	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	3294	2	0	0
T30	2218	4	0	0
T31	9409	7	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	10	0	0
T48	0	2	0	0
T59	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84275427	2393	0	0
CgEnOn_A	84275427	2392	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2393	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	3294	2	0	0
T30	2218	4	0	0
T31	9409	6	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	8	0	0
T48	0	2	0	0
T59	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2392	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T29	3294	2	0	0
T30	2218	4	0	0
T31	9409	6	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	8	0	0
T48	0	2	0	0
T59	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Covered	T4,T31,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84275427	2425	0	0
CgEnOn_A	84275427	2424	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2425	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T29	3294	0	0	0
T30	2218	4	0	0
T31	9409	5	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	14	0	0
T48	0	2	0	0
T59	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2424	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	4	0	0
T29	3294	0	0	0
T30	2218	4	0	0
T31	9409	5	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	14	0	0
T48	0	2	0	0
T59	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T45,T48
1	0	Covered	T4,T31,T44
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	84275427	2439	0	0
CgEnOn_A	84275427	2438	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2439	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	2	0	0
T29	3294	0	0	0
T30	2218	4	0	0
T31	9409	8	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	12	0	0
T48	0	2	0	0
T59	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	84275427	2438	0	0
T1	19558	0	0	0
T4	5262	1	0	0
T5	4114	0	0	0
T6	2670	0	0	0
T20	0	1	0	0
T21	0	1	0	0
T23	0	2	0	0
T29	3294	0	0	0
T30	2218	4	0	0
T31	9409	8	0	0
T32	1201	0	0	0
T33	1670	0	0	0
T34	3762	0	0	0
T44	0	1	0	0
T47	0	12	0	0
T48	0	2	0	0
T59	0	7	0	0