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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1009
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T1002 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.3851804114 Aug 28 08:00:53 PM UTC 24 Aug 28 08:00:55 PM UTC 24 11518290 ps
T1003 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.3529455013 Aug 28 08:00:53 PM UTC 24 Aug 28 08:00:55 PM UTC 24 60820287 ps
T1004 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3326421234 Aug 28 08:00:52 PM UTC 24 Aug 28 08:00:55 PM UTC 24 207238512 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3323474963 Aug 28 08:00:52 PM UTC 24 Aug 28 08:00:55 PM UTC 24 262357450 ps
T1005 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1103328517 Aug 28 08:00:52 PM UTC 24 Aug 28 08:00:56 PM UTC 24 404512103 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1401479030 Aug 28 08:00:52 PM UTC 24 Aug 28 08:00:56 PM UTC 24 279959308 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3329654724 Aug 28 08:00:52 PM UTC 24 Aug 28 08:00:56 PM UTC 24 601322020 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.2334086806 Aug 28 08:00:52 PM UTC 24 Aug 28 08:00:57 PM UTC 24 449633956 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.24931483 Aug 28 08:01:08 PM UTC 24 Aug 28 08:01:10 PM UTC 24 21159676 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.2832965056
Short name T1
Test name
Test status
Simulation time 195604742 ps
CPU time 3.59 seconds
Started Aug 28 07:55:23 PM UTC 24
Finished Aug 28 07:55:28 PM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832965056 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2832965056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.2187901994
Short name T11
Test name
Test status
Simulation time 4780279848 ps
CPU time 28.64 seconds
Started Aug 28 07:55:29 PM UTC 24
Finished Aug 28 07:55:59 PM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187901994 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.2187901994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1226132825
Short name T37
Test name
Test status
Simulation time 22077860 ps
CPU time 1.35 seconds
Started Aug 28 07:55:27 PM UTC 24
Finished Aug 28 07:55:29 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226132825 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.1226132825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.3305789929
Short name T41
Test name
Test status
Simulation time 1768819287 ps
CPU time 31.19 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:56:25 PM UTC 24
Peak memory 220456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305789929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3305789929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.1145098736
Short name T4
Test name
Test status
Simulation time 52643033 ps
CPU time 1.56 seconds
Started Aug 28 07:55:19 PM UTC 24
Finished Aug 28 07:55:22 PM UTC 24
Peak memory 209648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145098736 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1145098736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2749088458
Short name T121
Test name
Test status
Simulation time 91060752 ps
CPU time 2.15 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 229020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749088
458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.2749088458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.1436516024
Short name T45
Test name
Test status
Simulation time 331469838 ps
CPU time 3.53 seconds
Started Aug 28 07:55:29 PM UTC 24
Finished Aug 28 07:55:34 PM UTC 24
Peak memory 242604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436516024 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.1436516024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.1126545216
Short name T7
Test name
Test status
Simulation time 1181353232 ps
CPU time 12.89 seconds
Started Aug 28 07:55:37 PM UTC 24
Finished Aug 28 07:55:52 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126545216 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1126545216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.1877569738
Short name T30
Test name
Test status
Simulation time 23378896 ps
CPU time 1.14 seconds
Started Aug 28 07:55:23 PM UTC 24
Finished Aug 28 07:55:26 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877569738 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1877569738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.4226817054
Short name T63
Test name
Test status
Simulation time 28865148 ps
CPU time 1.43 seconds
Started Aug 28 07:55:36 PM UTC 24
Finished Aug 28 07:55:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226817054 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.4226817054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.3931061666
Short name T195
Test name
Test status
Simulation time 24727102 ps
CPU time 1.36 seconds
Started Aug 28 07:56:05 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931061666 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3931061666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1352581870
Short name T108
Test name
Test status
Simulation time 68498209 ps
CPU time 1.7 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:30 PM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352581870 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.1352581870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1512816131
Short name T125
Test name
Test status
Simulation time 133975784 ps
CPU time 2.32 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512816
131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.1512816131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.296322997
Short name T15
Test name
Test status
Simulation time 3448942577 ps
CPU time 25.02 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:56:21 PM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296322997 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.296322997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.560323387
Short name T651
Test name
Test status
Simulation time 2887746927 ps
CPU time 51.84 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:59:10 PM UTC 24
Peak memory 227352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=560323387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.560323387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.426394168
Short name T42
Test name
Test status
Simulation time 35277473 ps
CPU time 1.22 seconds
Started Aug 28 07:55:29 PM UTC 24
Finished Aug 28 07:55:32 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426394168 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.426394168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.1171763692
Short name T95
Test name
Test status
Simulation time 28290983 ps
CPU time 1.17 seconds
Started Aug 28 07:55:56 PM UTC 24
Finished Aug 28 07:55:59 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171763692 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1171763692
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1853807219
Short name T112
Test name
Test status
Simulation time 3523562729 ps
CPU time 12.67 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853807219 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.1853807219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.444861361
Short name T115
Test name
Test status
Simulation time 70230675 ps
CPU time 1.87 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444861361 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.444861361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.1781941963
Short name T3
Test name
Test status
Simulation time 1306665191 ps
CPU time 14.52 seconds
Started Aug 28 07:55:27 PM UTC 24
Finished Aug 28 07:55:43 PM UTC 24
Peak memory 210760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781941963 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1781941963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.1850987552
Short name T43
Test name
Test status
Simulation time 22625327 ps
CPU time 1.34 seconds
Started Aug 28 07:55:30 PM UTC 24
Finished Aug 28 07:55:33 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850987552 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1850987552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3419678239
Short name T126
Test name
Test status
Simulation time 72312942 ps
CPU time 1.65 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419678
239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.3419678239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3172524375
Short name T86
Test name
Test status
Simulation time 21776223 ps
CPU time 1.17 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172524375 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.3172524375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1164155172
Short name T101
Test name
Test status
Simulation time 21878900 ps
CPU time 1.09 seconds
Started Aug 28 07:57:35 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164155172 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.1164155172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.3773762674
Short name T5
Test name
Test status
Simulation time 41165501 ps
CPU time 1.45 seconds
Started Aug 28 07:55:22 PM UTC 24
Finished Aug 28 07:55:25 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773762674 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3773762674
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.654851698
Short name T53
Test name
Test status
Simulation time 2282417132 ps
CPU time 15.37 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654851698 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.654851698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3923514399
Short name T116
Test name
Test status
Simulation time 700124498 ps
CPU time 3.79 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 212668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923514399 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.3923514399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.97266241
Short name T868
Test name
Test status
Simulation time 148853158 ps
CPU time 4.22 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:35 PM UTC 24
Peak memory 212420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97266241 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.97266241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.445346224
Short name T118
Test name
Test status
Simulation time 74719022 ps
CPU time 1.06 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:31 PM UTC 24
Peak memory 212284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445346224 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.445346224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3703496631
Short name T861
Test name
Test status
Simulation time 245105180 ps
CPU time 2.06 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 212452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3703496631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_csr_mem_rw_with_rand_reset.3703496631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.1677741371
Short name T85
Test name
Test status
Simulation time 14863730 ps
CPU time 0.83 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:31 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677741371 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.1677741371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.67253418
Short name T852
Test name
Test status
Simulation time 14097452 ps
CPU time 0.71 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:31 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67253418 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.67253418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.330598567
Short name T88
Test name
Test status
Simulation time 21135273 ps
CPU time 1.26 seconds
Started Aug 28 08:00:29 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305
98567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.330598567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2593095449
Short name T64
Test name
Test status
Simulation time 66927057 ps
CPU time 1.55 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:30 PM UTC 24
Peak memory 211760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593095
449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.2593095449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3400823929
Short name T65
Test name
Test status
Simulation time 101448997 ps
CPU time 2.47 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:30 PM UTC 24
Peak memory 229436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3400823929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_
errors_with_csr_rw.3400823929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.2486287269
Short name T851
Test name
Test status
Simulation time 220773207 ps
CPU time 2.66 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:31 PM UTC 24
Peak memory 212464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486287269 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.2486287269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.2855845024
Short name T92
Test name
Test status
Simulation time 93694821 ps
CPU time 1.79 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855845024 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.2855845024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.330412917
Short name T874
Test name
Test status
Simulation time 655670987 ps
CPU time 7.8 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:39 PM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330412917 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.330412917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3579375825
Short name T855
Test name
Test status
Simulation time 176920952 ps
CPU time 1.21 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579375825 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.3579375825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.978316631
Short name T859
Test name
Test status
Simulation time 121430646 ps
CPU time 1.34 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=978316631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 1.clkmgr_csr_mem_rw_with_rand_reset.978316631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.4121072937
Short name T87
Test name
Test status
Simulation time 17293355 ps
CPU time 0.81 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121072937 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.4121072937
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.275544941
Short name T853
Test name
Test status
Simulation time 38173408 ps
CPU time 0.83 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275544941 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.275544941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.960790921
Short name T866
Test name
Test status
Simulation time 356176702 ps
CPU time 2.44 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9607
90921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.960790921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.261025067
Short name T66
Test name
Test status
Simulation time 43276066 ps
CPU time 1.63 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2610250
67 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.261025067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2458322626
Short name T67
Test name
Test status
Simulation time 87555564 ps
CPU time 2.21 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 212752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2458322626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_
errors_with_csr_rw.2458322626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.484111381
Short name T860
Test name
Test status
Simulation time 31639245 ps
CPU time 1.92 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 212016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484111381 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.484111381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1853295141
Short name T109
Test name
Test status
Simulation time 124713567 ps
CPU time 1.72 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853295141 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.1853295141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.4185006002
Short name T908
Test name
Test status
Simulation time 119228835 ps
CPU time 1.46 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4185006002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_csr_mem_rw_with_rand_reset.4185006002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1828612554
Short name T907
Test name
Test status
Simulation time 120417450 ps
CPU time 1.33 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828612554 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.1828612554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.3082922422
Short name T899
Test name
Test status
Simulation time 27006609 ps
CPU time 0.78 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082922422 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.3082922422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.181730017
Short name T910
Test name
Test status
Simulation time 165518542 ps
CPU time 1.81 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817
30017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.181730017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2312891618
Short name T135
Test name
Test status
Simulation time 229902327 ps
CPU time 2.14 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 221964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2312891618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg
_errors_with_csr_rw.2312891618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.37027270
Short name T894
Test name
Test status
Simulation time 25241919 ps
CPU time 1.56 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37027270 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.37027270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1597422413
Short name T909
Test name
Test status
Simulation time 57578392 ps
CPU time 1.74 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597422413 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.1597422413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1758030200
Short name T919
Test name
Test status
Simulation time 72030627 ps
CPU time 1.17 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:46 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1758030200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_csr_mem_rw_with_rand_reset.1758030200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.4180596686
Short name T918
Test name
Test status
Simulation time 113016819 ps
CPU time 1.16 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:46 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180596686 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.4180596686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.194344128
Short name T915
Test name
Test status
Simulation time 25839223 ps
CPU time 0.67 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:46 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194344128 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.194344128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.256821119
Short name T927
Test name
Test status
Simulation time 178011049 ps
CPU time 1.52 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568
21119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.256821119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2912247739
Short name T134
Test name
Test status
Simulation time 70821707 ps
CPU time 1.68 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912247
739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.2912247739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.974600146
Short name T911
Test name
Test status
Simulation time 62247701 ps
CPU time 1.75 seconds
Started Aug 28 08:00:39 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 211580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=974600146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_
errors_with_csr_rw.974600146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.2403199533
Short name T945
Test name
Test status
Simulation time 37950180 ps
CPU time 2.63 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 212784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403199533 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.2403199533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2765058042
Short name T947
Test name
Test status
Simulation time 88747167 ps
CPU time 2.32 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2765058042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.clkmgr_csr_mem_rw_with_rand_reset.2765058042
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.2164762972
Short name T921
Test name
Test status
Simulation time 21855388 ps
CPU time 1 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 212052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164762972 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.2164762972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.3370749163
Short name T917
Test name
Test status
Simulation time 37272580 ps
CPU time 0.74 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:46 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370749163 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.3370749163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.442348097
Short name T942
Test name
Test status
Simulation time 45226328 ps
CPU time 1.88 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4423
48097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.442348097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3000518572
Short name T922
Test name
Test status
Simulation time 54534610 ps
CPU time 1.37 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000518
572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.3000518572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3682983901
Short name T936
Test name
Test status
Simulation time 83172440 ps
CPU time 1.95 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 220724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3682983901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg
_errors_with_csr_rw.3682983901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.2532336100
Short name T931
Test name
Test status
Simulation time 138037251 ps
CPU time 1.81 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532336100 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.2532336100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2342154973
Short name T948
Test name
Test status
Simulation time 477249019 ps
CPU time 2.67 seconds
Started Aug 28 08:00:44 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 212356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342154973 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.2342154973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.767380249
Short name T928
Test name
Test status
Simulation time 23036715 ps
CPU time 0.97 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=767380249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.clkmgr_csr_mem_rw_with_rand_reset.767380249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.3884779476
Short name T926
Test name
Test status
Simulation time 39458012 ps
CPU time 0.92 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884779476 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.3884779476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.2876773551
Short name T920
Test name
Test status
Simulation time 12724123 ps
CPU time 0.71 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876773551 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.2876773551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.407482177
Short name T930
Test name
Test status
Simulation time 83428608 ps
CPU time 1.2 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074
82177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.407482177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2587571046
Short name T932
Test name
Test status
Simulation time 67780031 ps
CPU time 1.63 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587571
046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.2587571046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.678932541
Short name T935
Test name
Test status
Simulation time 58008413 ps
CPU time 1.63 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 220744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=678932541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_
errors_with_csr_rw.678932541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.115421647
Short name T937
Test name
Test status
Simulation time 255574151 ps
CPU time 1.65 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115421647 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.115421647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2498497171
Short name T934
Test name
Test status
Simulation time 50564080 ps
CPU time 1.09 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2498497171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_csr_mem_rw_with_rand_reset.2498497171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.2239909020
Short name T939
Test name
Test status
Simulation time 98976886 ps
CPU time 1.15 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239909020 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.2239909020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.3356701309
Short name T924
Test name
Test status
Simulation time 16362046 ps
CPU time 0.64 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356701309 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.3356701309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2347792186
Short name T940
Test name
Test status
Simulation time 50721598 ps
CPU time 1.28 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347
792186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.2347792186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.837544547
Short name T944
Test name
Test status
Simulation time 174987371 ps
CPU time 1.83 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8375445
47 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.837544547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.2036062114
Short name T132
Test name
Test status
Simulation time 159808071 ps
CPU time 3.04 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 221956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2036062114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg
_errors_with_csr_rw.2036062114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.991499522
Short name T925
Test name
Test status
Simulation time 240620447 ps
CPU time 3.91 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:50 PM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991499522 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.991499522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2012551521
Short name T954
Test name
Test status
Simulation time 217054050 ps
CPU time 2.8 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 212336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012551521 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.2012551521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4016536299
Short name T950
Test name
Test status
Simulation time 240712788 ps
CPU time 1.96 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4016536299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_csr_mem_rw_with_rand_reset.4016536299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.566127273
Short name T933
Test name
Test status
Simulation time 21781653 ps
CPU time 0.92 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566127273 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.566127273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.300180266
Short name T929
Test name
Test status
Simulation time 11902008 ps
CPU time 0.77 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300180266 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.300180266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1224528477
Short name T943
Test name
Test status
Simulation time 34996987 ps
CPU time 1.18 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224
528477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.1224528477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.984257181
Short name T949
Test name
Test status
Simulation time 314691473 ps
CPU time 2.21 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9842571
81 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.984257181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.947881531
Short name T956
Test name
Test status
Simulation time 413466606 ps
CPU time 2.85 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=947881531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_
errors_with_csr_rw.947881531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.3765881049
Short name T955
Test name
Test status
Simulation time 91283918 ps
CPU time 2.61 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765881049 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.3765881049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2500501552
Short name T113
Test name
Test status
Simulation time 158917658 ps
CPU time 2.95 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500501552 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.2500501552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.1675840478
Short name T952
Test name
Test status
Simulation time 34659644 ps
CPU time 1.82 seconds
Started Aug 28 08:00:46 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 211884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1675840478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_csr_mem_rw_with_rand_reset.1675840478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.2163062409
Short name T941
Test name
Test status
Simulation time 20539239 ps
CPU time 0.86 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163062409 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.2163062409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.1369817196
Short name T938
Test name
Test status
Simulation time 12594726 ps
CPU time 0.83 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:47 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369817196 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.1369817196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1041835310
Short name T946
Test name
Test status
Simulation time 32127390 ps
CPU time 1.14 seconds
Started Aug 28 08:00:46 PM UTC 24
Finished Aug 28 08:00:48 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041
835310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.1041835310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.240119769
Short name T953
Test name
Test status
Simulation time 189973636 ps
CPU time 2.1 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 213012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401197
69 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.240119769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3308557561
Short name T951
Test name
Test status
Simulation time 86227441 ps
CPU time 2 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 228828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3308557561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg
_errors_with_csr_rw.3308557561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.3510219762
Short name T959
Test name
Test status
Simulation time 132590724 ps
CPU time 3.37 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:50 PM UTC 24
Peak memory 212656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510219762 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.3510219762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1892556001
Short name T923
Test name
Test status
Simulation time 348976470 ps
CPU time 3.32 seconds
Started Aug 28 08:00:45 PM UTC 24
Finished Aug 28 08:00:50 PM UTC 24
Peak memory 212668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892556001 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.1892556001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1440670829
Short name T967
Test name
Test status
Simulation time 62203018 ps
CPU time 1.43 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1440670829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_csr_mem_rw_with_rand_reset.1440670829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.888349050
Short name T961
Test name
Test status
Simulation time 27828886 ps
CPU time 0.78 seconds
Started Aug 28 08:00:51 PM UTC 24
Finished Aug 28 08:00:53 PM UTC 24
Peak memory 212044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888349050 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.888349050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.81432903
Short name T960
Test name
Test status
Simulation time 39045429 ps
CPU time 0.81 seconds
Started Aug 28 08:00:51 PM UTC 24
Finished Aug 28 08:00:53 PM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=81432903 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.81432903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1991007534
Short name T965
Test name
Test status
Simulation time 33908528 ps
CPU time 1.14 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991
007534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.1991007534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1764638313
Short name T958
Test name
Test status
Simulation time 597144567 ps
CPU time 2.87 seconds
Started Aug 28 08:00:46 PM UTC 24
Finished Aug 28 08:00:50 PM UTC 24
Peak memory 221592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764638
313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.1764638313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2613106083
Short name T957
Test name
Test status
Simulation time 168009021 ps
CPU time 2.57 seconds
Started Aug 28 08:00:46 PM UTC 24
Finished Aug 28 08:00:49 PM UTC 24
Peak memory 222172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2613106083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg
_errors_with_csr_rw.2613106083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.3277704999
Short name T995
Test name
Test status
Simulation time 154513800 ps
CPU time 2.31 seconds
Started Aug 28 08:00:51 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277704999 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.3277704999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2682606116
Short name T117
Test name
Test status
Simulation time 75254783 ps
CPU time 1.9 seconds
Started Aug 28 08:00:51 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682606116 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.2682606116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2499764497
Short name T970
Test name
Test status
Simulation time 29168315 ps
CPU time 1.14 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2499764497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_csr_mem_rw_with_rand_reset.2499764497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.1281368854
Short name T964
Test name
Test status
Simulation time 26288255 ps
CPU time 0.87 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281368854 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.1281368854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.3926770077
Short name T962
Test name
Test status
Simulation time 17908606 ps
CPU time 0.72 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:53 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926770077 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.3926770077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2946508571
Short name T979
Test name
Test status
Simulation time 145776517 ps
CPU time 1.51 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946
508571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.2946508571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.390097082
Short name T998
Test name
Test status
Simulation time 131875059 ps
CPU time 2.33 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 212616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900970
82 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.390097082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1401479030
Short name T1006
Test name
Test status
Simulation time 279959308 ps
CPU time 3.48 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:56 PM UTC 24
Peak memory 222284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1401479030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg
_errors_with_csr_rw.1401479030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3326421234
Short name T1004
Test name
Test status
Simulation time 207238512 ps
CPU time 2.42 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 212800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326421234 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.3326421234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3329654724
Short name T1007
Test name
Test status
Simulation time 601322020 ps
CPU time 3.59 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:56 PM UTC 24
Peak memory 212652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329654724 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.3329654724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.985422016
Short name T977
Test name
Test status
Simulation time 27515876 ps
CPU time 1.11 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=985422016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.clkmgr_csr_mem_rw_with_rand_reset.985422016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.824397862
Short name T966
Test name
Test status
Simulation time 15293230 ps
CPU time 0.82 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824397862 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.824397862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.2226577274
Short name T963
Test name
Test status
Simulation time 15161762 ps
CPU time 0.66 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226577274 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.2226577274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.845809225
Short name T989
Test name
Test status
Simulation time 110679279 ps
CPU time 1.36 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8458
09225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.845809225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3323474963
Short name T129
Test name
Test status
Simulation time 262357450 ps
CPU time 2.24 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 213016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3323474
963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.3323474963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.974878099
Short name T996
Test name
Test status
Simulation time 157726935 ps
CPU time 1.94 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 220756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=974878099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_
errors_with_csr_rw.974878099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.2334086806
Short name T1008
Test name
Test status
Simulation time 449633956 ps
CPU time 3.89 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:57 PM UTC 24
Peak memory 212464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334086806 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.2334086806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1103328517
Short name T1005
Test name
Test status
Simulation time 404512103 ps
CPU time 2.6 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:56 PM UTC 24
Peak memory 211980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103328517 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.1103328517
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.4179969476
Short name T862
Test name
Test status
Simulation time 37130702 ps
CPU time 1.4 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179969476 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.4179969476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.4275509862
Short name T888
Test name
Test status
Simulation time 263256685 ps
CPU time 6.41 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:38 PM UTC 24
Peak memory 212332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275509862 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.4275509862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1421129387
Short name T856
Test name
Test status
Simulation time 18796031 ps
CPU time 0.98 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421129387 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.1421129387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3676216961
Short name T863
Test name
Test status
Simulation time 22499119 ps
CPU time 1.3 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3676216961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.clkmgr_csr_mem_rw_with_rand_reset.3676216961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.4098741074
Short name T90
Test name
Test status
Simulation time 27040050 ps
CPU time 1.23 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098741074 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.4098741074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.3378990924
Short name T858
Test name
Test status
Simulation time 141044007 ps
CPU time 1.07 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378990924 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.3378990924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1773914100
Short name T91
Test name
Test status
Simulation time 63371097 ps
CPU time 1.24 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773
914100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.1773914100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2334932976
Short name T70
Test name
Test status
Simulation time 97225531 ps
CPU time 2.36 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 221968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334932
976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.2334932976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1889641431
Short name T69
Test name
Test status
Simulation time 133336365 ps
CPU time 2.38 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 221976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1889641431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_
errors_with_csr_rw.1889641431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.2121872225
Short name T867
Test name
Test status
Simulation time 83879647 ps
CPU time 2.73 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:34 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121872225 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.2121872225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3309486065
Short name T110
Test name
Test status
Simulation time 130654725 ps
CPU time 2.09 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 212396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309486065 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.3309486065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.1374086396
Short name T971
Test name
Test status
Simulation time 14221141 ps
CPU time 0.72 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374086396 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.1374086396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.1298581907
Short name T973
Test name
Test status
Simulation time 15645592 ps
CPU time 0.78 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298581907 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.1298581907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.2854979078
Short name T969
Test name
Test status
Simulation time 22335203 ps
CPU time 0.69 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854979078 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.2854979078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.2312781036
Short name T972
Test name
Test status
Simulation time 21652669 ps
CPU time 0.7 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312781036 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.2312781036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.3112962767
Short name T974
Test name
Test status
Simulation time 45048443 ps
CPU time 0.84 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112962767 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.3112962767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.167592713
Short name T968
Test name
Test status
Simulation time 17635379 ps
CPU time 0.64 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167592713 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.167592713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.1462133188
Short name T982
Test name
Test status
Simulation time 100378527 ps
CPU time 1.01 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462133188 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.1462133188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.2973246673
Short name T976
Test name
Test status
Simulation time 39939429 ps
CPU time 0.75 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973246673 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.2973246673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.1942458669
Short name T975
Test name
Test status
Simulation time 23653743 ps
CPU time 0.69 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942458669 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.1942458669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.2323433419
Short name T978
Test name
Test status
Simulation time 21282179 ps
CPU time 0.79 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323433419 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.2323433419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3086450960
Short name T883
Test name
Test status
Simulation time 70082504 ps
CPU time 2.18 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086450960 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.3086450960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3553158118
Short name T896
Test name
Test status
Simulation time 1688686228 ps
CPU time 8.33 seconds
Started Aug 28 08:00:31 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553158118 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.3553158118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1990946602
Short name T864
Test name
Test status
Simulation time 21463872 ps
CPU time 1.16 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990946602 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.1990946602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.4288070080
Short name T876
Test name
Test status
Simulation time 123792946 ps
CPU time 1.79 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4288070080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_csr_mem_rw_with_rand_reset.4288070080
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.744664926
Short name T93
Test name
Test status
Simulation time 62175348 ps
CPU time 1.14 seconds
Started Aug 28 08:00:31 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744664926 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.744664926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.587269228
Short name T857
Test name
Test status
Simulation time 12159743 ps
CPU time 0.78 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:32 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587269228 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.587269228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3342399261
Short name T872
Test name
Test status
Simulation time 61934061 ps
CPU time 1.66 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342
399261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.3342399261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.532424625
Short name T68
Test name
Test status
Simulation time 99041348 ps
CPU time 1.63 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5324246
25 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.532424625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2275058526
Short name T72
Test name
Test status
Simulation time 90065169 ps
CPU time 1.86 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 228820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2275058526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_
errors_with_csr_rw.2275058526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.3008676863
Short name T865
Test name
Test status
Simulation time 140755364 ps
CPU time 1.8 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008676863 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.3008676863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.904087894
Short name T177
Test name
Test status
Simulation time 54485352 ps
CPU time 1.85 seconds
Started Aug 28 08:00:30 PM UTC 24
Finished Aug 28 08:00:33 PM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904087894 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.904087894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.825094290
Short name T980
Test name
Test status
Simulation time 12525459 ps
CPU time 0.74 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825094290 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.825094290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.2864589011
Short name T983
Test name
Test status
Simulation time 31908810 ps
CPU time 0.87 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864589011 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.2864589011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.1889859451
Short name T988
Test name
Test status
Simulation time 67116292 ps
CPU time 0.78 seconds
Started Aug 28 08:00:52 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889859451 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.1889859451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.2716567415
Short name T981
Test name
Test status
Simulation time 14612258 ps
CPU time 0.73 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716567415 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.2716567415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.769441781
Short name T986
Test name
Test status
Simulation time 31501753 ps
CPU time 0.78 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769441781 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.769441781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.3180747038
Short name T984
Test name
Test status
Simulation time 10980297 ps
CPU time 0.67 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180747038 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.3180747038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.4116845033
Short name T987
Test name
Test status
Simulation time 17346791 ps
CPU time 0.75 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116845033 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.4116845033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.4022391440
Short name T990
Test name
Test status
Simulation time 36265797 ps
CPU time 0.77 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022391440 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.4022391440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.3358840026
Short name T985
Test name
Test status
Simulation time 21157477 ps
CPU time 0.64 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358840026 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.3358840026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.3786348458
Short name T994
Test name
Test status
Simulation time 10998180 ps
CPU time 0.73 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786348458 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.3786348458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2893160893
Short name T877
Test name
Test status
Simulation time 67950185 ps
CPU time 1.3 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893160893 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.2893160893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.4146853075
Short name T891
Test name
Test status
Simulation time 354962685 ps
CPU time 4.69 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:39 PM UTC 24
Peak memory 212528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146853075 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.4146853075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.4090215793
Short name T871
Test name
Test status
Simulation time 16502766 ps
CPU time 0.9 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090215793 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.4090215793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2968043440
Short name T878
Test name
Test status
Simulation time 64391078 ps
CPU time 1.17 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2968043440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.clkmgr_csr_mem_rw_with_rand_reset.2968043440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.1305036967
Short name T870
Test name
Test status
Simulation time 16247650 ps
CPU time 0.79 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305036967 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.1305036967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.262942168
Short name T869
Test name
Test status
Simulation time 14125921 ps
CPU time 0.7 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:35 PM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262942168 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.262942168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1219648033
Short name T886
Test name
Test status
Simulation time 287047683 ps
CPU time 2.15 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 212212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219
648033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.1219648033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3064640163
Short name T71
Test name
Test status
Simulation time 59194855 ps
CPU time 1.76 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 220756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3064640163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_
errors_with_csr_rw.3064640163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.1711972458
Short name T887
Test name
Test status
Simulation time 119518607 ps
CPU time 3.03 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:38 PM UTC 24
Peak memory 212720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711972458 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.1711972458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2561945976
Short name T114
Test name
Test status
Simulation time 228408030 ps
CPU time 2.64 seconds
Started Aug 28 08:00:33 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561945976 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.2561945976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.3658500252
Short name T1000
Test name
Test status
Simulation time 39728813 ps
CPU time 0.89 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658500252 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.3658500252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.2981131121
Short name T993
Test name
Test status
Simulation time 36955590 ps
CPU time 0.69 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981131121 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.2981131121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.279183350
Short name T991
Test name
Test status
Simulation time 27800792 ps
CPU time 0.62 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279183350 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.279183350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.3529455013
Short name T1003
Test name
Test status
Simulation time 60820287 ps
CPU time 0.95 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529455013 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.3529455013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.3179234380
Short name T992
Test name
Test status
Simulation time 13786895 ps
CPU time 0.71 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179234380 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.3179234380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.3184257636
Short name T997
Test name
Test status
Simulation time 11736206 ps
CPU time 0.71 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184257636 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.3184257636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.3738808730
Short name T1001
Test name
Test status
Simulation time 46673174 ps
CPU time 0.75 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738808730 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.3738808730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.1941231698
Short name T999
Test name
Test status
Simulation time 36897981 ps
CPU time 0.68 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941231698 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.1941231698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.3851804114
Short name T1002
Test name
Test status
Simulation time 11518290 ps
CPU time 0.73 seconds
Started Aug 28 08:00:53 PM UTC 24
Finished Aug 28 08:00:55 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851804114 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.3851804114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.24931483
Short name T1009
Test name
Test status
Simulation time 21159676 ps
CPU time 0.79 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:10 PM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24931483 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.24931483
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3002381773
Short name T882
Test name
Test status
Simulation time 79251114 ps
CPU time 1.33 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3002381773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_csr_mem_rw_with_rand_reset.3002381773
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.266279751
Short name T880
Test name
Test status
Simulation time 60247742 ps
CPU time 1.19 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266279751 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.266279751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.2002683511
Short name T873
Test name
Test status
Simulation time 21091196 ps
CPU time 0.82 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002683511 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.2002683511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1789177016
Short name T884
Test name
Test status
Simulation time 51290183 ps
CPU time 1.57 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789
177016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.1789177016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.673064960
Short name T122
Test name
Test status
Simulation time 394730114 ps
CPU time 2.45 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6730649
60 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.673064960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1496276013
Short name T131
Test name
Test status
Simulation time 84834056 ps
CPU time 1.76 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 211636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1496276013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_
errors_with_csr_rw.1496276013
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.641564240
Short name T914
Test name
Test status
Simulation time 1691373807 ps
CPU time 8.29 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:43 PM UTC 24
Peak memory 212456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641564240 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.641564240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.317818115
Short name T893
Test name
Test status
Simulation time 32561898 ps
CPU time 1.14 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=317818115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 6.clkmgr_csr_mem_rw_with_rand_reset.317818115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.264716770
Short name T881
Test name
Test status
Simulation time 66205294 ps
CPU time 0.99 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264716770 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.264716770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.3984858239
Short name T879
Test name
Test status
Simulation time 40997132 ps
CPU time 0.97 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:36 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984858239 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.3984858239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.11737832
Short name T885
Test name
Test status
Simulation time 92904581 ps
CPU time 1.25 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173
7832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.11737832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2008052508
Short name T123
Test name
Test status
Simulation time 282142301 ps
CPU time 2.39 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:38 PM UTC 24
Peak memory 212620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008052
508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.2008052508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2738210343
Short name T133
Test name
Test status
Simulation time 462420676 ps
CPU time 3.73 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:39 PM UTC 24
Peak memory 222300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2738210343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_
errors_with_csr_rw.2738210343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.1081519576
Short name T889
Test name
Test status
Simulation time 91181304 ps
CPU time 2.7 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:38 PM UTC 24
Peak memory 212712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081519576 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.1081519576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2129237232
Short name T178
Test name
Test status
Simulation time 248552114 ps
CPU time 3.41 seconds
Started Aug 28 08:00:34 PM UTC 24
Finished Aug 28 08:00:39 PM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129237232 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.2129237232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2119897383
Short name T897
Test name
Test status
Simulation time 218020184 ps
CPU time 1.5 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2119897383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.clkmgr_csr_mem_rw_with_rand_reset.2119897383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.772358081
Short name T892
Test name
Test status
Simulation time 16818497 ps
CPU time 0.86 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772358081 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.772358081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.2585571401
Short name T890
Test name
Test status
Simulation time 16619156 ps
CPU time 0.67 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:39 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585571401 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.2585571401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.43794648
Short name T901
Test name
Test status
Simulation time 105097951 ps
CPU time 1.68 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4379
4648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.43794648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3452607707
Short name T128
Test name
Test status
Simulation time 265256347 ps
CPU time 2.92 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 221972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3452607707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_
errors_with_csr_rw.3452607707
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.3866601406
Short name T916
Test name
Test status
Simulation time 1550084683 ps
CPU time 7.19 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:46 PM UTC 24
Peak memory 212544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866601406 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.3866601406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2182827292
Short name T900
Test name
Test status
Simulation time 123265027 ps
CPU time 1.86 seconds
Started Aug 28 08:00:37 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2182827292 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.2182827292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1964706313
Short name T898
Test name
Test status
Simulation time 42566518 ps
CPU time 1 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1964706313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_csr_mem_rw_with_rand_reset.1964706313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.4021805897
Short name T89
Test name
Test status
Simulation time 167176462 ps
CPU time 1.32 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 210896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021805897 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.4021805897
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.3547442212
Short name T895
Test name
Test status
Simulation time 13604561 ps
CPU time 0.78 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547442212 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.3547442212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.408580278
Short name T902
Test name
Test status
Simulation time 94550036 ps
CPU time 1.44 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085
80278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.408580278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1412206569
Short name T124
Test name
Test status
Simulation time 206477580 ps
CPU time 1.9 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412206
569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.1412206569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.4008019014
Short name T130
Test name
Test status
Simulation time 143399942 ps
CPU time 2.97 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 212808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4008019014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_
errors_with_csr_rw.4008019014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.1455058274
Short name T905
Test name
Test status
Simulation time 30003732 ps
CPU time 1.98 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455058274 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.1455058274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.4026129453
Short name T912
Test name
Test status
Simulation time 516832707 ps
CPU time 3.9 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:43 PM UTC 24
Peak memory 212420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026129453 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.4026129453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.4209738749
Short name T903
Test name
Test status
Simulation time 47021175 ps
CPU time 1.46 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4209738749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_csr_mem_rw_with_rand_reset.4209738749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.2450952639
Short name T875
Test name
Test status
Simulation time 17741896 ps
CPU time 0.83 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 212120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450952639 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.2450952639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.89051100
Short name T854
Test name
Test status
Simulation time 33168643 ps
CPU time 1.01 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 211488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89051100 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.89051100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1820517378
Short name T904
Test name
Test status
Simulation time 97271903 ps
CPU time 1.67 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820
517378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.1820517378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.345210272
Short name T127
Test name
Test status
Simulation time 132726997 ps
CPU time 2.15 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 229112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452102
72 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.345210272
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2672133944
Short name T913
Test name
Test status
Simulation time 545328338 ps
CPU time 4.17 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:43 PM UTC 24
Peak memory 212624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2672133944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_
errors_with_csr_rw.2672133944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.763539249
Short name T906
Test name
Test status
Simulation time 28121334 ps
CPU time 1.77 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763539249 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.763539249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.388722277
Short name T176
Test name
Test status
Simulation time 99143446 ps
CPU time 1.85 seconds
Started Aug 28 08:00:38 PM UTC 24
Finished Aug 28 08:00:41 PM UTC 24
Peak memory 211888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388722277 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.388722277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.217725908
Short name T34
Test name
Test status
Simulation time 37643574 ps
CPU time 1.3 seconds
Started Aug 28 07:55:27 PM UTC 24
Finished Aug 28 07:55:29 PM UTC 24
Peak memory 210112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217725908 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.217725908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.1679343113
Short name T2
Test name
Test status
Simulation time 385198764 ps
CPU time 5.03 seconds
Started Aug 28 07:55:23 PM UTC 24
Finished Aug 28 07:55:29 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679343113 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.1679343113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.1211854221
Short name T31
Test name
Test status
Simulation time 94112923 ps
CPU time 1.92 seconds
Started Aug 28 07:55:24 PM UTC 24
Finished Aug 28 07:55:28 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211854221 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.1211854221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.69789306
Short name T33
Test name
Test status
Simulation time 16730157 ps
CPU time 1.11 seconds
Started Aug 28 07:55:26 PM UTC 24
Finished Aug 28 07:55:28 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69789306 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.69789306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.3161408135
Short name T32
Test name
Test status
Simulation time 12035748 ps
CPU time 1.04 seconds
Started Aug 28 07:55:26 PM UTC 24
Finished Aug 28 07:55:28 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161408135
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.3161408135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.4102288964
Short name T6
Test name
Test status
Simulation time 26720926 ps
CPU time 1.17 seconds
Started Aug 28 07:55:23 PM UTC 24
Finished Aug 28 07:55:26 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102288964 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.4102288964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.3772710310
Short name T17
Test name
Test status
Simulation time 3073070602 ps
CPU time 54.84 seconds
Started Aug 28 07:55:29 PM UTC 24
Finished Aug 28 07:56:26 PM UTC 24
Peak memory 227536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772710310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.3772710310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.1847710467
Short name T29
Test name
Test status
Simulation time 32964107 ps
CPU time 1.31 seconds
Started Aug 28 07:55:23 PM UTC 24
Finished Aug 28 07:55:26 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847710467 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.1847710467
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.611558709
Short name T51
Test name
Test status
Simulation time 47975009 ps
CPU time 1.22 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:55 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611558709 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.611558709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2734015516
Short name T60
Test name
Test status
Simulation time 20536353 ps
CPU time 1.2 seconds
Started Aug 28 07:55:36 PM UTC 24
Finished Aug 28 07:55:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734015516 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.2734015516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.4281897018
Short name T48
Test name
Test status
Simulation time 14115497 ps
CPU time 1.08 seconds
Started Aug 28 07:55:35 PM UTC 24
Finished Aug 28 07:55:37 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281897018 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.4281897018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.3020333133
Short name T10
Test name
Test status
Simulation time 1881572069 ps
CPU time 23.06 seconds
Started Aug 28 07:55:30 PM UTC 24
Finished Aug 28 07:55:55 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020333133 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3020333133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.2363944099
Short name T38
Test name
Test status
Simulation time 2184588622 ps
CPU time 17.2 seconds
Started Aug 28 07:55:32 PM UTC 24
Finished Aug 28 07:55:51 PM UTC 24
Peak memory 210784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363944099 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.2363944099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.4029691325
Short name T59
Test name
Test status
Simulation time 25190394 ps
CPU time 1.41 seconds
Started Aug 28 07:55:35 PM UTC 24
Finished Aug 28 07:55:38 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029691325 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.4029691325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3014742205
Short name T62
Test name
Test status
Simulation time 21667203 ps
CPU time 1.24 seconds
Started Aug 28 07:55:36 PM UTC 24
Finished Aug 28 07:55:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014742205
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.3014742205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.637384462
Short name T61
Test name
Test status
Simulation time 27828913 ps
CPU time 1.28 seconds
Started Aug 28 07:55:36 PM UTC 24
Finished Aug 28 07:55:39 PM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637384462 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.637384462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.3312229443
Short name T46
Test name
Test status
Simulation time 22322039 ps
CPU time 1 seconds
Started Aug 28 07:55:32 PM UTC 24
Finished Aug 28 07:55:35 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3312229443 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.3312229443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.171710738
Short name T49
Test name
Test status
Simulation time 297059000 ps
CPU time 5.11 seconds
Started Aug 28 07:55:37 PM UTC 24
Finished Aug 28 07:55:44 PM UTC 24
Peak memory 242808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171710738 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.171710738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.2973036522
Short name T44
Test name
Test status
Simulation time 115419375 ps
CPU time 1.94 seconds
Started Aug 28 07:55:30 PM UTC 24
Finished Aug 28 07:55:34 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973036522 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2973036522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.3472367334
Short name T18
Test name
Test status
Simulation time 7558090200 ps
CPU time 35.96 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:56:30 PM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472367334 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.3472367334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.2903663342
Short name T47
Test name
Test status
Simulation time 137984314 ps
CPU time 1.86 seconds
Started Aug 28 07:55:33 PM UTC 24
Finished Aug 28 07:55:37 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903663342 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2903663342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.3590173884
Short name T238
Test name
Test status
Simulation time 15152091 ps
CPU time 0.77 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:38 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590173884 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.3590173884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.3677172315
Short name T175
Test name
Test status
Simulation time 68175886 ps
CPU time 0.96 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677172315 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3677172315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.2558698999
Short name T237
Test name
Test status
Simulation time 90771680 ps
CPU time 1.28 seconds
Started Aug 28 07:57:35 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558698999 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.2558698999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.4021538378
Short name T232
Test name
Test status
Simulation time 16762765 ps
CPU time 0.85 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:36 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021538378 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.4021538378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.260764649
Short name T287
Test name
Test status
Simulation time 1613773546 ps
CPU time 9.13 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=260764649 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.260764649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.595723363
Short name T266
Test name
Test status
Simulation time 1225485629 ps
CPU time 6.56 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:42 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595723363 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.595723363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.4160919431
Short name T235
Test name
Test status
Simulation time 23039986 ps
CPU time 0.97 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160919431 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.4160919431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3354612007
Short name T236
Test name
Test status
Simulation time 21908423 ps
CPU time 1.02 seconds
Started Aug 28 07:57:35 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354612007
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.3354612007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.228118618
Short name T210
Test name
Test status
Simulation time 86121413 ps
CPU time 1.25 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=228118618 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.228118618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.129820731
Short name T233
Test name
Test status
Simulation time 35650038 ps
CPU time 0.88 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:36 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129820731 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.129820731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.184104071
Short name T9
Test name
Test status
Simulation time 1329105993 ps
CPU time 8.1 seconds
Started Aug 28 07:57:35 PM UTC 24
Finished Aug 28 07:57:44 PM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184104071 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.184104071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.3370775797
Short name T231
Test name
Test status
Simulation time 29239774 ps
CPU time 0.93 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:36 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370775797 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.3370775797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.3990449923
Short name T140
Test name
Test status
Simulation time 5422996074 ps
CPU time 28.18 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990449923 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.3990449923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.2210024323
Short name T652
Test name
Test status
Simulation time 5076474186 ps
CPU time 93.13 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:59:11 PM UTC 24
Peak memory 220428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210024323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.2210024323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.489160628
Short name T234
Test name
Test status
Simulation time 26839397 ps
CPU time 0.95 seconds
Started Aug 28 07:57:34 PM UTC 24
Finished Aug 28 07:57:37 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489160628 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.489160628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.4001926808
Short name T247
Test name
Test status
Simulation time 23961671 ps
CPU time 1.14 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001926808 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.4001926808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.3299513842
Short name T103
Test name
Test status
Simulation time 77656553 ps
CPU time 1.2 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299513842 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.3299513842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.3917494257
Short name T255
Test name
Test status
Simulation time 166277443 ps
CPU time 1.59 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 208956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917494257 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3917494257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.723351445
Short name T241
Test name
Test status
Simulation time 29759567 ps
CPU time 0.94 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723351445 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.723351445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.3421311477
Short name T242
Test name
Test status
Simulation time 68100603 ps
CPU time 1.24 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421311477 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.3421311477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.1177862424
Short name T265
Test name
Test status
Simulation time 892312497 ps
CPU time 4.58 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:42 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177862424 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1177862424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.2526170110
Short name T260
Test name
Test status
Simulation time 377516144 ps
CPU time 3.85 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:41 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526170110 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.2526170110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.3110381783
Short name T240
Test name
Test status
Simulation time 14530504 ps
CPU time 0.81 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:38 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110381783 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.3110381783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.2588406242
Short name T246
Test name
Test status
Simulation time 53234273 ps
CPU time 1.2 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588406242
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.2588406242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.433002715
Short name T245
Test name
Test status
Simulation time 44795815 ps
CPU time 1.12 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 209992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433002715 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.433002715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.1884685147
Short name T244
Test name
Test status
Simulation time 63778316 ps
CPU time 1.25 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884685147 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1884685147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.3992207172
Short name T160
Test name
Test status
Simulation time 980290200 ps
CPU time 6.98 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992207172 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3992207172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.1014866639
Short name T137
Test name
Test status
Simulation time 21550681 ps
CPU time 0.95 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:38 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014866639 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1014866639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.2870510341
Short name T438
Test name
Test status
Simulation time 3620965182 ps
CPU time 33.85 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870510341 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.2870510341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.510226035
Short name T620
Test name
Test status
Simulation time 6211155325 ps
CPU time 72.01 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:58:50 PM UTC 24
Peak memory 220520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510226035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.510226035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.2649436987
Short name T243
Test name
Test status
Simulation time 74286677 ps
CPU time 1.18 seconds
Started Aug 28 07:57:36 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649436987 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2649436987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.1413815823
Short name T258
Test name
Test status
Simulation time 59876870 ps
CPU time 1.03 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:41 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413815823 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.1413815823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.462849267
Short name T104
Test name
Test status
Simulation time 15146176 ps
CPU time 1.05 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462849267 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.462849267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.3114611395
Short name T249
Test name
Test status
Simulation time 33513011 ps
CPU time 0.93 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114611395 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3114611395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.3183968924
Short name T256
Test name
Test status
Simulation time 64126897 ps
CPU time 1.09 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183968924 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.3183968924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.1784049461
Short name T250
Test name
Test status
Simulation time 16438630 ps
CPU time 1.09 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784049461 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1784049461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.3230298931
Short name T331
Test name
Test status
Simulation time 1402100223 ps
CPU time 14.73 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:53 PM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230298931 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3230298931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.3451174829
Short name T334
Test name
Test status
Simulation time 2304603067 ps
CPU time 15.52 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451174829 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.3451174829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.2221706621
Short name T254
Test name
Test status
Simulation time 18604388 ps
CPU time 1.03 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221706621 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.2221706621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3925352813
Short name T251
Test name
Test status
Simulation time 15313068 ps
CPU time 0.91 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925352813
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.3925352813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.1892743814
Short name T253
Test name
Test status
Simulation time 23583533 ps
CPU time 1.01 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892743814
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.1892743814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.3810009639
Short name T248
Test name
Test status
Simulation time 43109766 ps
CPU time 0.95 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810009639 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3810009639
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.2879433506
Short name T159
Test name
Test status
Simulation time 264164922 ps
CPU time 2.6 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879433506 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2879433506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.2995260990
Short name T138
Test name
Test status
Simulation time 205716884 ps
CPU time 1.71 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:40 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995260990 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2995260990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.3911863220
Short name T374
Test name
Test status
Simulation time 2796431654 ps
CPU time 20.21 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:58:00 PM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911863220 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3911863220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.50974122
Short name T653
Test name
Test status
Simulation time 13650412474 ps
CPU time 91.31 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:59:12 PM UTC 24
Peak memory 224424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50974122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.50974122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.2175006306
Short name T252
Test name
Test status
Simulation time 20836842 ps
CPU time 1.07 seconds
Started Aug 28 07:57:37 PM UTC 24
Finished Aug 28 07:57:39 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175006306 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2175006306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.1371137956
Short name T272
Test name
Test status
Simulation time 52184618 ps
CPU time 1.29 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371137956 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.1371137956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2719398053
Short name T105
Test name
Test status
Simulation time 56335418 ps
CPU time 1.14 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719398053 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2719398053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.2730893635
Short name T259
Test name
Test status
Simulation time 16068685 ps
CPU time 0.93 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:41 PM UTC 24
Peak memory 209080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730893635 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2730893635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.3316817658
Short name T269
Test name
Test status
Simulation time 18099835 ps
CPU time 1.03 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316817658 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.3316817658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.1841510960
Short name T267
Test name
Test status
Simulation time 319917775 ps
CPU time 2.06 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:42 PM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841510960 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1841510960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.3399276065
Short name T349
Test name
Test status
Simulation time 2259985305 ps
CPU time 14.45 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:55 PM UTC 24
Peak memory 210748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399276065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3399276065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.3005598685
Short name T284
Test name
Test status
Simulation time 379529205 ps
CPU time 3.76 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:44 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005598685 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.3005598685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.1070156257
Short name T268
Test name
Test status
Simulation time 289202871 ps
CPU time 2.13 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:42 PM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070156257 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.1070156257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1031860102
Short name T271
Test name
Test status
Simulation time 27577597 ps
CPU time 1.22 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 208980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031860102
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.1031860102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3561395144
Short name T263
Test name
Test status
Simulation time 87924366 ps
CPU time 1.32 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:42 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561395144
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.3561395144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.1517846963
Short name T262
Test name
Test status
Simulation time 45560176 ps
CPU time 1.1 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:41 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517846963 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1517846963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.1848362627
Short name T297
Test name
Test status
Simulation time 624988440 ps
CPU time 3.59 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848362627 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1848362627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.2176426189
Short name T261
Test name
Test status
Simulation time 26415089 ps
CPU time 1.13 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:41 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176426189 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2176426189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.1887188740
Short name T444
Test name
Test status
Simulation time 3145114320 ps
CPU time 30.1 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887188740 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.1887188740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.1561691399
Short name T77
Test name
Test status
Simulation time 2871470952 ps
CPU time 32.54 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 220652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561691399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1561691399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.3716164717
Short name T264
Test name
Test status
Simulation time 158617153 ps
CPU time 1.59 seconds
Started Aug 28 07:57:39 PM UTC 24
Finished Aug 28 07:57:42 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716164717 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3716164717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.21188328
Short name T282
Test name
Test status
Simulation time 117610057 ps
CPU time 1.17 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:44 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21188328 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.21188328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1475946059
Short name T106
Test name
Test status
Simulation time 19033774 ps
CPU time 1.21 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:44 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475946059 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.1475946059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.748907825
Short name T278
Test name
Test status
Simulation time 45998499 ps
CPU time 1.14 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748907825 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.748907825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.330950225
Short name T280
Test name
Test status
Simulation time 25412610 ps
CPU time 1.02 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330950225 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.330950225
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.351984032
Short name T277
Test name
Test status
Simulation time 27699610 ps
CPU time 1.18 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351984032 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.351984032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.1439860337
Short name T397
Test name
Test status
Simulation time 2240637967 ps
CPU time 23.82 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439860337 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1439860337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.1864968732
Short name T342
Test name
Test status
Simulation time 2506712879 ps
CPU time 11.92 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864968732 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.1864968732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.3450170454
Short name T281
Test name
Test status
Simulation time 38445956 ps
CPU time 1.19 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:44 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3450170454 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.3450170454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.944768341
Short name T275
Test name
Test status
Simulation time 49050011 ps
CPU time 1.1 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944768341 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.944768341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.1969867919
Short name T279
Test name
Test status
Simulation time 62370089 ps
CPU time 1.13 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 209584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969867919
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.1969867919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.3089792822
Short name T274
Test name
Test status
Simulation time 14117244 ps
CPU time 0.94 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089792822 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3089792822
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.779119977
Short name T299
Test name
Test status
Simulation time 658788763 ps
CPU time 4.21 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779119977 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.779119977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.804388762
Short name T276
Test name
Test status
Simulation time 62546461 ps
CPU time 1.41 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:43 PM UTC 24
Peak memory 209752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804388762 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.804388762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.1221008304
Short name T355
Test name
Test status
Simulation time 1270760357 ps
CPU time 13.56 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221008304 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.1221008304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.930931043
Short name T78
Test name
Test status
Simulation time 2303961850 ps
CPU time 24.98 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 227316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930931043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.930931043
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.661751839
Short name T283
Test name
Test status
Simulation time 53781670 ps
CPU time 1.54 seconds
Started Aug 28 07:57:41 PM UTC 24
Finished Aug 28 07:57:44 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661751839 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.661751839
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.2877727649
Short name T300
Test name
Test status
Simulation time 23567029 ps
CPU time 1.06 seconds
Started Aug 28 07:57:44 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877727649 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.2877727649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.89309420
Short name T295
Test name
Test status
Simulation time 26557525 ps
CPU time 1.15 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89309420 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.89309420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.3276656793
Short name T293
Test name
Test status
Simulation time 131459027 ps
CPU time 1.26 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276656793 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3276656793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.2723294797
Short name T302
Test name
Test status
Simulation time 39773154 ps
CPU time 1.36 seconds
Started Aug 28 07:57:44 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723294797 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.2723294797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.3305280
Short name T288
Test name
Test status
Simulation time 36253784 ps
CPU time 1.02 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 207964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305280 -assert nopostproc +UVM_TESTNAME=clkmg
r_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3305280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.1562639850
Short name T360
Test name
Test status
Simulation time 2134320074 ps
CPU time 12.84 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562639850 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1562639850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.725503527
Short name T316
Test name
Test status
Simulation time 1602527349 ps
CPU time 6.01 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:50 PM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=725503527 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.725503527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.275162328
Short name T294
Test name
Test status
Simulation time 28800446 ps
CPU time 1.25 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275162328 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.275162328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3507070508
Short name T292
Test name
Test status
Simulation time 33682572 ps
CPU time 1.08 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507070508
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.3507070508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3766887784
Short name T290
Test name
Test status
Simulation time 12158799 ps
CPU time 0.96 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766887784
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.3766887784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.3026665133
Short name T291
Test name
Test status
Simulation time 39499161 ps
CPU time 1.11 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026665133 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3026665133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.4105284393
Short name T161
Test name
Test status
Simulation time 957463627 ps
CPU time 6.73 seconds
Started Aug 28 07:57:44 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105284393 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.4105284393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.1502345085
Short name T289
Test name
Test status
Simulation time 37276564 ps
CPU time 1.11 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 207540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502345085 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1502345085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.2772258497
Short name T650
Test name
Test status
Simulation time 11516122969 ps
CPU time 80.54 seconds
Started Aug 28 07:57:44 PM UTC 24
Finished Aug 28 07:59:07 PM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772258497 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.2772258497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.2620646586
Short name T642
Test name
Test status
Simulation time 3583681026 ps
CPU time 71.41 seconds
Started Aug 28 07:57:44 PM UTC 24
Finished Aug 28 07:58:58 PM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620646586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.2620646586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.1180144918
Short name T298
Test name
Test status
Simulation time 69338202 ps
CPU time 1.59 seconds
Started Aug 28 07:57:43 PM UTC 24
Finished Aug 28 07:57:46 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180144918 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1180144918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.1339772418
Short name T310
Test name
Test status
Simulation time 17397592 ps
CPU time 1.11 seconds
Started Aug 28 07:57:46 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339772418 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.1339772418
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1972431973
Short name T102
Test name
Test status
Simulation time 22480045 ps
CPU time 1.28 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972431973 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.1972431973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.3090185135
Short name T286
Test name
Test status
Simulation time 148039262 ps
CPU time 1.63 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:48 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090185135 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.3090185135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.1161842597
Short name T308
Test name
Test status
Simulation time 62607839 ps
CPU time 1.38 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:48 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161842597 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.1161842597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.2718142125
Short name T303
Test name
Test status
Simulation time 32645392 ps
CPU time 1.29 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718142125 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2718142125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.1108558178
Short name T404
Test name
Test status
Simulation time 1999639790 ps
CPU time 20.58 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:58:07 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108558178 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1108558178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.3532721308
Short name T354
Test name
Test status
Simulation time 861039146 ps
CPU time 10.1 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532721308 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.3532721308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.3242578655
Short name T309
Test name
Test status
Simulation time 199918228 ps
CPU time 2.03 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:48 PM UTC 24
Peak memory 210384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242578655 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.3242578655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1893947033
Short name T285
Test name
Test status
Simulation time 34213237 ps
CPU time 1.2 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893947033
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.1893947033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.574396181
Short name T306
Test name
Test status
Simulation time 57141762 ps
CPU time 1.25 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574396181 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.574396181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.4059164655
Short name T304
Test name
Test status
Simulation time 40632981 ps
CPU time 1.21 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059164655 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.4059164655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.3671933617
Short name T162
Test name
Test status
Simulation time 1602914639 ps
CPU time 6.44 seconds
Started Aug 28 07:57:46 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671933617 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3671933617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.3770719450
Short name T301
Test name
Test status
Simulation time 18159113 ps
CPU time 1.12 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770719450 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3770719450
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.3668712186
Short name T600
Test name
Test status
Simulation time 12083665471 ps
CPU time 57.47 seconds
Started Aug 28 07:57:46 PM UTC 24
Finished Aug 28 07:58:46 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668712186 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.3668712186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.4212938585
Short name T699
Test name
Test status
Simulation time 6429836310 ps
CPU time 115.09 seconds
Started Aug 28 07:57:46 PM UTC 24
Finished Aug 28 07:59:44 PM UTC 24
Peak memory 224364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212938585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.4212938585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.798672652
Short name T305
Test name
Test status
Simulation time 43404250 ps
CPU time 1.26 seconds
Started Aug 28 07:57:45 PM UTC 24
Finished Aug 28 07:57:47 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798672652 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.798672652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.1319801085
Short name T318
Test name
Test status
Simulation time 27685811 ps
CPU time 1.19 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:50 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319801085 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.1319801085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.3805175183
Short name T313
Test name
Test status
Simulation time 17911560 ps
CPU time 1.11 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805175183 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.3805175183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.3837871845
Short name T311
Test name
Test status
Simulation time 17736192 ps
CPU time 1.11 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837871845 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3837871845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.4236018140
Short name T323
Test name
Test status
Simulation time 157248490 ps
CPU time 1.63 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:51 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236018140 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.4236018140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.2444442568
Short name T270
Test name
Test status
Simulation time 67869491 ps
CPU time 1.44 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444442568 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2444442568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.1764919460
Short name T337
Test name
Test status
Simulation time 825856239 ps
CPU time 5.86 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764919460 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1764919460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.2050133020
Short name T371
Test name
Test status
Simulation time 979294613 ps
CPU time 10.68 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:58 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050133020 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.2050133020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.1339646122
Short name T315
Test name
Test status
Simulation time 72469844 ps
CPU time 1.69 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:50 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339646122 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.1339646122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.2811754308
Short name T314
Test name
Test status
Simulation time 78681268 ps
CPU time 1.45 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811754308
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.2811754308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3569582962
Short name T312
Test name
Test status
Simulation time 43164895 ps
CPU time 1.23 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569582962
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.3569582962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.1607168198
Short name T307
Test name
Test status
Simulation time 15702851 ps
CPU time 1.05 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607168198 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1607168198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.3252894988
Short name T351
Test name
Test status
Simulation time 647365160 ps
CPU time 6.4 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252894988 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.3252894988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.1772675210
Short name T139
Test name
Test status
Simulation time 70580449 ps
CPU time 1.61 seconds
Started Aug 28 07:57:46 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772675210 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1772675210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.2322562672
Short name T630
Test name
Test status
Simulation time 7552474048 ps
CPU time 62.24 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:58:52 PM UTC 24
Peak memory 227252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322562672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.2322562672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.715469918
Short name T273
Test name
Test status
Simulation time 63093079 ps
CPU time 1.24 seconds
Started Aug 28 07:57:47 PM UTC 24
Finished Aug 28 07:57:49 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715469918 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.715469918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.2473583464
Short name T329
Test name
Test status
Simulation time 39151022 ps
CPU time 1.28 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473583464 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.2473583464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1606513924
Short name T107
Test name
Test status
Simulation time 77164957 ps
CPU time 1.38 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606513924 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.1606513924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.573730714
Short name T319
Test name
Test status
Simulation time 16950294 ps
CPU time 0.96 seconds
Started Aug 28 07:57:49 PM UTC 24
Finished Aug 28 07:57:51 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573730714 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.573730714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.3074992234
Short name T330
Test name
Test status
Simulation time 100263264 ps
CPU time 1.68 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:53 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074992234 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.3074992234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.3955149660
Short name T322
Test name
Test status
Simulation time 62604598 ps
CPU time 1.28 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:51 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955149660 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3955149660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.1598873516
Short name T373
Test name
Test status
Simulation time 1042996542 ps
CPU time 10.69 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:58:00 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598873516 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1598873516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.3393461597
Short name T338
Test name
Test status
Simulation time 670990623 ps
CPU time 4.21 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393461597 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.3393461597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.209371082
Short name T328
Test name
Test status
Simulation time 44589881 ps
CPU time 1.42 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209371082 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.209371082
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2184944641
Short name T325
Test name
Test status
Simulation time 31229959 ps
CPU time 1.05 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184944641
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.2184944641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2178708237
Short name T327
Test name
Test status
Simulation time 43822154 ps
CPU time 1.25 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178708237
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.2178708237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.1728451587
Short name T321
Test name
Test status
Simulation time 17379727 ps
CPU time 1.17 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:51 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728451587 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1728451587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.2150240169
Short name T352
Test name
Test status
Simulation time 723742594 ps
CPU time 4.62 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150240169 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2150240169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.3614645528
Short name T320
Test name
Test status
Simulation time 21769907 ps
CPU time 1.24 seconds
Started Aug 28 07:57:48 PM UTC 24
Finished Aug 28 07:57:51 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614645528 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3614645528
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.1916674296
Short name T648
Test name
Test status
Simulation time 10936120329 ps
CPU time 72.6 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:59:05 PM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916674296 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.1916674296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.306598067
Short name T516
Test name
Test status
Simulation time 1906667199 ps
CPU time 33.79 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:58:25 PM UTC 24
Peak memory 220164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306598067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.306598067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.2102340696
Short name T324
Test name
Test status
Simulation time 23192374 ps
CPU time 1.28 seconds
Started Aug 28 07:57:49 PM UTC 24
Finished Aug 28 07:57:51 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102340696 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.2102340696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.1389989841
Short name T350
Test name
Test status
Simulation time 19223844 ps
CPU time 1.05 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:57:55 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389989841 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.1389989841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.558715657
Short name T348
Test name
Test status
Simulation time 114031549 ps
CPU time 1.52 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=558715657 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.558715657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.3293199501
Short name T340
Test name
Test status
Simulation time 49828343 ps
CPU time 1.13 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293199501 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3293199501
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.3122143398
Short name T343
Test name
Test status
Simulation time 39199576 ps
CPU time 1.09 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122143398 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.3122143398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.2385665232
Short name T341
Test name
Test status
Simulation time 75315931 ps
CPU time 1.51 seconds
Started Aug 28 07:57:51 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 209840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385665232 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2385665232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.4040545389
Short name T370
Test name
Test status
Simulation time 434492131 ps
CPU time 5.09 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:58 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040545389 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.4040545389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.857911076
Short name T372
Test name
Test status
Simulation time 1046138674 ps
CPU time 6.02 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:59 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857911076 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.857911076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.1499678746
Short name T346
Test name
Test status
Simulation time 47957285 ps
CPU time 1.45 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1499678746 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1499678746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.121305028
Short name T344
Test name
Test status
Simulation time 51354339 ps
CPU time 1.24 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121305028 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.121305028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.429642826
Short name T345
Test name
Test status
Simulation time 81852425 ps
CPU time 1.47 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429642826 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.429642826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.1690635589
Short name T339
Test name
Test status
Simulation time 14159045 ps
CPU time 1.05 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690635589 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1690635589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.4214808853
Short name T375
Test name
Test status
Simulation time 1390528666 ps
CPU time 6.4 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:58:01 PM UTC 24
Peak memory 210764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214808853 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.4214808853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.888407597
Short name T332
Test name
Test status
Simulation time 138078716 ps
CPU time 1.6 seconds
Started Aug 28 07:57:50 PM UTC 24
Finished Aug 28 07:57:53 PM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888407597 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.888407597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.1731697484
Short name T394
Test name
Test status
Simulation time 1933420113 ps
CPU time 11.06 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731697484 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.1731697484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.4077254159
Short name T165
Test name
Test status
Simulation time 4041900869 ps
CPU time 73.02 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:59:08 PM UTC 24
Peak memory 224144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077254159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.4077254159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.3474854505
Short name T347
Test name
Test status
Simulation time 127834285 ps
CPU time 1.63 seconds
Started Aug 28 07:57:52 PM UTC 24
Finished Aug 28 07:57:54 PM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474854505 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3474854505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.2069890246
Short name T52
Test name
Test status
Simulation time 14751862 ps
CPU time 1.03 seconds
Started Aug 28 07:55:56 PM UTC 24
Finished Aug 28 07:55:58 PM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069890246 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.2069890246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.627157174
Short name T27
Test name
Test status
Simulation time 22962277 ps
CPU time 1.41 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:55:57 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627157174 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.627157174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.4225441336
Short name T21
Test name
Test status
Simulation time 38209148 ps
CPU time 1.12 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:55 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225441336 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.4225441336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.3028711653
Short name T94
Test name
Test status
Simulation time 180163598 ps
CPU time 1.6 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:55:58 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028711653 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.3028711653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.2791087417
Short name T22
Test name
Test status
Simulation time 31595294 ps
CPU time 1.27 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:55 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791087417 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2791087417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.902299385
Short name T35
Test name
Test status
Simulation time 1490124579 ps
CPU time 9.66 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:56:04 PM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902299385 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.902299385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.2969376940
Short name T24
Test name
Test status
Simulation time 279973251 ps
CPU time 2.14 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:56 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969376940 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.2969376940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.3307780976
Short name T25
Test name
Test status
Simulation time 49176633 ps
CPU time 1.35 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:55:57 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307780976 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.3307780976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.4180594620
Short name T28
Test name
Test status
Simulation time 74061888 ps
CPU time 1.59 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:55:57 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180594620
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.4180594620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.291988055
Short name T26
Test name
Test status
Simulation time 39763089 ps
CPU time 1.49 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:55:57 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291988055 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.291988055
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.1008301066
Short name T163
Test name
Test status
Simulation time 14908790 ps
CPU time 1.03 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:55 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008301066 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1008301066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.3310200952
Short name T39
Test name
Test status
Simulation time 75692731 ps
CPU time 1.58 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:55:58 PM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310200952 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3310200952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.2116686205
Short name T50
Test name
Test status
Simulation time 158453159 ps
CPU time 3.48 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:56:00 PM UTC 24
Peak memory 241432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116686205 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.2116686205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.3781088364
Short name T20
Test name
Test status
Simulation time 70440065 ps
CPU time 1.31 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:55 PM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781088364 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3781088364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.3331679836
Short name T56
Test name
Test status
Simulation time 4788085132 ps
CPU time 57.66 seconds
Started Aug 28 07:55:55 PM UTC 24
Finished Aug 28 07:56:54 PM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331679836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.3331679836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.1587399431
Short name T23
Test name
Test status
Simulation time 76015138 ps
CPU time 1.54 seconds
Started Aug 28 07:55:53 PM UTC 24
Finished Aug 28 07:55:56 PM UTC 24
Peak memory 209904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587399431 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1587399431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.4197157343
Short name T366
Test name
Test status
Simulation time 26993641 ps
CPU time 0.99 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197157343 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.4197157343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3190831988
Short name T363
Test name
Test status
Simulation time 20190980 ps
CPU time 1.09 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190831988 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3190831988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.894291942
Short name T361
Test name
Test status
Simulation time 32548945 ps
CPU time 1.07 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894291942 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.894291942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.4173154702
Short name T368
Test name
Test status
Simulation time 19746223 ps
CPU time 1.27 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173154702 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.4173154702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.2951279777
Short name T358
Test name
Test status
Simulation time 147228484 ps
CPU time 2.08 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951279777 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.2951279777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.3070370777
Short name T400
Test name
Test status
Simulation time 2058144147 ps
CPU time 11.88 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070370777 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.3070370777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.2113069849
Short name T421
Test name
Test status
Simulation time 1461125480 ps
CPU time 14.63 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:58:09 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113069849 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.2113069849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.4139934668
Short name T362
Test name
Test status
Simulation time 17478276 ps
CPU time 1.11 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139934668 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.4139934668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1613051177
Short name T367
Test name
Test status
Simulation time 26196643 ps
CPU time 1.31 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613051177
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.1613051177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3014409455
Short name T364
Test name
Test status
Simulation time 54358399 ps
CPU time 1.18 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014409455
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.3014409455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.704575871
Short name T359
Test name
Test status
Simulation time 13349646 ps
CPU time 0.93 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704575871 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.704575871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.956334877
Short name T369
Test name
Test status
Simulation time 80559898 ps
CPU time 1.54 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:58 PM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956334877 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.956334877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.4149396731
Short name T353
Test name
Test status
Simulation time 157339420 ps
CPU time 1.62 seconds
Started Aug 28 07:57:53 PM UTC 24
Finished Aug 28 07:57:56 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149396731 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.4149396731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.3718427353
Short name T507
Test name
Test status
Simulation time 5382941523 ps
CPU time 27.26 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718427353 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3718427353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.3487081646
Short name T639
Test name
Test status
Simulation time 2672713718 ps
CPU time 60.23 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:58:57 PM UTC 24
Peak memory 227056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487081646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3487081646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.2342097560
Short name T365
Test name
Test status
Simulation time 80208860 ps
CPU time 1.42 seconds
Started Aug 28 07:57:55 PM UTC 24
Finished Aug 28 07:57:57 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342097560 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2342097560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.3524144323
Short name T336
Test name
Test status
Simulation time 36687088 ps
CPU time 1.08 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:04 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524144323 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.3524144323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3050364588
Short name T383
Test name
Test status
Simulation time 80067033 ps
CPU time 1.43 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:04 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050364588 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.3050364588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.1517728770
Short name T378
Test name
Test status
Simulation time 25245377 ps
CPU time 0.91 seconds
Started Aug 28 07:58:01 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517728770 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1517728770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.107420217
Short name T333
Test name
Test status
Simulation time 17913930 ps
CPU time 0.87 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:04 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107420217 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.107420217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.1903762372
Short name T379
Test name
Test status
Simulation time 30486571 ps
CPU time 1.18 seconds
Started Aug 28 07:58:00 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903762372 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1903762372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.4186945271
Short name T408
Test name
Test status
Simulation time 807848865 ps
CPU time 6.24 seconds
Started Aug 28 07:58:00 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186945271 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.4186945271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.2115995164
Short name T436
Test name
Test status
Simulation time 1726188740 ps
CPU time 9.8 seconds
Started Aug 28 07:58:00 PM UTC 24
Finished Aug 28 07:58:11 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115995164 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.2115995164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.3469615917
Short name T356
Test name
Test status
Simulation time 98221823 ps
CPU time 1.46 seconds
Started Aug 28 07:58:01 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469615917 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3469615917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3308338317
Short name T335
Test name
Test status
Simulation time 41743867 ps
CPU time 1.1 seconds
Started Aug 28 07:58:01 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308338317
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.3308338317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1907343235
Short name T381
Test name
Test status
Simulation time 92902356 ps
CPU time 1.57 seconds
Started Aug 28 07:58:01 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907343235
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.1907343235
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.2668131609
Short name T376
Test name
Test status
Simulation time 14868447 ps
CPU time 0.96 seconds
Started Aug 28 07:58:00 PM UTC 24
Finished Aug 28 07:58:02 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668131609 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.2668131609
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.3404055867
Short name T391
Test name
Test status
Simulation time 273258178 ps
CPU time 1.99 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 209972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404055867 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3404055867
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.2430714795
Short name T380
Test name
Test status
Simulation time 34041847 ps
CPU time 1.17 seconds
Started Aug 28 07:58:00 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430714795 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.2430714795
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.859510981
Short name T645
Test name
Test status
Simulation time 9541173910 ps
CPU time 58.91 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:59:03 PM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859510981 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.859510981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.1885330571
Short name T683
Test name
Test status
Simulation time 6061072462 ps
CPU time 88.82 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:59:33 PM UTC 24
Peak memory 220300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885330571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1885330571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.2708847274
Short name T357
Test name
Test status
Simulation time 272358292 ps
CPU time 1.96 seconds
Started Aug 28 07:58:01 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708847274 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2708847274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.3284156888
Short name T395
Test name
Test status
Simulation time 15026903 ps
CPU time 1.08 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284156888 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.3284156888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.614104914
Short name T389
Test name
Test status
Simulation time 34033492 ps
CPU time 1.27 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614104914 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.614104914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.1142160305
Short name T386
Test name
Test status
Simulation time 35059232 ps
CPU time 1.15 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142160305 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1142160305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.4205865193
Short name T392
Test name
Test status
Simulation time 99646421 ps
CPU time 1.49 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205865193 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.4205865193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2137107586
Short name T385
Test name
Test status
Simulation time 35837042 ps
CPU time 1.33 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137107586 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2137107586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.3349652175
Short name T407
Test name
Test status
Simulation time 319740771 ps
CPU time 3.84 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:07 PM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349652175 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3349652175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.2442072691
Short name T484
Test name
Test status
Simulation time 1462148598 ps
CPU time 15.3 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442072691 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.2442072691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.3539069279
Short name T393
Test name
Test status
Simulation time 136829126 ps
CPU time 1.57 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539069279 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3539069279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.4156358016
Short name T387
Test name
Test status
Simulation time 15526836 ps
CPU time 1.02 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156358016
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.4156358016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2798320842
Short name T388
Test name
Test status
Simulation time 26616494 ps
CPU time 1.34 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798320842
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.2798320842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.2588585473
Short name T384
Test name
Test status
Simulation time 27253624 ps
CPU time 1.07 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588585473 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.2588585473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.4176960347
Short name T406
Test name
Test status
Simulation time 371089742 ps
CPU time 3.09 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:58:07 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176960347 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.4176960347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.1610660236
Short name T382
Test name
Test status
Simulation time 37672421 ps
CPU time 1.19 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:04 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610660236 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1610660236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.2667901902
Short name T681
Test name
Test status
Simulation time 10186842338 ps
CPU time 86.58 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:59:32 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667901902 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2667901902
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.2518047718
Short name T686
Test name
Test status
Simulation time 4637993508 ps
CPU time 90.02 seconds
Started Aug 28 07:58:03 PM UTC 24
Finished Aug 28 07:59:35 PM UTC 24
Peak memory 220276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518047718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.2518047718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.334322991
Short name T390
Test name
Test status
Simulation time 75439845 ps
CPU time 1.43 seconds
Started Aug 28 07:58:02 PM UTC 24
Finished Aug 28 07:58:05 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334322991 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.334322991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.2364626015
Short name T414
Test name
Test status
Simulation time 16641224 ps
CPU time 1.09 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364626015 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.2364626015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.913207474
Short name T415
Test name
Test status
Simulation time 24523776 ps
CPU time 1.39 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913207474 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.913207474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.1207913585
Short name T398
Test name
Test status
Simulation time 28677963 ps
CPU time 0.91 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207913585 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1207913585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.1561658088
Short name T412
Test name
Test status
Simulation time 18003455 ps
CPU time 1.16 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561658088 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.1561658088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.1429995252
Short name T402
Test name
Test status
Simulation time 31122326 ps
CPU time 1.33 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429995252 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1429995252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.3842562334
Short name T428
Test name
Test status
Simulation time 571878172 ps
CPU time 4.94 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842562334 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3842562334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.3492027377
Short name T422
Test name
Test status
Simulation time 380729244 ps
CPU time 4.69 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492027377 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.3492027377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.1375057102
Short name T405
Test name
Test status
Simulation time 65171050 ps
CPU time 1.27 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:07 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375057102 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.1375057102
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.2715457599
Short name T409
Test name
Test status
Simulation time 14503982 ps
CPU time 1.15 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715457599
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.2715457599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2062111503
Short name T411
Test name
Test status
Simulation time 21449413 ps
CPU time 1.22 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062111503
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.2062111503
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.660920887
Short name T401
Test name
Test status
Simulation time 36762107 ps
CPU time 1.17 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660920887 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.660920887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.3217304018
Short name T462
Test name
Test status
Simulation time 2092226854 ps
CPU time 8.4 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3217304018 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3217304018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.2083761768
Short name T399
Test name
Test status
Simulation time 17494658 ps
CPU time 1.28 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083761768 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2083761768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.3767138490
Short name T593
Test name
Test status
Simulation time 6715723560 ps
CPU time 42.22 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:50 PM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767138490 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.3767138490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.2185153664
Short name T701
Test name
Test status
Simulation time 17206599885 ps
CPU time 97.63 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:59:46 PM UTC 24
Peak memory 226612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185153664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2185153664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.727410831
Short name T403
Test name
Test status
Simulation time 73928726 ps
CPU time 1.28 seconds
Started Aug 28 07:58:04 PM UTC 24
Finished Aug 28 07:58:06 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727410831 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.727410831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.1227323550
Short name T427
Test name
Test status
Simulation time 27840464 ps
CPU time 1.08 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227323550 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.1227323550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3939931091
Short name T430
Test name
Test status
Simulation time 73824837 ps
CPU time 1.63 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939931091 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.3939931091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.3837176584
Short name T417
Test name
Test status
Simulation time 13802736 ps
CPU time 0.96 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837176584 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3837176584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.695313478
Short name T424
Test name
Test status
Simulation time 26685416 ps
CPU time 1.26 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695313478 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.695313478
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.3016406742
Short name T416
Test name
Test status
Simulation time 43734874 ps
CPU time 0.96 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016406742 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3016406742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.4245148698
Short name T543
Test name
Test status
Simulation time 2121244509 ps
CPU time 23.26 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:31 PM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245148698 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.4245148698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.3470183522
Short name T431
Test name
Test status
Simulation time 415283962 ps
CPU time 3.02 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470183522 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.3470183522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.295790632
Short name T429
Test name
Test status
Simulation time 84995567 ps
CPU time 1.52 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 208952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295790632 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.295790632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.571042289
Short name T423
Test name
Test status
Simulation time 18847904 ps
CPU time 1.18 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571042289 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.571042289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1802447678
Short name T425
Test name
Test status
Simulation time 84717774 ps
CPU time 1.33 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802447678
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.1802447678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.3153402979
Short name T418
Test name
Test status
Simulation time 45755626 ps
CPU time 1.28 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:09 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153402979 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3153402979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.4177342380
Short name T449
Test name
Test status
Simulation time 774928418 ps
CPU time 4.56 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:13 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177342380 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.4177342380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.2479935493
Short name T420
Test name
Test status
Simulation time 127440386 ps
CPU time 1.85 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:09 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479935493 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2479935493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.1770520058
Short name T635
Test name
Test status
Simulation time 4623022418 ps
CPU time 45.9 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:55 PM UTC 24
Peak memory 210780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770520058 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1770520058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.1809687848
Short name T55
Test name
Test status
Simulation time 6751092764 ps
CPU time 70.51 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:59:20 PM UTC 24
Peak memory 220212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809687848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.1809687848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.1291993460
Short name T419
Test name
Test status
Simulation time 70104928 ps
CPU time 1.46 seconds
Started Aug 28 07:58:06 PM UTC 24
Finished Aug 28 07:58:09 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291993460 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.1291993460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.1882322296
Short name T441
Test name
Test status
Simulation time 14764362 ps
CPU time 1.1 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882322296 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.1882322296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.447714135
Short name T445
Test name
Test status
Simulation time 84266454 ps
CPU time 1.63 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447714135 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.447714135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.2401572594
Short name T435
Test name
Test status
Simulation time 14514267 ps
CPU time 0.86 seconds
Started Aug 28 07:58:09 PM UTC 24
Finished Aug 28 07:58:11 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401572594 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2401572594
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.3259614095
Short name T437
Test name
Test status
Simulation time 23185370 ps
CPU time 1.14 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259614095 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.3259614095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.3337108131
Short name T426
Test name
Test status
Simulation time 24444940 ps
CPU time 1.04 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:10 PM UTC 24
Peak memory 208972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337108131 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3337108131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.3224884380
Short name T561
Test name
Test status
Simulation time 2475343179 ps
CPU time 26.15 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:36 PM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224884380 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3224884380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.1994109401
Short name T499
Test name
Test status
Simulation time 2067213973 ps
CPU time 12.18 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:21 PM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994109401 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.1994109401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.3929137207
Short name T439
Test name
Test status
Simulation time 25171460 ps
CPU time 1.39 seconds
Started Aug 28 07:58:09 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929137207 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.3929137207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.383798860
Short name T440
Test name
Test status
Simulation time 34938093 ps
CPU time 1.37 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383798860 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.383798860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2524052004
Short name T442
Test name
Test status
Simulation time 132545571 ps
CPU time 1.54 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524052004
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.2524052004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.3587259332
Short name T434
Test name
Test status
Simulation time 14347996 ps
CPU time 0.92 seconds
Started Aug 28 07:58:09 PM UTC 24
Finished Aug 28 07:58:11 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587259332 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.3587259332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.660988305
Short name T456
Test name
Test status
Simulation time 372989720 ps
CPU time 3.55 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660988305 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.660988305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.1685172492
Short name T432
Test name
Test status
Simulation time 62342106 ps
CPU time 1.47 seconds
Started Aug 28 07:58:08 PM UTC 24
Finished Aug 28 07:58:11 PM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685172492 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1685172492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.2915494001
Short name T443
Test name
Test status
Simulation time 36683987 ps
CPU time 1.26 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915494001 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2915494001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.822410296
Short name T703
Test name
Test status
Simulation time 15569632430 ps
CPU time 98.98 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:59:51 PM UTC 24
Peak memory 227244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822410296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.822410296
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.2690305140
Short name T447
Test name
Test status
Simulation time 118514048 ps
CPU time 1.96 seconds
Started Aug 28 07:58:09 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690305140 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2690305140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.1329917500
Short name T410
Test name
Test status
Simulation time 37380590 ps
CPU time 1.15 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329917500 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.1329917500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2302403646
Short name T454
Test name
Test status
Simulation time 28573897 ps
CPU time 1.22 seconds
Started Aug 28 07:58:12 PM UTC 24
Finished Aug 28 07:58:14 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302403646 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.2302403646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.3381869146
Short name T451
Test name
Test status
Simulation time 15706142 ps
CPU time 1.01 seconds
Started Aug 28 07:58:11 PM UTC 24
Finished Aug 28 07:58:14 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381869146 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3381869146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.1492301444
Short name T452
Test name
Test status
Simulation time 41421117 ps
CPU time 1.08 seconds
Started Aug 28 07:58:12 PM UTC 24
Finished Aug 28 07:58:14 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492301444 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.1492301444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.1131377548
Short name T448
Test name
Test status
Simulation time 63704780 ps
CPU time 1.29 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:13 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131377548 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1131377548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.3499069815
Short name T413
Test name
Test status
Simulation time 218308429 ps
CPU time 2.46 seconds
Started Aug 28 07:58:11 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499069815 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3499069815
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.4275642665
Short name T396
Test name
Test status
Simulation time 142236832 ps
CPU time 2.22 seconds
Started Aug 28 07:58:11 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275642665 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.4275642665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.3665079689
Short name T457
Test name
Test status
Simulation time 156742973 ps
CPU time 2.25 seconds
Started Aug 28 07:58:11 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665079689 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.3665079689
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.2098297602
Short name T455
Test name
Test status
Simulation time 49305420 ps
CPU time 1.52 seconds
Started Aug 28 07:58:12 PM UTC 24
Finished Aug 28 07:58:14 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098297602
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.2098297602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2914394882
Short name T459
Test name
Test status
Simulation time 247863041 ps
CPU time 2.49 seconds
Started Aug 28 07:58:12 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914394882
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.2914394882
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.2755914518
Short name T450
Test name
Test status
Simulation time 22140194 ps
CPU time 1.17 seconds
Started Aug 28 07:58:11 PM UTC 24
Finished Aug 28 07:58:14 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755914518 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2755914518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.4142596649
Short name T470
Test name
Test status
Simulation time 562740627 ps
CPU time 3.26 seconds
Started Aug 28 07:58:12 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142596649 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.4142596649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.2227480949
Short name T446
Test name
Test status
Simulation time 22395420 ps
CPU time 1.3 seconds
Started Aug 28 07:58:10 PM UTC 24
Finished Aug 28 07:58:12 PM UTC 24
Peak memory 209972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227480949 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2227480949
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.3501921861
Short name T601
Test name
Test status
Simulation time 4691569943 ps
CPU time 31.82 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:46 PM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501921861 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.3501921861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.1490463673
Short name T644
Test name
Test status
Simulation time 5787531273 ps
CPU time 46.24 seconds
Started Aug 28 07:58:12 PM UTC 24
Finished Aug 28 07:59:00 PM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490463673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.1490463673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.3524197371
Short name T453
Test name
Test status
Simulation time 26161232 ps
CPU time 1.17 seconds
Started Aug 28 07:58:11 PM UTC 24
Finished Aug 28 07:58:14 PM UTC 24
Peak memory 209992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524197371 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3524197371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.1103145589
Short name T472
Test name
Test status
Simulation time 61476197 ps
CPU time 1.32 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:18 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103145589 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.1103145589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.20346003
Short name T471
Test name
Test status
Simulation time 147043561 ps
CPU time 1.85 seconds
Started Aug 28 07:58:14 PM UTC 24
Finished Aug 28 07:58:17 PM UTC 24
Peak memory 209684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20346003 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.20346003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.2932821096
Short name T461
Test name
Test status
Simulation time 24189491 ps
CPU time 0.98 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932821096 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.2932821096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.4121545191
Short name T469
Test name
Test status
Simulation time 66481694 ps
CPU time 1.28 seconds
Started Aug 28 07:58:14 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121545191 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.4121545191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.2170831779
Short name T460
Test name
Test status
Simulation time 39505416 ps
CPU time 1.17 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:15 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170831779 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2170831779
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.450050976
Short name T520
Test name
Test status
Simulation time 798752883 ps
CPU time 12.21 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=450050976 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.450050976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.1996741928
Short name T527
Test name
Test status
Simulation time 1336140892 ps
CPU time 13.18 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:28 PM UTC 24
Peak memory 210724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996741928 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.1996741928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.3319312169
Short name T466
Test name
Test status
Simulation time 29773521 ps
CPU time 1.15 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319312169 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.3319312169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.2478128645
Short name T467
Test name
Test status
Simulation time 21146987 ps
CPU time 1.03 seconds
Started Aug 28 07:58:14 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478128645
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.2478128645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.4128609028
Short name T464
Test name
Test status
Simulation time 17619141 ps
CPU time 1.06 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128609028
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.4128609028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.3491860554
Short name T463
Test name
Test status
Simulation time 39115951 ps
CPU time 1.29 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491860554 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3491860554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.1476007680
Short name T491
Test name
Test status
Simulation time 845954071 ps
CPU time 4.86 seconds
Started Aug 28 07:58:14 PM UTC 24
Finished Aug 28 07:58:20 PM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476007680 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1476007680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.751569114
Short name T465
Test name
Test status
Simulation time 81659244 ps
CPU time 1.47 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751569114 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.751569114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.1433840399
Short name T649
Test name
Test status
Simulation time 7448445484 ps
CPU time 49.64 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:59:06 PM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433840399 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.1433840399
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.1370347425
Short name T618
Test name
Test status
Simulation time 2662303387 ps
CPU time 33.61 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:50 PM UTC 24
Peak memory 220272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370347425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.1370347425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.494949365
Short name T468
Test name
Test status
Simulation time 97480941 ps
CPU time 1.62 seconds
Started Aug 28 07:58:13 PM UTC 24
Finished Aug 28 07:58:16 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494949365 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.494949365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.3603962820
Short name T480
Test name
Test status
Simulation time 14371103 ps
CPU time 0.9 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603962820 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.3603962820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.604293704
Short name T486
Test name
Test status
Simulation time 29666618 ps
CPU time 1.25 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604293704 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.604293704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.2564873595
Short name T479
Test name
Test status
Simulation time 35775427 ps
CPU time 1 seconds
Started Aug 28 07:58:16 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564873595 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2564873595
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.3507998077
Short name T488
Test name
Test status
Simulation time 53161473 ps
CPU time 1.48 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507998077 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.3507998077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.35179220
Short name T474
Test name
Test status
Simulation time 24704503 ps
CPU time 1.22 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:18 PM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35179220 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.35179220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.1751170743
Short name T519
Test name
Test status
Simulation time 917039856 ps
CPU time 9.84 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751170743 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.1751170743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.217317725
Short name T477
Test name
Test status
Simulation time 150271107 ps
CPU time 1.67 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:18 PM UTC 24
Peak memory 209740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217317725 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.217317725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.1552651173
Short name T482
Test name
Test status
Simulation time 27963267 ps
CPU time 1.28 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 209012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552651173 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.1552651173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.47774012
Short name T485
Test name
Test status
Simulation time 51894109 ps
CPU time 1.32 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47774012 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.47774012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.324427921
Short name T481
Test name
Test status
Simulation time 28227298 ps
CPU time 1.2 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324427921 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.324427921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.4106514755
Short name T475
Test name
Test status
Simulation time 68253841 ps
CPU time 1.21 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:18 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106514755 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.4106514755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.1401051919
Short name T515
Test name
Test status
Simulation time 956501632 ps
CPU time 7.1 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:25 PM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401051919 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1401051919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.830899231
Short name T473
Test name
Test status
Simulation time 21921021 ps
CPU time 1.3 seconds
Started Aug 28 07:58:15 PM UTC 24
Finished Aug 28 07:58:18 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830899231 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.830899231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.3602338650
Short name T675
Test name
Test status
Simulation time 7025962756 ps
CPU time 65.04 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:59:24 PM UTC 24
Peak memory 210720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602338650 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.3602338650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.323801802
Short name T483
Test name
Test status
Simulation time 39050260 ps
CPU time 1.44 seconds
Started Aug 28 07:58:16 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=323801802 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.323801802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.1296536945
Short name T500
Test name
Test status
Simulation time 35427396 ps
CPU time 1.21 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296536945 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.1296536945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.1956211125
Short name T497
Test name
Test status
Simulation time 30978101 ps
CPU time 1.29 seconds
Started Aug 28 07:58:18 PM UTC 24
Finished Aug 28 07:58:21 PM UTC 24
Peak memory 209520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956211125 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.1956211125
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.2941310458
Short name T493
Test name
Test status
Simulation time 45687060 ps
CPU time 1.04 seconds
Started Aug 28 07:58:18 PM UTC 24
Finished Aug 28 07:58:20 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941310458 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2941310458
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.3449724261
Short name T495
Test name
Test status
Simulation time 43999441 ps
CPU time 1 seconds
Started Aug 28 07:58:19 PM UTC 24
Finished Aug 28 07:58:21 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449724261 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.3449724261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.4273451394
Short name T487
Test name
Test status
Simulation time 16136817 ps
CPU time 1.22 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273451394 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.4273451394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.295393362
Short name T555
Test name
Test status
Simulation time 2240711626 ps
CPU time 16.37 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:35 PM UTC 24
Peak memory 210968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295393362 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.295393362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.2523162227
Short name T508
Test name
Test status
Simulation time 1064285990 ps
CPU time 5.75 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523162227 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.2523162227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.1287427629
Short name T498
Test name
Test status
Simulation time 89960833 ps
CPU time 1.52 seconds
Started Aug 28 07:58:18 PM UTC 24
Finished Aug 28 07:58:21 PM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287427629 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.1287427629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.923946739
Short name T496
Test name
Test status
Simulation time 34738201 ps
CPU time 1.14 seconds
Started Aug 28 07:58:18 PM UTC 24
Finished Aug 28 07:58:21 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923946739 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.923946739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1188809448
Short name T494
Test name
Test status
Simulation time 72066009 ps
CPU time 1.26 seconds
Started Aug 28 07:58:18 PM UTC 24
Finished Aug 28 07:58:21 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188809448
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.1188809448
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.113030926
Short name T490
Test name
Test status
Simulation time 32499579 ps
CPU time 1.21 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113030926 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.113030926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.424119833
Short name T518
Test name
Test status
Simulation time 710796338 ps
CPU time 4.72 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:26 PM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424119833 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.424119833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.4003806100
Short name T492
Test name
Test status
Simulation time 187712212 ps
CPU time 1.83 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:20 PM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003806100 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.4003806100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.2619448981
Short name T643
Test name
Test status
Simulation time 3658897460 ps
CPU time 37.19 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:59 PM UTC 24
Peak memory 210992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619448981 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.2619448981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.1075791894
Short name T688
Test name
Test status
Simulation time 4578373568 ps
CPU time 73.79 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:59:36 PM UTC 24
Peak memory 220232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075791894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.1075791894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.3290221141
Short name T489
Test name
Test status
Simulation time 26863336 ps
CPU time 1.06 seconds
Started Aug 28 07:58:17 PM UTC 24
Finished Aug 28 07:58:19 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290221141 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3290221141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.771929263
Short name T153
Test name
Test status
Simulation time 22630446 ps
CPU time 0.97 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:01 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771929263 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.771929263
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.64035798
Short name T111
Test name
Test status
Simulation time 81133071 ps
CPU time 1.61 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:01 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64035798 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.64035798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.692916414
Short name T148
Test name
Test status
Simulation time 18060133 ps
CPU time 1.01 seconds
Started Aug 28 07:55:58 PM UTC 24
Finished Aug 28 07:56:00 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692916414 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.692916414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.3200522535
Short name T152
Test name
Test status
Simulation time 14652824 ps
CPU time 1.17 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:01 PM UTC 24
Peak memory 210052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200522535 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.3200522535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.2773962293
Short name T16
Test name
Test status
Simulation time 2121436695 ps
CPU time 25.62 seconds
Started Aug 28 07:55:56 PM UTC 24
Finished Aug 28 07:56:23 PM UTC 24
Peak memory 210828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773962293 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2773962293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.1884247083
Short name T40
Test name
Test status
Simulation time 1226542617 ps
CPU time 7.02 seconds
Started Aug 28 07:55:56 PM UTC 24
Finished Aug 28 07:56:05 PM UTC 24
Peak memory 210464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884247083 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.1884247083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.1448178500
Short name T149
Test name
Test status
Simulation time 21489786 ps
CPU time 1.3 seconds
Started Aug 28 07:55:58 PM UTC 24
Finished Aug 28 07:56:00 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448178500 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1448178500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3041345097
Short name T150
Test name
Test status
Simulation time 35896088 ps
CPU time 1.34 seconds
Started Aug 28 07:55:58 PM UTC 24
Finished Aug 28 07:56:00 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041345097
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.3041345097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.590525866
Short name T151
Test name
Test status
Simulation time 155435192 ps
CPU time 1.65 seconds
Started Aug 28 07:55:58 PM UTC 24
Finished Aug 28 07:56:00 PM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590525866 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.590525866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.2714004076
Short name T98
Test name
Test status
Simulation time 37862324 ps
CPU time 1.29 seconds
Started Aug 28 07:55:57 PM UTC 24
Finished Aug 28 07:55:59 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714004076 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2714004076
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.207939963
Short name T8
Test name
Test status
Simulation time 1212928217 ps
CPU time 10.46 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:11 PM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207939963 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.207939963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.2397761644
Short name T57
Test name
Test status
Simulation time 215679416 ps
CPU time 2.97 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 242540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397761644 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.2397761644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.3737267453
Short name T96
Test name
Test status
Simulation time 38390567 ps
CPU time 1.41 seconds
Started Aug 28 07:55:56 PM UTC 24
Finished Aug 28 07:55:59 PM UTC 24
Peak memory 209744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737267453 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.3737267453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.2798047264
Short name T19
Test name
Test status
Simulation time 5345293167 ps
CPU time 47.87 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:48 PM UTC 24
Peak memory 210844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798047264 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.2798047264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.2549419533
Short name T74
Test name
Test status
Simulation time 8619699687 ps
CPU time 58.7 seconds
Started Aug 28 07:55:59 PM UTC 24
Finished Aug 28 07:56:59 PM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549419533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2549419533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.3672472091
Short name T97
Test name
Test status
Simulation time 30083915 ps
CPU time 1.23 seconds
Started Aug 28 07:55:57 PM UTC 24
Finished Aug 28 07:55:59 PM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672472091 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3672472091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.119418678
Short name T513
Test name
Test status
Simulation time 37213917 ps
CPU time 1.27 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119418678 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.119418678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.473179191
Short name T512
Test name
Test status
Simulation time 30143874 ps
CPU time 1.27 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473179191 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.473179191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.4241076889
Short name T506
Test name
Test status
Simulation time 19137453 ps
CPU time 1.19 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241076889 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.4241076889
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.768980268
Short name T511
Test name
Test status
Simulation time 19764134 ps
CPU time 1.18 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768980268 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.768980268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.2463991236
Short name T503
Test name
Test status
Simulation time 91389765 ps
CPU time 1.54 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463991236 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2463991236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.3442660932
Short name T549
Test name
Test status
Simulation time 1801143992 ps
CPU time 11.51 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:34 PM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442660932 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3442660932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.1498981628
Short name T539
Test name
Test status
Simulation time 1647023837 ps
CPU time 8.11 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498981628 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.1498981628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.2208099577
Short name T504
Test name
Test status
Simulation time 13280480 ps
CPU time 1.08 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208099577 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.2208099577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2219854931
Short name T509
Test name
Test status
Simulation time 25881570 ps
CPU time 1.1 seconds
Started Aug 28 07:58:21 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219854931
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.2219854931
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1720187355
Short name T510
Test name
Test status
Simulation time 35141357 ps
CPU time 1.22 seconds
Started Aug 28 07:58:21 PM UTC 24
Finished Aug 28 07:58:24 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720187355
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.1720187355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.2920865104
Short name T502
Test name
Test status
Simulation time 14834130 ps
CPU time 1.12 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920865104 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2920865104
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.3432687201
Short name T532
Test name
Test status
Simulation time 938094025 ps
CPU time 5.57 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:58:29 PM UTC 24
Peak memory 210764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432687201 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3432687201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.1133442502
Short name T501
Test name
Test status
Simulation time 80847700 ps
CPU time 1.27 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133442502 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1133442502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.3346725784
Short name T646
Test name
Test status
Simulation time 6965506992 ps
CPU time 39.45 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:59:03 PM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346725784 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.3346725784
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.1824055426
Short name T700
Test name
Test status
Simulation time 6768090667 ps
CPU time 80.1 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:59:44 PM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824055426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.1824055426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.121720568
Short name T505
Test name
Test status
Simulation time 32795529 ps
CPU time 1.28 seconds
Started Aug 28 07:58:20 PM UTC 24
Finished Aug 28 07:58:23 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121720568 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.121720568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.399745015
Short name T531
Test name
Test status
Simulation time 39266032 ps
CPU time 1.26 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:28 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399745015 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.399745015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3441600390
Short name T533
Test name
Test status
Simulation time 281373543 ps
CPU time 2.29 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:29 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441600390 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.3441600390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.3671207130
Short name T521
Test name
Test status
Simulation time 45686394 ps
CPU time 1.2 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671207130 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3671207130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.3262184631
Short name T528
Test name
Test status
Simulation time 46913573 ps
CPU time 1.22 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:28 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262184631 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.3262184631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.2826408414
Short name T517
Test name
Test status
Simulation time 25995526 ps
CPU time 1.19 seconds
Started Aug 28 07:58:23 PM UTC 24
Finished Aug 28 07:58:25 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826408414 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2826408414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.4250786542
Short name T562
Test name
Test status
Simulation time 681102251 ps
CPU time 10.21 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:36 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250786542 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.4250786542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.3864715874
Short name T526
Test name
Test status
Simulation time 135997761 ps
CPU time 2.15 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864715874 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.3864715874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.4178774451
Short name T529
Test name
Test status
Simulation time 401956437 ps
CPU time 2.99 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:28 PM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178774451 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.4178774451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1976480760
Short name T524
Test name
Test status
Simulation time 27014391 ps
CPU time 1.13 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976480760
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.1976480760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.318391805
Short name T525
Test name
Test status
Simulation time 27926360 ps
CPU time 1.39 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318391805 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.318391805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.782108435
Short name T522
Test name
Test status
Simulation time 104969079 ps
CPU time 1.54 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782108435 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.782108435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.3935753212
Short name T567
Test name
Test status
Simulation time 2348598829 ps
CPU time 10.47 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:37 PM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935753212 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3935753212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.3440746502
Short name T514
Test name
Test status
Simulation time 34680907 ps
CPU time 1.48 seconds
Started Aug 28 07:58:22 PM UTC 24
Finished Aug 28 07:58:25 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440746502 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3440746502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.498054995
Short name T658
Test name
Test status
Simulation time 5796214819 ps
CPU time 52.45 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:59:20 PM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498054995 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.498054995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.4177367976
Short name T706
Test name
Test status
Simulation time 4768723382 ps
CPU time 85.61 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:59:53 PM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177367976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.4177367976
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.1963639404
Short name T523
Test name
Test status
Simulation time 52481969 ps
CPU time 1.51 seconds
Started Aug 28 07:58:24 PM UTC 24
Finished Aug 28 07:58:27 PM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963639404 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1963639404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.769169997
Short name T545
Test name
Test status
Simulation time 19118291 ps
CPU time 1.12 seconds
Started Aug 28 07:58:29 PM UTC 24
Finished Aug 28 07:58:31 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769169997 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.769169997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1297082078
Short name T541
Test name
Test status
Simulation time 138833685 ps
CPU time 1.58 seconds
Started Aug 28 07:58:28 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297082078 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.1297082078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.279692440
Short name T537
Test name
Test status
Simulation time 45379634 ps
CPU time 1.28 seconds
Started Aug 28 07:58:27 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279692440 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.279692440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.1356554553
Short name T544
Test name
Test status
Simulation time 20476175 ps
CPU time 1.19 seconds
Started Aug 28 07:58:29 PM UTC 24
Finished Aug 28 07:58:31 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356554553 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.1356554553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.1560375186
Short name T530
Test name
Test status
Simulation time 57352541 ps
CPU time 1.17 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:28 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560375186 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1560375186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.2783592336
Short name T584
Test name
Test status
Simulation time 2054798085 ps
CPU time 14.3 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:42 PM UTC 24
Peak memory 210896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783592336 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2783592336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.3438157527
Short name T542
Test name
Test status
Simulation time 148458627 ps
CPU time 2.15 seconds
Started Aug 28 07:58:27 PM UTC 24
Finished Aug 28 07:58:31 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438157527 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.3438157527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.231114812
Short name T540
Test name
Test status
Simulation time 85362187 ps
CPU time 1.71 seconds
Started Aug 28 07:58:27 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231114812 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.231114812
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2365412809
Short name T536
Test name
Test status
Simulation time 16206806 ps
CPU time 1.12 seconds
Started Aug 28 07:58:28 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365412809
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.2365412809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3611901397
Short name T458
Test name
Test status
Simulation time 53680751 ps
CPU time 1.31 seconds
Started Aug 28 07:58:28 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611901397
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.3611901397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.3900215069
Short name T535
Test name
Test status
Simulation time 16811863 ps
CPU time 1.17 seconds
Started Aug 28 07:58:27 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900215069 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3900215069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.3595054813
Short name T563
Test name
Test status
Simulation time 772446290 ps
CPU time 5.63 seconds
Started Aug 28 07:58:29 PM UTC 24
Finished Aug 28 07:58:36 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595054813 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3595054813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.3367310312
Short name T534
Test name
Test status
Simulation time 191517239 ps
CPU time 2.24 seconds
Started Aug 28 07:58:26 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367310312 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3367310312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.563946715
Short name T546
Test name
Test status
Simulation time 138798919 ps
CPU time 2.28 seconds
Started Aug 28 07:58:29 PM UTC 24
Finished Aug 28 07:58:32 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563946715 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.563946715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.3035743239
Short name T674
Test name
Test status
Simulation time 2876434765 ps
CPU time 52.66 seconds
Started Aug 28 07:58:29 PM UTC 24
Finished Aug 28 07:59:23 PM UTC 24
Peak memory 227312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035743239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3035743239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.3756469524
Short name T478
Test name
Test status
Simulation time 38238433 ps
CPU time 1.38 seconds
Started Aug 28 07:58:27 PM UTC 24
Finished Aug 28 07:58:30 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756469524 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3756469524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.2112637866
Short name T559
Test name
Test status
Simulation time 37892913 ps
CPU time 1.39 seconds
Started Aug 28 07:58:33 PM UTC 24
Finished Aug 28 07:58:35 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112637866 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.2112637866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3356301527
Short name T556
Test name
Test status
Simulation time 66048680 ps
CPU time 1.59 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:35 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356301527 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.3356301527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.1266887265
Short name T550
Test name
Test status
Simulation time 31023348 ps
CPU time 0.88 seconds
Started Aug 28 07:58:31 PM UTC 24
Finished Aug 28 07:58:34 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266887265 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1266887265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.841881126
Short name T552
Test name
Test status
Simulation time 16737407 ps
CPU time 1.03 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:34 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841881126 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.841881126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.2245998203
Short name T476
Test name
Test status
Simulation time 58109623 ps
CPU time 1.12 seconds
Started Aug 28 07:58:30 PM UTC 24
Finished Aug 28 07:58:33 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245998203 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2245998203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.3494668171
Short name T633
Test name
Test status
Simulation time 1996948190 ps
CPU time 22.14 seconds
Started Aug 28 07:58:30 PM UTC 24
Finished Aug 28 07:58:54 PM UTC 24
Peak memory 210640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494668171 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3494668171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.2444392284
Short name T586
Test name
Test status
Simulation time 973804522 ps
CPU time 11.69 seconds
Started Aug 28 07:58:30 PM UTC 24
Finished Aug 28 07:58:43 PM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444392284 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.2444392284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.3399924508
Short name T554
Test name
Test status
Simulation time 25804930 ps
CPU time 1.21 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:34 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399924508 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3399924508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.924358777
Short name T551
Test name
Test status
Simulation time 25285997 ps
CPU time 1 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:34 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924358777 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.924358777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1848540132
Short name T553
Test name
Test status
Simulation time 20671829 ps
CPU time 1.13 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:34 PM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848540132
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.1848540132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.1903230749
Short name T538
Test name
Test status
Simulation time 20046299 ps
CPU time 0.9 seconds
Started Aug 28 07:58:30 PM UTC 24
Finished Aug 28 07:58:32 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903230749 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1903230749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.2692772837
Short name T576
Test name
Test status
Simulation time 1251867517 ps
CPU time 6.65 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 210764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692772837 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2692772837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.2701164913
Short name T547
Test name
Test status
Simulation time 68447270 ps
CPU time 1.57 seconds
Started Aug 28 07:58:30 PM UTC 24
Finished Aug 28 07:58:33 PM UTC 24
Peak memory 209836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701164913 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2701164913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.1201367766
Short name T673
Test name
Test status
Simulation time 10963987892 ps
CPU time 49.41 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:59:23 PM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201367766 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.1201367766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.97704093
Short name T164
Test name
Test status
Simulation time 1492847723 ps
CPU time 25.27 seconds
Started Aug 28 07:58:32 PM UTC 24
Finished Aug 28 07:58:59 PM UTC 24
Peak memory 220164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97704093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.97704093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.3245161666
Short name T548
Test name
Test status
Simulation time 24982449 ps
CPU time 1.35 seconds
Started Aug 28 07:58:30 PM UTC 24
Finished Aug 28 07:58:33 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245161666 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3245161666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.1796037322
Short name T572
Test name
Test status
Simulation time 76965089 ps
CPU time 1.44 seconds
Started Aug 28 07:58:36 PM UTC 24
Finished Aug 28 07:58:39 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796037322 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.1796037322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.1790983880
Short name T571
Test name
Test status
Simulation time 86341151 ps
CPU time 1.69 seconds
Started Aug 28 07:58:36 PM UTC 24
Finished Aug 28 07:58:39 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790983880 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.1790983880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.339217118
Short name T564
Test name
Test status
Simulation time 19489086 ps
CPU time 1 seconds
Started Aug 28 07:58:34 PM UTC 24
Finished Aug 28 07:58:37 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339217118 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.339217118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.367963710
Short name T570
Test name
Test status
Simulation time 16469748 ps
CPU time 1.04 seconds
Started Aug 28 07:58:36 PM UTC 24
Finished Aug 28 07:58:38 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367963710 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.367963710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.459400036
Short name T558
Test name
Test status
Simulation time 19627918 ps
CPU time 1.15 seconds
Started Aug 28 07:58:33 PM UTC 24
Finished Aug 28 07:58:35 PM UTC 24
Peak memory 208468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459400036 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.459400036
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.2841882123
Short name T636
Test name
Test status
Simulation time 2122406908 ps
CPU time 21.11 seconds
Started Aug 28 07:58:33 PM UTC 24
Finished Aug 28 07:58:56 PM UTC 24
Peak memory 210640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841882123 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2841882123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.3143395380
Short name T637
Test name
Test status
Simulation time 2428426223 ps
CPU time 22.03 seconds
Started Aug 28 07:58:33 PM UTC 24
Finished Aug 28 07:58:56 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143395380 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.3143395380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.482721107
Short name T566
Test name
Test status
Simulation time 40189414 ps
CPU time 1.29 seconds
Started Aug 28 07:58:34 PM UTC 24
Finished Aug 28 07:58:37 PM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=482721107 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.482721107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1716528078
Short name T569
Test name
Test status
Simulation time 176892234 ps
CPU time 2.14 seconds
Started Aug 28 07:58:34 PM UTC 24
Finished Aug 28 07:58:38 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716528078
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.1716528078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1939759454
Short name T565
Test name
Test status
Simulation time 19258957 ps
CPU time 0.97 seconds
Started Aug 28 07:58:34 PM UTC 24
Finished Aug 28 07:58:37 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939759454
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.1939759454
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.83722496
Short name T560
Test name
Test status
Simulation time 49516201 ps
CPU time 1.23 seconds
Started Aug 28 07:58:33 PM UTC 24
Finished Aug 28 07:58:35 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83722496 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.83722496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.4141817412
Short name T603
Test name
Test status
Simulation time 912541149 ps
CPU time 9.19 seconds
Started Aug 28 07:58:36 PM UTC 24
Finished Aug 28 07:58:46 PM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141817412 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.4141817412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.1724251722
Short name T557
Test name
Test status
Simulation time 16428560 ps
CPU time 1.09 seconds
Started Aug 28 07:58:33 PM UTC 24
Finished Aug 28 07:58:35 PM UTC 24
Peak memory 209084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724251722 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1724251722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.803419615
Short name T577
Test name
Test status
Simulation time 269393737 ps
CPU time 2.53 seconds
Started Aug 28 07:58:36 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 210592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803419615 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.803419615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.999664298
Short name T696
Test name
Test status
Simulation time 9526761606 ps
CPU time 62.11 seconds
Started Aug 28 07:58:36 PM UTC 24
Finished Aug 28 07:59:40 PM UTC 24
Peak memory 220276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999664298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.999664298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.2520850214
Short name T568
Test name
Test status
Simulation time 89847138 ps
CPU time 1.83 seconds
Started Aug 28 07:58:34 PM UTC 24
Finished Aug 28 07:58:38 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520850214 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.2520850214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.2733592498
Short name T592
Test name
Test status
Simulation time 102074687 ps
CPU time 1.82 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733592498 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.2733592498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2131657992
Short name T581
Test name
Test status
Simulation time 16348062 ps
CPU time 1.12 seconds
Started Aug 28 07:58:39 PM UTC 24
Finished Aug 28 07:58:41 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131657992 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.2131657992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.639995597
Short name T575
Test name
Test status
Simulation time 22043928 ps
CPU time 1.1 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639995597 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.639995597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.3401534988
Short name T585
Test name
Test status
Simulation time 67469612 ps
CPU time 1.43 seconds
Started Aug 28 07:58:40 PM UTC 24
Finished Aug 28 07:58:42 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401534988 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3401534988
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.422996198
Short name T574
Test name
Test status
Simulation time 21794888 ps
CPU time 1.14 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422996198 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.422996198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.37399666
Short name T632
Test name
Test status
Simulation time 2098941864 ps
CPU time 14.62 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:53 PM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37399666 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.37399666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.1730176842
Short name T624
Test name
Test status
Simulation time 1603646883 ps
CPU time 12.2 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:51 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730176842 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.1730176842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.1847247967
Short name T580
Test name
Test status
Simulation time 78176884 ps
CPU time 1.68 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:41 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847247967 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.1847247967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2175036780
Short name T583
Test name
Test status
Simulation time 64190326 ps
CPU time 1.53 seconds
Started Aug 28 07:58:39 PM UTC 24
Finished Aug 28 07:58:41 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175036780
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.2175036780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1750240481
Short name T582
Test name
Test status
Simulation time 19477058 ps
CPU time 1.25 seconds
Started Aug 28 07:58:39 PM UTC 24
Finished Aug 28 07:58:41 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750240481
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.1750240481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.2120880336
Short name T573
Test name
Test status
Simulation time 14541079 ps
CPU time 1.14 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120880336 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2120880336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.3372859083
Short name T594
Test name
Test status
Simulation time 473142519 ps
CPU time 3.47 seconds
Started Aug 28 07:58:40 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3372859083 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3372859083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.1518916903
Short name T578
Test name
Test status
Simulation time 58962196 ps
CPU time 1.47 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518916903 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1518916903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.4184737824
Short name T676
Test name
Test status
Simulation time 6643965899 ps
CPU time 42.3 seconds
Started Aug 28 07:58:40 PM UTC 24
Finished Aug 28 07:59:24 PM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184737824 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.4184737824
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.2685015695
Short name T707
Test name
Test status
Simulation time 6651330353 ps
CPU time 72.3 seconds
Started Aug 28 07:58:40 PM UTC 24
Finished Aug 28 07:59:54 PM UTC 24
Peak memory 220492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685015695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2685015695
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.4150367813
Short name T579
Test name
Test status
Simulation time 29579668 ps
CPU time 1.51 seconds
Started Aug 28 07:58:37 PM UTC 24
Finished Aug 28 07:58:40 PM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150367813 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.4150367813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.3067449743
Short name T605
Test name
Test status
Simulation time 18006850 ps
CPU time 1.06 seconds
Started Aug 28 07:58:45 PM UTC 24
Finished Aug 28 07:58:47 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067449743 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.3067449743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.299321568
Short name T598
Test name
Test status
Simulation time 15618068 ps
CPU time 1 seconds
Started Aug 28 07:58:43 PM UTC 24
Finished Aug 28 07:58:45 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299321568 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.299321568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.2710646321
Short name T590
Test name
Test status
Simulation time 37677381 ps
CPU time 1.21 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710646321 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2710646321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.4013345738
Short name T602
Test name
Test status
Simulation time 28753096 ps
CPU time 1.3 seconds
Started Aug 28 07:58:44 PM UTC 24
Finished Aug 28 07:58:46 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013345738 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.4013345738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.2262678809
Short name T588
Test name
Test status
Simulation time 65099253 ps
CPU time 1.5 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262678809 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2262678809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.3986233667
Short name T634
Test name
Test status
Simulation time 1411640732 ps
CPU time 12.05 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:55 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986233667 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3986233667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.2509817803
Short name T599
Test name
Test status
Simulation time 300651125 ps
CPU time 2.53 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:45 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509817803 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.2509817803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.2901581526
Short name T597
Test name
Test status
Simulation time 55078720 ps
CPU time 1.2 seconds
Started Aug 28 07:58:43 PM UTC 24
Finished Aug 28 07:58:45 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901581526 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.2901581526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.828528846
Short name T596
Test name
Test status
Simulation time 22132936 ps
CPU time 1.04 seconds
Started Aug 28 07:58:43 PM UTC 24
Finished Aug 28 07:58:45 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828528846 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.828528846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.2616531616
Short name T595
Test name
Test status
Simulation time 13139306 ps
CPU time 0.97 seconds
Started Aug 28 07:58:43 PM UTC 24
Finished Aug 28 07:58:45 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616531616
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.2616531616
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.20670466
Short name T589
Test name
Test status
Simulation time 42459195 ps
CPU time 1.33 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 210188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20670466 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.20670466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.1872208298
Short name T619
Test name
Test status
Simulation time 1018466314 ps
CPU time 5.26 seconds
Started Aug 28 07:58:44 PM UTC 24
Finished Aug 28 07:58:50 PM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872208298 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1872208298
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.265511905
Short name T587
Test name
Test status
Simulation time 40581191 ps
CPU time 1.38 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265511905 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.265511905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.487015823
Short name T654
Test name
Test status
Simulation time 4671401521 ps
CPU time 25.69 seconds
Started Aug 28 07:58:45 PM UTC 24
Finished Aug 28 07:59:12 PM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487015823 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.487015823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.4013984114
Short name T850
Test name
Test status
Simulation time 66463337045 ps
CPU time 240.15 seconds
Started Aug 28 07:58:44 PM UTC 24
Finished Aug 28 08:02:48 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013984114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.4013984114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.4005979246
Short name T591
Test name
Test status
Simulation time 52111114 ps
CPU time 1.52 seconds
Started Aug 28 07:58:41 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005979246 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.4005979246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.91405114
Short name T613
Test name
Test status
Simulation time 14530317 ps
CPU time 1.08 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:58:49 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91405114 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.91405114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1205050683
Short name T615
Test name
Test status
Simulation time 62537550 ps
CPU time 1.49 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:58:49 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205050683 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.1205050683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.2241912874
Short name T608
Test name
Test status
Simulation time 13611744 ps
CPU time 1.04 seconds
Started Aug 28 07:58:46 PM UTC 24
Finished Aug 28 07:58:48 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241912874 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2241912874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.1856427252
Short name T614
Test name
Test status
Simulation time 60476858 ps
CPU time 1.31 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:58:49 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856427252 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.1856427252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.478136071
Short name T611
Test name
Test status
Simulation time 98960559 ps
CPU time 1.68 seconds
Started Aug 28 07:58:45 PM UTC 24
Finished Aug 28 07:58:48 PM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478136071 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.478136071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.3954436081
Short name T647
Test name
Test status
Simulation time 1877854820 ps
CPU time 17.46 seconds
Started Aug 28 07:58:45 PM UTC 24
Finished Aug 28 07:59:04 PM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954436081 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3954436081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.3363492427
Short name T638
Test name
Test status
Simulation time 2247161867 ps
CPU time 10.06 seconds
Started Aug 28 07:58:46 PM UTC 24
Finished Aug 28 07:58:57 PM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363492427 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.3363492427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.1955312717
Short name T609
Test name
Test status
Simulation time 14740818 ps
CPU time 1.07 seconds
Started Aug 28 07:58:46 PM UTC 24
Finished Aug 28 07:58:48 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955312717 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.1955312717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.2206104309
Short name T616
Test name
Test status
Simulation time 84405398 ps
CPU time 1.66 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:58:50 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206104309
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.2206104309
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2093187185
Short name T612
Test name
Test status
Simulation time 73661787 ps
CPU time 1.51 seconds
Started Aug 28 07:58:46 PM UTC 24
Finished Aug 28 07:58:48 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093187185
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.2093187185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.2512012167
Short name T610
Test name
Test status
Simulation time 48940722 ps
CPU time 1.35 seconds
Started Aug 28 07:58:46 PM UTC 24
Finished Aug 28 07:58:48 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512012167 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2512012167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.1985923582
Short name T626
Test name
Test status
Simulation time 296118488 ps
CPU time 3.59 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:58:52 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985923582 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1985923582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.2440775394
Short name T606
Test name
Test status
Simulation time 19419305 ps
CPU time 1.11 seconds
Started Aug 28 07:58:45 PM UTC 24
Finished Aug 28 07:58:47 PM UTC 24
Peak memory 209912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440775394 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2440775394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.268631010
Short name T656
Test name
Test status
Simulation time 4846705934 ps
CPU time 28.72 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:59:17 PM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268631010 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.268631010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.692127900
Short name T679
Test name
Test status
Simulation time 7759700859 ps
CPU time 39.48 seconds
Started Aug 28 07:58:47 PM UTC 24
Finished Aug 28 07:59:28 PM UTC 24
Peak memory 220276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692127900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.692127900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.501788326
Short name T607
Test name
Test status
Simulation time 18543752 ps
CPU time 1.16 seconds
Started Aug 28 07:58:46 PM UTC 24
Finished Aug 28 07:58:48 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501788326 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.501788326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.114490347
Short name T617
Test name
Test status
Simulation time 42674382 ps
CPU time 0.9 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 07:59:36 PM UTC 24
Peak memory 210228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114490347 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.114490347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.2476900010
Short name T628
Test name
Test status
Simulation time 23924926 ps
CPU time 1.14 seconds
Started Aug 28 07:58:50 PM UTC 24
Finished Aug 28 07:58:52 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2476900010 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2476900010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.2488364728
Short name T684
Test name
Test status
Simulation time 23693554 ps
CPU time 1.03 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 07:59:33 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488364728 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.2488364728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.592905605
Short name T621
Test name
Test status
Simulation time 18874212 ps
CPU time 1.23 seconds
Started Aug 28 07:58:48 PM UTC 24
Finished Aug 28 07:58:51 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592905605 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.592905605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.836708199
Short name T640
Test name
Test status
Simulation time 1300934538 ps
CPU time 7.51 seconds
Started Aug 28 07:58:49 PM UTC 24
Finished Aug 28 07:58:57 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836708199 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.836708199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.4208515783
Short name T641
Test name
Test status
Simulation time 861389961 ps
CPU time 8.18 seconds
Started Aug 28 07:58:49 PM UTC 24
Finished Aug 28 07:58:58 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208515783 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.4208515783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.282138187
Short name T631
Test name
Test status
Simulation time 70837740 ps
CPU time 1.39 seconds
Started Aug 28 07:58:50 PM UTC 24
Finished Aug 28 07:58:52 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282138187 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.282138187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1842377077
Short name T629
Test name
Test status
Simulation time 15963067 ps
CPU time 1.12 seconds
Started Aug 28 07:58:50 PM UTC 24
Finished Aug 28 07:58:52 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842377077
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.1842377077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.865696751
Short name T627
Test name
Test status
Simulation time 17600363 ps
CPU time 1.03 seconds
Started Aug 28 07:58:50 PM UTC 24
Finished Aug 28 07:58:52 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865696751 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.865696751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.170671493
Short name T623
Test name
Test status
Simulation time 21955241 ps
CPU time 1.2 seconds
Started Aug 28 07:58:49 PM UTC 24
Finished Aug 28 07:58:51 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170671493 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.170671493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.1593172138
Short name T697
Test name
Test status
Simulation time 1635065691 ps
CPU time 4.86 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 07:59:40 PM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593172138 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1593172138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.1021082908
Short name T622
Test name
Test status
Simulation time 21658522 ps
CPU time 1.28 seconds
Started Aug 28 07:58:48 PM UTC 24
Finished Aug 28 07:58:51 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021082908 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1021082908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.1128777645
Short name T705
Test name
Test status
Simulation time 4641829116 ps
CPU time 17.17 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 07:59:53 PM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128777645 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1128777645
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.1662387813
Short name T836
Test name
Test status
Simulation time 3869186006 ps
CPU time 60.63 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 08:00:37 PM UTC 24
Peak memory 224300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662387813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1662387813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.2367986228
Short name T625
Test name
Test status
Simulation time 41975690 ps
CPU time 1.4 seconds
Started Aug 28 07:58:49 PM UTC 24
Finished Aug 28 07:58:51 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367986228 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2367986228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.3917461353
Short name T661
Test name
Test status
Simulation time 16445494 ps
CPU time 0.9 seconds
Started Aug 28 07:58:56 PM UTC 24
Finished Aug 28 07:59:21 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917461353 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.3917461353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1627048936
Short name T689
Test name
Test status
Simulation time 49459837 ps
CPU time 1.06 seconds
Started Aug 28 07:58:54 PM UTC 24
Finished Aug 28 07:59:36 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627048936 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.1627048936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.3834926894
Short name T665
Test name
Test status
Simulation time 30992276 ps
CPU time 0.92 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834926894 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3834926894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.1971513666
Short name T691
Test name
Test status
Simulation time 167897921 ps
CPU time 1.38 seconds
Started Aug 28 07:58:54 PM UTC 24
Finished Aug 28 07:59:37 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971513666 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1971513666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.2972669317
Short name T692
Test name
Test status
Simulation time 80883941 ps
CPU time 1.13 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 07:59:37 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972669317 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2972669317
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.2826605576
Short name T678
Test name
Test status
Simulation time 941834923 ps
CPU time 5.08 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:26 PM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826605576 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2826605576
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.1442834633
Short name T672
Test name
Test status
Simulation time 136952158 ps
CPU time 1.91 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:23 PM UTC 24
Peak memory 209740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442834633 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.1442834633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.3955632970
Short name T655
Test name
Test status
Simulation time 48929609 ps
CPU time 0.97 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:16 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955632970 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.3955632970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.3202694396
Short name T670
Test name
Test status
Simulation time 15602648 ps
CPU time 1.01 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202694396
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.3202694396
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1690300555
Short name T668
Test name
Test status
Simulation time 21905238 ps
CPU time 1.09 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690300555
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.1690300555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.1886282072
Short name T666
Test name
Test status
Simulation time 40189599 ps
CPU time 1.05 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886282072 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1886282072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.929448819
Short name T698
Test name
Test status
Simulation time 2477959492 ps
CPU time 7.33 seconds
Started Aug 28 07:58:54 PM UTC 24
Finished Aug 28 07:59:43 PM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929448819 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.929448819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.1625390563
Short name T690
Test name
Test status
Simulation time 17496976 ps
CPU time 0.99 seconds
Started Aug 28 07:58:51 PM UTC 24
Finished Aug 28 07:59:36 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625390563 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1625390563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.67842276
Short name T704
Test name
Test status
Simulation time 8192113610 ps
CPU time 31.35 seconds
Started Aug 28 07:58:56 PM UTC 24
Finished Aug 28 07:59:52 PM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67842276 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.67842276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.2101748923
Short name T842
Test name
Test status
Simulation time 17506006768 ps
CPU time 103.42 seconds
Started Aug 28 07:58:55 PM UTC 24
Finished Aug 28 08:01:21 PM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101748923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2101748923
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.1257529930
Short name T664
Test name
Test status
Simulation time 21874974 ps
CPU time 0.91 seconds
Started Aug 28 07:58:53 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257529930 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1257529930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.3062869743
Short name T191
Test name
Test status
Simulation time 14210146 ps
CPU time 0.96 seconds
Started Aug 28 07:56:03 PM UTC 24
Finished Aug 28 07:56:05 PM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062869743 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.3062869743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.3942791798
Short name T189
Test name
Test status
Simulation time 21000847 ps
CPU time 1.21 seconds
Started Aug 28 07:56:02 PM UTC 24
Finished Aug 28 07:56:04 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942791798 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.3942791798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.15091701
Short name T169
Test name
Test status
Simulation time 13472288 ps
CPU time 1.08 seconds
Started Aug 28 07:56:01 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15091701 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.15091701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.2384354851
Short name T155
Test name
Test status
Simulation time 63007158 ps
CPU time 1.37 seconds
Started Aug 28 07:56:02 PM UTC 24
Finished Aug 28 07:56:04 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384354851 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2384354851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.775689440
Short name T187
Test name
Test status
Simulation time 60174809 ps
CPU time 1.45 seconds
Started Aug 28 07:56:00 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775689440 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.775689440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.607511060
Short name T36
Test name
Test status
Simulation time 855604404 ps
CPU time 6.06 seconds
Started Aug 28 07:56:00 PM UTC 24
Finished Aug 28 07:56:08 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607511060 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.607511060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.912671878
Short name T84
Test name
Test status
Simulation time 1586970550 ps
CPU time 12.55 seconds
Started Aug 28 07:56:00 PM UTC 24
Finished Aug 28 07:56:14 PM UTC 24
Peak memory 210656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912671878 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.912671878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.915925249
Short name T184
Test name
Test status
Simulation time 164180687 ps
CPU time 1.59 seconds
Started Aug 28 07:56:01 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915925249 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.915925249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1560368978
Short name T188
Test name
Test status
Simulation time 27505649 ps
CPU time 1.12 seconds
Started Aug 28 07:56:02 PM UTC 24
Finished Aug 28 07:56:04 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560368978
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.1560368978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.231593005
Short name T190
Test name
Test status
Simulation time 83499688 ps
CPU time 1.42 seconds
Started Aug 28 07:56:02 PM UTC 24
Finished Aug 28 07:56:04 PM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231593005 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.231593005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.3307063982
Short name T185
Test name
Test status
Simulation time 16520288 ps
CPU time 1.16 seconds
Started Aug 28 07:56:01 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307063982 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3307063982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.2022414293
Short name T83
Test name
Test status
Simulation time 1014685489 ps
CPU time 5.93 seconds
Started Aug 28 07:56:03 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2022414293 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2022414293
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.253232101
Short name T58
Test name
Test status
Simulation time 157999596 ps
CPU time 2.89 seconds
Started Aug 28 07:56:03 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 242600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253232101 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.253232101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.675635017
Short name T154
Test name
Test status
Simulation time 16835757 ps
CPU time 1.17 seconds
Started Aug 28 07:56:00 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675635017 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.675635017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.786940507
Short name T179
Test name
Test status
Simulation time 79584036 ps
CPU time 1.71 seconds
Started Aug 28 07:56:03 PM UTC 24
Finished Aug 28 07:56:06 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786940507 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.786940507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.90894062
Short name T75
Test name
Test status
Simulation time 13142941516 ps
CPU time 85.87 seconds
Started Aug 28 07:56:03 PM UTC 24
Finished Aug 28 07:57:31 PM UTC 24
Peak memory 220424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90894062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.90894062
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.2500352732
Short name T186
Test name
Test status
Simulation time 19415967 ps
CPU time 1.22 seconds
Started Aug 28 07:56:01 PM UTC 24
Finished Aug 28 07:56:03 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2500352732 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2500352732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.3045767338
Short name T671
Test name
Test status
Simulation time 49962413 ps
CPU time 0.88 seconds
Started Aug 28 07:59:07 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045767338 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.3045767338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1577216655
Short name T669
Test name
Test status
Simulation time 21680881 ps
CPU time 0.89 seconds
Started Aug 28 07:59:03 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577216655 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.1577216655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.1561337194
Short name T662
Test name
Test status
Simulation time 28581214 ps
CPU time 0.82 seconds
Started Aug 28 07:59:00 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561337194 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1561337194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.60246535
Short name T677
Test name
Test status
Simulation time 21822216 ps
CPU time 0.78 seconds
Started Aug 28 07:59:04 PM UTC 24
Finished Aug 28 07:59:26 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60246535 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.60246535
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.1868146220
Short name T657
Test name
Test status
Simulation time 20290761 ps
CPU time 0.92 seconds
Started Aug 28 07:58:57 PM UTC 24
Finished Aug 28 07:59:19 PM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868146220 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1868146220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.3327732810
Short name T680
Test name
Test status
Simulation time 1818787710 ps
CPU time 8.88 seconds
Started Aug 28 07:58:58 PM UTC 24
Finished Aug 28 07:59:29 PM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327732810 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.3327732810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.209256826
Short name T685
Test name
Test status
Simulation time 403347305 ps
CPU time 2.2 seconds
Started Aug 28 07:58:58 PM UTC 24
Finished Aug 28 07:59:34 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209256826 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.209256826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.1801470277
Short name T667
Test name
Test status
Simulation time 32119474 ps
CPU time 1.15 seconds
Started Aug 28 07:59:00 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801470277 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.1801470277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.4236041723
Short name T682
Test name
Test status
Simulation time 52012587 ps
CPU time 0.87 seconds
Started Aug 28 07:59:01 PM UTC 24
Finished Aug 28 07:59:33 PM UTC 24
Peak memory 209000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236041723
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.4236041723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2561172810
Short name T687
Test name
Test status
Simulation time 19874194 ps
CPU time 0.82 seconds
Started Aug 28 07:59:01 PM UTC 24
Finished Aug 28 07:59:36 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561172810
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.2561172810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.3050559555
Short name T663
Test name
Test status
Simulation time 16364320 ps
CPU time 0.92 seconds
Started Aug 28 07:58:59 PM UTC 24
Finished Aug 28 07:59:22 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050559555 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.3050559555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.1964300793
Short name T693
Test name
Test status
Simulation time 408167518 ps
CPU time 1.69 seconds
Started Aug 28 07:59:04 PM UTC 24
Finished Aug 28 07:59:37 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964300793 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.1964300793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.154174066
Short name T659
Test name
Test status
Simulation time 79958889 ps
CPU time 1.16 seconds
Started Aug 28 07:58:57 PM UTC 24
Finished Aug 28 07:59:21 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154174066 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.154174066
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.3498085087
Short name T734
Test name
Test status
Simulation time 8002178844 ps
CPU time 43.51 seconds
Started Aug 28 07:59:05 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498085087 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.3498085087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.261322891
Short name T846
Test name
Test status
Simulation time 28121726908 ps
CPU time 137.75 seconds
Started Aug 28 07:59:05 PM UTC 24
Finished Aug 28 08:01:46 PM UTC 24
Peak memory 220272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261322891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.261322891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.1447907914
Short name T660
Test name
Test status
Simulation time 68767881 ps
CPU time 0.95 seconds
Started Aug 28 07:58:59 PM UTC 24
Finished Aug 28 07:59:21 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447907914 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1447907914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.2593306519
Short name T716
Test name
Test status
Simulation time 17233393 ps
CPU time 0.72 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593306519 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.2593306519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2908541358
Short name T717
Test name
Test status
Simulation time 50355175 ps
CPU time 0.85 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908541358 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.2908541358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.2757525466
Short name T710
Test name
Test status
Simulation time 13533690 ps
CPU time 0.68 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:17 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757525466 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2757525466
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.3824119443
Short name T711
Test name
Test status
Simulation time 17342974 ps
CPU time 0.79 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824119443 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.3824119443
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.4014741890
Short name T694
Test name
Test status
Simulation time 28685881 ps
CPU time 0.79 seconds
Started Aug 28 07:59:26 PM UTC 24
Finished Aug 28 07:59:37 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014741890 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.4014741890
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.464940033
Short name T702
Test name
Test status
Simulation time 1157166355 ps
CPU time 9.41 seconds
Started Aug 28 07:59:26 PM UTC 24
Finished Aug 28 07:59:46 PM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464940033 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.464940033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.1734631917
Short name T768
Test name
Test status
Simulation time 1585529985 ps
CPU time 8.66 seconds
Started Aug 28 08:00:15 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734631917 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.1734631917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.1649083834
Short name T712
Test name
Test status
Simulation time 61954893 ps
CPU time 1.02 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649083834 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.1649083834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.4223302532
Short name T714
Test name
Test status
Simulation time 74808092 ps
CPU time 0.97 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223302532
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.4223302532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3977446938
Short name T713
Test name
Test status
Simulation time 37232843 ps
CPU time 0.89 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977446938
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.3977446938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.2884265089
Short name T708
Test name
Test status
Simulation time 18508492 ps
CPU time 0.77 seconds
Started Aug 28 08:00:15 PM UTC 24
Finished Aug 28 08:00:16 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884265089 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2884265089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.605240745
Short name T718
Test name
Test status
Simulation time 104168104 ps
CPU time 0.88 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605240745 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.605240745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.2167375807
Short name T695
Test name
Test status
Simulation time 23520775 ps
CPU time 0.88 seconds
Started Aug 28 07:59:26 PM UTC 24
Finished Aug 28 07:59:38 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167375807 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2167375807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.2284350047
Short name T840
Test name
Test status
Simulation time 8273635559 ps
CPU time 36.47 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:54 PM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284350047 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.2284350047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.485570636
Short name T849
Test name
Test status
Simulation time 19245938422 ps
CPU time 129.42 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:02:28 PM UTC 24
Peak memory 220216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485570636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.485570636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.3191741172
Short name T709
Test name
Test status
Simulation time 67392312 ps
CPU time 1.1 seconds
Started Aug 28 08:00:15 PM UTC 24
Finished Aug 28 08:00:17 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191741172 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.3191741172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.1608262203
Short name T729
Test name
Test status
Simulation time 36737476 ps
CPU time 0.84 seconds
Started Aug 28 08:00:17 PM UTC 24
Finished Aug 28 08:00:19 PM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608262203 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.1608262203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1088180759
Short name T730
Test name
Test status
Simulation time 56291163 ps
CPU time 1.06 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:19 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088180759 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.1088180759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.1019188187
Short name T721
Test name
Test status
Simulation time 15885674 ps
CPU time 0.8 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019188187 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1019188187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.306745647
Short name T727
Test name
Test status
Simulation time 42249297 ps
CPU time 0.91 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:19 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306745647 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.306745647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.467073924
Short name T723
Test name
Test status
Simulation time 61619748 ps
CPU time 0.91 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467073924 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.467073924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.4005915771
Short name T831
Test name
Test status
Simulation time 1757453160 ps
CPU time 16.72 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:34 PM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005915771 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.4005915771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.510921622
Short name T835
Test name
Test status
Simulation time 1935203461 ps
CPU time 17.82 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:35 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510921622 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.510921622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.1006799287
Short name T726
Test name
Test status
Simulation time 97783857 ps
CPU time 1.12 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006799287 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.1006799287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3537738009
Short name T725
Test name
Test status
Simulation time 23693088 ps
CPU time 0.86 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537738009
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.3537738009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2412985960
Short name T722
Test name
Test status
Simulation time 19317357 ps
CPU time 0.74 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412985960
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.2412985960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.3833757423
Short name T719
Test name
Test status
Simulation time 23131428 ps
CPU time 0.72 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833757423 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3833757423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.4207303669
Short name T754
Test name
Test status
Simulation time 694681319 ps
CPU time 3.52 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207303669 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.4207303669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.2365606677
Short name T720
Test name
Test status
Simulation time 26819972 ps
CPU time 0.95 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365606677 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2365606677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.2511231321
Short name T791
Test name
Test status
Simulation time 818043126 ps
CPU time 7.83 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 210292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511231321 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.2511231321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.3441695697
Short name T166
Test name
Test status
Simulation time 2771762417 ps
CPU time 40.25 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:58 PM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441695697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3441695697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.3715266094
Short name T724
Test name
Test status
Simulation time 69057421 ps
CPU time 0.94 seconds
Started Aug 28 08:00:16 PM UTC 24
Finished Aug 28 08:00:18 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715266094 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3715266094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.3912213206
Short name T741
Test name
Test status
Simulation time 13518557 ps
CPU time 0.76 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912213206 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.3912213206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2948518589
Short name T738
Test name
Test status
Simulation time 20786096 ps
CPU time 0.82 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948518589 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.2948518589
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.3384294613
Short name T733
Test name
Test status
Simulation time 13404234 ps
CPU time 0.83 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384294613 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3384294613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.3369359206
Short name T740
Test name
Test status
Simulation time 21677517 ps
CPU time 0.84 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 209992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369359206 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.3369359206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.3254674723
Short name T731
Test name
Test status
Simulation time 29287128 ps
CPU time 1.02 seconds
Started Aug 28 08:00:17 PM UTC 24
Finished Aug 28 08:00:19 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254674723 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3254674723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.3745065313
Short name T759
Test name
Test status
Simulation time 324287801 ps
CPU time 2.99 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:22 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745065313 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.3745065313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.3133961093
Short name T829
Test name
Test status
Simulation time 1461375518 ps
CPU time 11.38 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:31 PM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133961093 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.3133961093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.2880761001
Short name T744
Test name
Test status
Simulation time 92986991 ps
CPU time 1.33 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880761001 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.2880761001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.378350778
Short name T736
Test name
Test status
Simulation time 19693466 ps
CPU time 0.82 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378350778 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.378350778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2552491445
Short name T735
Test name
Test status
Simulation time 66582462 ps
CPU time 0.91 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552491445
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.2552491445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.4220649829
Short name T732
Test name
Test status
Simulation time 15745219 ps
CPU time 0.67 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 210056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220649829 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.4220649829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.3236444964
Short name T760
Test name
Test status
Simulation time 619484578 ps
CPU time 3.35 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:23 PM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236444964 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3236444964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.788394585
Short name T728
Test name
Test status
Simulation time 18282530 ps
CPU time 0.81 seconds
Started Aug 28 08:00:17 PM UTC 24
Finished Aug 28 08:00:19 PM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788394585 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.788394585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.3810240723
Short name T800
Test name
Test status
Simulation time 1386750618 ps
CPU time 7.51 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810240723 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.3810240723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.1812877331
Short name T168
Test name
Test status
Simulation time 4460898496 ps
CPU time 57.17 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:01:17 PM UTC 24
Peak memory 227308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812877331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1812877331
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.2448162702
Short name T739
Test name
Test status
Simulation time 138018379 ps
CPU time 1.16 seconds
Started Aug 28 08:00:18 PM UTC 24
Finished Aug 28 08:00:20 PM UTC 24
Peak memory 209924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448162702 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2448162702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.594215823
Short name T753
Test name
Test status
Simulation time 12135637 ps
CPU time 0.88 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594215823 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.594215823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1754771464
Short name T749
Test name
Test status
Simulation time 26462084 ps
CPU time 0.81 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754771464 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.1754771464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.837910720
Short name T748
Test name
Test status
Simulation time 36302788 ps
CPU time 0.85 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837910720 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.837910720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.638967545
Short name T756
Test name
Test status
Simulation time 101083911 ps
CPU time 1.02 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638967545 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.638967545
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.1008562012
Short name T745
Test name
Test status
Simulation time 32173686 ps
CPU time 0.99 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 209768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008562012 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1008562012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.376157743
Short name T802
Test name
Test status
Simulation time 1044066403 ps
CPU time 7.55 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376157743 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.376157743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.3879128266
Short name T830
Test name
Test status
Simulation time 2060160544 ps
CPU time 11.47 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:31 PM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879128266 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.3879128266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.769839140
Short name T747
Test name
Test status
Simulation time 48905991 ps
CPU time 0.93 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769839140 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.769839140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.662659647
Short name T755
Test name
Test status
Simulation time 75213452 ps
CPU time 1.05 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662659647 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.662659647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.762941542
Short name T746
Test name
Test status
Simulation time 17942299 ps
CPU time 0.79 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762941542 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.762941542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.3866844370
Short name T742
Test name
Test status
Simulation time 39028808 ps
CPU time 0.81 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866844370 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3866844370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.4060012456
Short name T801
Test name
Test status
Simulation time 1693125762 ps
CPU time 7.08 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060012456 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.4060012456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.441657690
Short name T743
Test name
Test status
Simulation time 73472489 ps
CPU time 1.02 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441657690 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.441657690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.2591565024
Short name T797
Test name
Test status
Simulation time 908538042 ps
CPU time 6.39 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591565024 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.2591565024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.2459837736
Short name T847
Test name
Test status
Simulation time 13736289033 ps
CPU time 92.89 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:01:54 PM UTC 24
Peak memory 220224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459837736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.2459837736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.1362057056
Short name T750
Test name
Test status
Simulation time 36523944 ps
CPU time 1.1 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362057056 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1362057056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.348015685
Short name T715
Test name
Test status
Simulation time 67737522 ps
CPU time 0.98 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348015685 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.348015685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.466587567
Short name T762
Test name
Test status
Simulation time 37851313 ps
CPU time 0.95 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466587567 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.466587567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.844994477
Short name T761
Test name
Test status
Simulation time 21830246 ps
CPU time 0.9 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844994477 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.844994477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.609798584
Short name T767
Test name
Test status
Simulation time 113526941 ps
CPU time 1.26 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609798584 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.609798584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.1087040872
Short name T752
Test name
Test status
Simulation time 23082749 ps
CPU time 0.84 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087040872 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1087040872
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.2485417356
Short name T839
Test name
Test status
Simulation time 2477683485 ps
CPU time 21.21 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:42 PM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485417356 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.2485417356
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.150231722
Short name T819
Test name
Test status
Simulation time 1600032351 ps
CPU time 8.06 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150231722 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.150231722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.3193366952
Short name T764
Test name
Test status
Simulation time 34244726 ps
CPU time 1 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193366952 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.3193366952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2442704606
Short name T763
Test name
Test status
Simulation time 22479999 ps
CPU time 0.86 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442704606
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.2442704606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.4198831718
Short name T777
Test name
Test status
Simulation time 305009797 ps
CPU time 1.9 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198831718
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.4198831718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.1484042979
Short name T751
Test name
Test status
Simulation time 23292321 ps
CPU time 0.72 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484042979 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1484042979
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.2993675030
Short name T766
Test name
Test status
Simulation time 72838195 ps
CPU time 1 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993675030 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2993675030
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.3271930738
Short name T757
Test name
Test status
Simulation time 59736301 ps
CPU time 0.98 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:21 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271930738 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3271930738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.449178920
Short name T793
Test name
Test status
Simulation time 462126393 ps
CPU time 2.62 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449178920 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.449178920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.1776348430
Short name T841
Test name
Test status
Simulation time 5472954202 ps
CPU time 41.75 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:01:05 PM UTC 24
Peak memory 224392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776348430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.1776348430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.2452804665
Short name T758
Test name
Test status
Simulation time 63795417 ps
CPU time 1.22 seconds
Started Aug 28 08:00:19 PM UTC 24
Finished Aug 28 08:00:22 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452804665 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2452804665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.3023557577
Short name T774
Test name
Test status
Simulation time 15693131 ps
CPU time 0.92 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023557577 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.3023557577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1996330008
Short name T773
Test name
Test status
Simulation time 20165103 ps
CPU time 0.95 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996330008 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1996330008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.3025294011
Short name T769
Test name
Test status
Simulation time 48704789 ps
CPU time 0.99 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025294011 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3025294011
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.2814895802
Short name T772
Test name
Test status
Simulation time 45913342 ps
CPU time 1.01 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814895802 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.2814895802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.2612445926
Short name T765
Test name
Test status
Simulation time 17780350 ps
CPU time 0.75 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612445926 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2612445926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.3152212679
Short name T808
Test name
Test status
Simulation time 562836295 ps
CPU time 4.52 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152212679 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.3152212679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.2921174733
Short name T799
Test name
Test status
Simulation time 627543829 ps
CPU time 3.5 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921174733 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.2921174733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.1245990098
Short name T779
Test name
Test status
Simulation time 77710008 ps
CPU time 1.34 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 208896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245990098 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.1245990098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3988605351
Short name T770
Test name
Test status
Simulation time 32867824 ps
CPU time 0.84 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988605351
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.3988605351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3045164301
Short name T771
Test name
Test status
Simulation time 36971496 ps
CPU time 0.96 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045164301
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.3045164301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.3210602199
Short name T737
Test name
Test status
Simulation time 29810254 ps
CPU time 0.86 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:24 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210602199 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3210602199
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.3040983341
Short name T798
Test name
Test status
Simulation time 562788134 ps
CPU time 2.79 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040983341 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.3040983341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.1122024222
Short name T778
Test name
Test status
Simulation time 165469914 ps
CPU time 1.65 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122024222 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1122024222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.3906218771
Short name T790
Test name
Test status
Simulation time 154524474 ps
CPU time 1.66 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906218771 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.3906218771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.3621939237
Short name T167
Test name
Test status
Simulation time 6622360434 ps
CPU time 35.6 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:01:00 PM UTC 24
Peak memory 220404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621939237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.3621939237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.3920655236
Short name T775
Test name
Test status
Simulation time 65530733 ps
CPU time 1.24 seconds
Started Aug 28 08:00:22 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920655236 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3920655236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.3660122703
Short name T788
Test name
Test status
Simulation time 23998561 ps
CPU time 0.86 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660122703 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.3660122703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.1458349938
Short name T794
Test name
Test status
Simulation time 240619093 ps
CPU time 1.47 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458349938 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.1458349938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.383638364
Short name T781
Test name
Test status
Simulation time 59768873 ps
CPU time 0.98 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383638364 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.383638364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.1673961560
Short name T786
Test name
Test status
Simulation time 18971149 ps
CPU time 0.99 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673961560 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.1673961560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.2263073694
Short name T782
Test name
Test status
Simulation time 73692483 ps
CPU time 1.08 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263073694 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.2263073694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.329890905
Short name T796
Test name
Test status
Simulation time 360378961 ps
CPU time 2.4 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329890905 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.329890905
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1929018873
Short name T828
Test name
Test status
Simulation time 1601494261 ps
CPU time 6.32 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:30 PM UTC 24
Peak memory 210652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929018873 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.1929018873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.1895476240
Short name T785
Test name
Test status
Simulation time 32487709 ps
CPU time 1.02 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895476240 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.1895476240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1792464758
Short name T784
Test name
Test status
Simulation time 116422486 ps
CPU time 1.02 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792464758
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.1792464758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.934763186
Short name T783
Test name
Test status
Simulation time 22363233 ps
CPU time 0.98 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934763186 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.934763186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.1696667256
Short name T776
Test name
Test status
Simulation time 18325208 ps
CPU time 0.82 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696667256 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.1696667256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.2417727921
Short name T816
Test name
Test status
Simulation time 860987607 ps
CPU time 4.14 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417727921 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2417727921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.4262263068
Short name T780
Test name
Test status
Simulation time 23225156 ps
CPU time 0.99 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262263068 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.4262263068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3925328171
Short name T795
Test name
Test status
Simulation time 155763016 ps
CPU time 1.42 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925328171 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.3925328171
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.1658426463
Short name T843
Test name
Test status
Simulation time 10422435612 ps
CPU time 70.5 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:01:36 PM UTC 24
Peak memory 227496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658426463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1658426463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.3965280245
Short name T787
Test name
Test status
Simulation time 39142759 ps
CPU time 1.2 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965280245 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.3965280245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.4278355660
Short name T809
Test name
Test status
Simulation time 16682985 ps
CPU time 0.81 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278355660 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.4278355660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3183350007
Short name T811
Test name
Test status
Simulation time 26143879 ps
CPU time 1.08 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183350007 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.3183350007
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.2786486564
Short name T807
Test name
Test status
Simulation time 25224964 ps
CPU time 1.01 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 209104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786486564 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2786486564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.1771224372
Short name T815
Test name
Test status
Simulation time 79383258 ps
CPU time 1.23 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 209496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771224372 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.1771224372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.4121719715
Short name T792
Test name
Test status
Simulation time 44283278 ps
CPU time 1.23 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:26 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121719715 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.4121719715
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.1757431178
Short name T838
Test name
Test status
Simulation time 2359062346 ps
CPU time 12.88 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:40 PM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757431178 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1757431178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.2016649818
Short name T832
Test name
Test status
Simulation time 856252766 ps
CPU time 7.86 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:35 PM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016649818 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.2016649818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.3537667891
Short name T806
Test name
Test status
Simulation time 30761694 ps
CPU time 0.92 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537667891 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.3537667891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.4162253241
Short name T805
Test name
Test status
Simulation time 17595891 ps
CPU time 0.89 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162253241
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.4162253241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2092365158
Short name T810
Test name
Test status
Simulation time 24658375 ps
CPU time 1.06 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092365158
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.2092365158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.3532994708
Short name T803
Test name
Test status
Simulation time 21120428 ps
CPU time 0.72 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:27 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532994708 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3532994708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.1788093146
Short name T822
Test name
Test status
Simulation time 201214651 ps
CPU time 1.47 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 209452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788093146 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1788093146
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.765723694
Short name T789
Test name
Test status
Simulation time 23141785 ps
CPU time 1.04 seconds
Started Aug 28 08:00:23 PM UTC 24
Finished Aug 28 08:00:25 PM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765723694 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.765723694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.2000007751
Short name T844
Test name
Test status
Simulation time 8527262672 ps
CPU time 76.2 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:01:44 PM UTC 24
Peak memory 210848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000007751 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.2000007751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.2633586817
Short name T848
Test name
Test status
Simulation time 15768948868 ps
CPU time 99.87 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:02:08 PM UTC 24
Peak memory 220464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633586817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2633586817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.509789376
Short name T804
Test name
Test status
Simulation time 33220623 ps
CPU time 0.82 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509789376 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.509789376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.1576400921
Short name T821
Test name
Test status
Simulation time 18696766 ps
CPU time 0.79 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1576400921 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.1576400921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.614691898
Short name T825
Test name
Test status
Simulation time 77131930 ps
CPU time 1.15 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614691898 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.614691898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.3207146881
Short name T814
Test name
Test status
Simulation time 18017077 ps
CPU time 0.85 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207146881 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3207146881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.4116292016
Short name T823
Test name
Test status
Simulation time 22501920 ps
CPU time 0.93 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116292016 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.4116292016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.2828084168
Short name T818
Test name
Test status
Simulation time 109499364 ps
CPU time 1.27 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828084168 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2828084168
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.2124516083
Short name T833
Test name
Test status
Simulation time 796728174 ps
CPU time 7.36 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:35 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124516083 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2124516083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.1772880233
Short name T834
Test name
Test status
Simulation time 1107052729 ps
CPU time 7.05 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:35 PM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772880233 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.1772880233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.2256262106
Short name T827
Test name
Test status
Simulation time 184555845 ps
CPU time 1.72 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256262106 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.2256262106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3344860229
Short name T826
Test name
Test status
Simulation time 88694636 ps
CPU time 1.25 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344860229
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.3344860229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3008233548
Short name T820
Test name
Test status
Simulation time 66152364 ps
CPU time 0.99 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008233548
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.3008233548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.45586228
Short name T812
Test name
Test status
Simulation time 13541936 ps
CPU time 0.79 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45586228 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.45586228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.3512665710
Short name T824
Test name
Test status
Simulation time 46685021 ps
CPU time 0.98 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512665710 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3512665710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.3489301704
Short name T813
Test name
Test status
Simulation time 60830901 ps
CPU time 1.04 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:28 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489301704 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3489301704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.4174812921
Short name T837
Test name
Test status
Simulation time 1369989051 ps
CPU time 11.47 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:00:39 PM UTC 24
Peak memory 210384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174812921 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.4174812921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.1137435297
Short name T845
Test name
Test status
Simulation time 10128641449 ps
CPU time 76.87 seconds
Started Aug 28 08:00:27 PM UTC 24
Finished Aug 28 08:01:46 PM UTC 24
Peak memory 227304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137435297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.1137435297
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.1797463177
Short name T817
Test name
Test status
Simulation time 53179412 ps
CPU time 1.1 seconds
Started Aug 28 08:00:26 PM UTC 24
Finished Aug 28 08:00:29 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797463177 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1797463177
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.3209441749
Short name T198
Test name
Test status
Simulation time 14531431 ps
CPU time 0.97 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:08 PM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209441749 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.3209441749
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1882122718
Short name T182
Test name
Test status
Simulation time 28674621 ps
CPU time 1.15 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:08 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882122718 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.1882122718
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.2919385497
Short name T170
Test name
Test status
Simulation time 14627337 ps
CPU time 1.13 seconds
Started Aug 28 07:56:05 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919385497 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2919385497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.1198614562
Short name T197
Test name
Test status
Simulation time 28897286 ps
CPU time 1.15 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:08 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198614562 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.1198614562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.2711674315
Short name T181
Test name
Test status
Simulation time 26062694 ps
CPU time 1.34 seconds
Started Aug 28 07:56:04 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711674315 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2711674315
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.4176191012
Short name T12
Test name
Test status
Simulation time 921968184 ps
CPU time 8.57 seconds
Started Aug 28 07:56:04 PM UTC 24
Finished Aug 28 07:56:14 PM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176191012 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.4176191012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.4230779067
Short name T120
Test name
Test status
Simulation time 141482249 ps
CPU time 2.25 seconds
Started Aug 28 07:56:05 PM UTC 24
Finished Aug 28 07:56:08 PM UTC 24
Peak memory 210464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230779067 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.4230779067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.1704133489
Short name T196
Test name
Test status
Simulation time 19367631 ps
CPU time 1.16 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:08 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704133489
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.1704133489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1828265961
Short name T156
Test name
Test status
Simulation time 20978506 ps
CPU time 1.29 seconds
Started Aug 28 07:56:05 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828265961
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.1828265961
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.3966761637
Short name T194
Test name
Test status
Simulation time 83485605 ps
CPU time 1.37 seconds
Started Aug 28 07:56:05 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966761637 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3966761637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.410988240
Short name T146
Test name
Test status
Simulation time 605559385 ps
CPU time 3.62 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:11 PM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410988240 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.410988240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.2401371484
Short name T192
Test name
Test status
Simulation time 17760010 ps
CPU time 1.06 seconds
Started Aug 28 07:56:03 PM UTC 24
Finished Aug 28 07:56:05 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401371484 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2401371484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.4199404330
Short name T13
Test name
Test status
Simulation time 1731251558 ps
CPU time 8.39 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:16 PM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199404330 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.4199404330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.2465607650
Short name T73
Test name
Test status
Simulation time 4560802238 ps
CPU time 51.23 seconds
Started Aug 28 07:56:06 PM UTC 24
Finished Aug 28 07:56:59 PM UTC 24
Peak memory 220232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465607650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.2465607650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.3093263412
Short name T193
Test name
Test status
Simulation time 23734082 ps
CPU time 1.27 seconds
Started Aug 28 07:56:05 PM UTC 24
Finished Aug 28 07:56:07 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093263412 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3093263412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.223328099
Short name T202
Test name
Test status
Simulation time 114715557 ps
CPU time 1 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223328099 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.223328099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.441000304
Short name T80
Test name
Test status
Simulation time 14348238 ps
CPU time 0.79 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:18 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441000304 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.441000304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.4242933530
Short name T171
Test name
Test status
Simulation time 19270304 ps
CPU time 0.97 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242933530 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.4242933530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.2779464444
Short name T81
Test name
Test status
Simulation time 19887689 ps
CPU time 0.92 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:18 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779464444 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.2779464444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.3138325093
Short name T199
Test name
Test status
Simulation time 18958807 ps
CPU time 1.19 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138325093 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3138325093
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.66417981
Short name T14
Test name
Test status
Simulation time 1287617893 ps
CPU time 8.07 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:17 PM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66417981 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.66417981
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.1858944376
Short name T200
Test name
Test status
Simulation time 2399633965 ps
CPU time 12.32 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:21 PM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858944376 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.1858944376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.3717416431
Short name T143
Test name
Test status
Simulation time 79281879 ps
CPU time 1.36 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717416431 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.3717416431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.3977998625
Short name T144
Test name
Test status
Simulation time 77989968 ps
CPU time 1.43 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977998625
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.3977998625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.337489077
Short name T141
Test name
Test status
Simulation time 18951492 ps
CPU time 1.19 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337489077 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.337489077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.1638376368
Short name T142
Test name
Test status
Simulation time 143387384 ps
CPU time 1.38 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638376368 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1638376368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.2108560716
Short name T157
Test name
Test status
Simulation time 1013305104 ps
CPU time 5.14 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:23 PM UTC 24
Peak memory 210704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108560716 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2108560716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.4078909871
Short name T136
Test name
Test status
Simulation time 21677990 ps
CPU time 1.29 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:10 PM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078909871 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.4078909871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.1368111012
Short name T296
Test name
Test status
Simulation time 5769875120 ps
CPU time 27.49 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:45 PM UTC 24
Peak memory 210812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368111012 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.1368111012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.1679927605
Short name T76
Test name
Test status
Simulation time 4726890049 ps
CPU time 44.59 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:58:03 PM UTC 24
Peak memory 227440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679927605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.1679927605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.662282224
Short name T145
Test name
Test status
Simulation time 97994536 ps
CPU time 1.78 seconds
Started Aug 28 07:56:08 PM UTC 24
Finished Aug 28 07:56:11 PM UTC 24
Peak memory 208880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662282224 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.662282224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.731995224
Short name T212
Test name
Test status
Simulation time 46815046 ps
CPU time 0.88 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731995224 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.731995224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2672033349
Short name T99
Test name
Test status
Simulation time 32499271 ps
CPU time 0.91 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672033349 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.2672033349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.141554267
Short name T172
Test name
Test status
Simulation time 40076286 ps
CPU time 0.83 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 209024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141554267 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.141554267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.974201870
Short name T207
Test name
Test status
Simulation time 25992171 ps
CPU time 0.97 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974201870 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.974201870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.1725147496
Short name T201
Test name
Test status
Simulation time 18749197 ps
CPU time 0.88 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725147496 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1725147496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.3572305230
Short name T119
Test name
Test status
Simulation time 454945352 ps
CPU time 3.21 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:21 PM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572305230 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3572305230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.362835319
Short name T206
Test name
Test status
Simulation time 1285354080 ps
CPU time 5.39 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:23 PM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362835319 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.362835319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.3033589929
Short name T205
Test name
Test status
Simulation time 138521419 ps
CPU time 1.37 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033589929 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.3033589929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.3296212118
Short name T211
Test name
Test status
Simulation time 75178586 ps
CPU time 1.07 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 209124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296212118
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.3296212118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.572481366
Short name T208
Test name
Test status
Simulation time 33329427 ps
CPU time 0.9 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572481366 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.572481366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.1995154676
Short name T203
Test name
Test status
Simulation time 54387028 ps
CPU time 0.9 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995154676 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1995154676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.2456525430
Short name T230
Test name
Test status
Simulation time 494469163 ps
CPU time 2.59 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:36 PM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456525430 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2456525430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.280585977
Short name T82
Test name
Test status
Simulation time 14749079 ps
CPU time 0.86 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280585977 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.280585977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.1115876953
Short name T604
Test name
Test status
Simulation time 7178756631 ps
CPU time 72.24 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:58:46 PM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115876953 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1115876953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.2898333944
Short name T79
Test name
Test status
Simulation time 1926630898 ps
CPU time 34.68 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:58:08 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898333944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.2898333944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.269494965
Short name T204
Test name
Test status
Simulation time 89998041 ps
CPU time 1.04 seconds
Started Aug 28 07:57:16 PM UTC 24
Finished Aug 28 07:57:19 PM UTC 24
Peak memory 210088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269494965 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.269494965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.2676893706
Short name T221
Test name
Test status
Simulation time 135067562 ps
CPU time 1.21 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676893706 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.2676893706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2491091679
Short name T100
Test name
Test status
Simulation time 21720932 ps
CPU time 0.95 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491091679 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.2491091679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.1039466360
Short name T173
Test name
Test status
Simulation time 47222467 ps
CPU time 0.81 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039466360 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1039466360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.2089605549
Short name T219
Test name
Test status
Simulation time 32401450 ps
CPU time 1.25 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089605549 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.2089605549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.2238134041
Short name T180
Test name
Test status
Simulation time 56390397 ps
CPU time 0.85 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238134041 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.2238134041
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.4164436982
Short name T326
Test name
Test status
Simulation time 2480604873 ps
CPU time 18.53 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:52 PM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164436982 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.4164436982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.2194505586
Short name T227
Test name
Test status
Simulation time 141367423 ps
CPU time 2.08 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194505586 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.2194505586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.3985345788
Short name T216
Test name
Test status
Simulation time 55408103 ps
CPU time 1.17 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985345788 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3985345788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1337381825
Short name T214
Test name
Test status
Simulation time 18644814 ps
CPU time 0.77 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337381825
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.1337381825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.372384928
Short name T215
Test name
Test status
Simulation time 57258059 ps
CPU time 1.03 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372384928 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.372384928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.2126406625
Short name T209
Test name
Test status
Simulation time 15594953 ps
CPU time 0.67 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126406625 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2126406625
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.127214739
Short name T158
Test name
Test status
Simulation time 97262175 ps
CPU time 1.19 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127214739 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.127214739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.3894871860
Short name T147
Test name
Test status
Simulation time 21771553 ps
CPU time 0.88 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 209628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894871860 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3894871860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.2671056710
Short name T377
Test name
Test status
Simulation time 2966954613 ps
CPU time 28.31 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:58:02 PM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671056710 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.2671056710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.4072429873
Short name T183
Test name
Test status
Simulation time 5111787902 ps
CPU time 69.73 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:58:44 PM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072429873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.4072429873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.3461456420
Short name T213
Test name
Test status
Simulation time 23641650 ps
CPU time 0.84 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:34 PM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461456420 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3461456420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.2163125521
Short name T228
Test name
Test status
Simulation time 115907201 ps
CPU time 1.19 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163125521 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.2163125521
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2012856542
Short name T220
Test name
Test status
Simulation time 36385162 ps
CPU time 0.86 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012856542 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.2012856542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.1970398079
Short name T174
Test name
Test status
Simulation time 12952970 ps
CPU time 0.83 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970398079 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1970398079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.2805489686
Short name T226
Test name
Test status
Simulation time 78548179 ps
CPU time 1.07 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805489686 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.2805489686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.3297169502
Short name T218
Test name
Test status
Simulation time 27247377 ps
CPU time 1.01 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297169502 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.3297169502
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.774272996
Short name T317
Test name
Test status
Simulation time 1756378366 ps
CPU time 16.23 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:50 PM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774272996 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.774272996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.3994258154
Short name T239
Test name
Test status
Simulation time 375434547 ps
CPU time 3.97 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:38 PM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3994258154 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.3994258154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.3816684264
Short name T225
Test name
Test status
Simulation time 28750371 ps
CPU time 1.12 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816684264 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.3816684264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1770262500
Short name T224
Test name
Test status
Simulation time 72034500 ps
CPU time 1.03 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770262500
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.1770262500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3075859304
Short name T222
Test name
Test status
Simulation time 31350489 ps
CPU time 0.99 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075859304
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.3075859304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.4264376504
Short name T217
Test name
Test status
Simulation time 35722353 ps
CPU time 0.83 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264376504 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.4264376504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.233076611
Short name T257
Test name
Test status
Simulation time 737274407 ps
CPU time 5.18 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:40 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233076611 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.233076611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.28549390
Short name T229
Test name
Test status
Simulation time 197699477 ps
CPU time 1.64 seconds
Started Aug 28 07:57:32 PM UTC 24
Finished Aug 28 07:57:36 PM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28549390 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.28549390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.4166070613
Short name T433
Test name
Test status
Simulation time 5343471141 ps
CPU time 36.14 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:58:11 PM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166070613 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.4166070613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.1789497796
Short name T54
Test name
Test status
Simulation time 13319259513 ps
CPU time 84.97 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:59:00 PM UTC 24
Peak memory 220292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789497796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1789497796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2006358618
Short name T223
Test name
Test status
Simulation time 68125851 ps
CPU time 1.14 seconds
Started Aug 28 07:57:33 PM UTC 24
Finished Aug 28 07:57:35 PM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006358618 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2006358618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/9.clkmgr_trans/latest
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