Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	197608	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

435286

1

T4

31

T5

7

T29

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	185654	1			T4	42		T5	6		T29	4
values[0x0]	212188	1			T4	16		T5	8		T29	1
values[0x1]	235052	1			T4	23		T5	5		T29	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	137898	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

494996

1

T4

40

T5

8

T29

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2405	1			T2	52		T25	2		T11	5
valid_sources[0x01]	2708	1			T1	3		T3	2		T11	2
valid_sources[0x02]	2266	1			T4	1		T10	4		T3	4
valid_sources[0x03]	2341	1			T10	2		T61	2		T21	4
valid_sources[0x04]	3123	1			T4	1		T3	2		T21	1
valid_sources[0x05]	2186	1			T1	4		T53	2		T20	1
valid_sources[0x06]	2227	1			T3	3		T68	5		T213	2
valid_sources[0x07]	2650	1			T3	2		T21	1		T22	2
valid_sources[0x08]	2224	1			T58	2		T61	2		T3	4
valid_sources[0x09]	2299	1			T61	1		T3	2		T11	1
valid_sources[0x0a]	1934	1			T10	1		T3	2		T11	5
valid_sources[0x0b]	2874	1			T1	8		T10	5		T65	1
valid_sources[0x0c]	2240	1			T3	4		T21	2		T52	1
valid_sources[0x0d]	2162	1			T60	1		T3	2		T21	3
valid_sources[0x0e]	2289	1			T3	1		T21	1		T204	3
valid_sources[0x0f]	2591	1			T58	13		T61	1		T155	4
valid_sources[0x10]	2660	1			T5	1		T29	1		T10	1
valid_sources[0x11]	2789	1			T72	2		T61	2		T28	2
valid_sources[0x12]	2496	1			T4	1		T11	5		T52	1
valid_sources[0x13]	2541	1			T4	1		T5	1		T60	1
valid_sources[0x14]	2715	1			T69	4		T61	1		T3	7
valid_sources[0x15]	2073	1			T10	1		T86	2		T3	7
valid_sources[0x16]	2190	1			T72	3		T61	1		T3	2
valid_sources[0x17]	2253	1			T3	1		T21	2		T11	2
valid_sources[0x18]	2704	1			T5	1		T53	8		T69	5
valid_sources[0x19]	2244	1			T61	1		T11	2		T52	2
valid_sources[0x1a]	2096	1			T10	3		T72	1		T20	1
valid_sources[0x1b]	2401	1			T22	3		T11	1		T40	9
valid_sources[0x1c]	2068	1			T64	2		T20	1		T22	1
valid_sources[0x1d]	2416	1			T9	6		T58	3		T11	2
valid_sources[0x1e]	2657	1			T1	7		T54	35		T10	1
valid_sources[0x1f]	2736	1			T5	1		T53	2		T60	1
valid_sources[0x20]	2704	1			T4	2		T35	2		T57	1
valid_sources[0x21]	2845	1			T57	1		T61	2		T64	3
valid_sources[0x22]	2293	1			T57	1		T21	1		T207	1
valid_sources[0x23]	2084	1			T10	3		T61	1		T3	2
valid_sources[0x24]	3316	1			T3	2		T21	2		T203	1
valid_sources[0x25]	2177	1			T4	2		T5	1		T3	2
valid_sources[0x26]	2198	1			T10	5		T65	3		T20	1
valid_sources[0x27]	2447	1			T10	3		T3	4		T21	1
valid_sources[0x28]	2272	1			T4	1		T60	1		T3	1
valid_sources[0x29]	2260	1			T61	2		T11	1		T40	1
valid_sources[0x2a]	2116	1			T72	1		T20	2		T203	1
valid_sources[0x2b]	2465	1			T4	1		T1	2		T10	1
valid_sources[0x2c]	2848	1			T5	1		T3	1		T20	2
valid_sources[0x2d]	2372	1			T85	1		T10	5		T3	3
valid_sources[0x2e]	2419	1			T4	2		T65	1		T21	2
valid_sources[0x2f]	1923	1			T5	1		T1	19		T10	1
valid_sources[0x30]	2862	1			T10	1		T3	4		T203	2
valid_sources[0x31]	1991	1			T1	2		T61	1		T65	4
valid_sources[0x32]	2029	1			T58	8		T10	1		T3	1
valid_sources[0x33]	2186	1			T10	2		T72	1		T61	1
valid_sources[0x34]	2214	1			T10	1		T61	1		T3	7
valid_sources[0x35]	3249	1			T4	1		T25	3		T11	2
valid_sources[0x36]	2007	1			T4	1		T3	3		T20	5
valid_sources[0x37]	2476	1			T4	1		T64	1		T52	2
valid_sources[0x38]	2046	1			T1	6		T3	3		T20	1
valid_sources[0x39]	2184	1			T4	2		T10	1		T61	1
valid_sources[0x3a]	2114	1			T30	1		T85	1		T10	4
valid_sources[0x3b]	2368	1			T9	3		T72	4		T155	5
valid_sources[0x3c]	2876	1			T4	1		T1	5		T10	4
valid_sources[0x3d]	2432	1			T10	1		T72	1		T23	1
valid_sources[0x3e]	2544	1			T3	2		T11	1		T40	1
valid_sources[0x3f]	1982	1			T10	3		T61	1		T3	8
valid_sources[0x40]	2347	1			T4	2		T33	61		T10	3
valid_sources[0x41]	2276	1			T4	1		T69	1		T21	1
valid_sources[0x42]	4583	1			T4	2		T60	2		T10	1
valid_sources[0x43]	2300	1			T1	13		T10	3		T3	2
valid_sources[0x44]	2292	1			T4	1		T60	3		T10	5
valid_sources[0x45]	3376	1			T30	8		T31	91		T1	1
valid_sources[0x46]	2400	1			T34	22		T35	1		T3	1
valid_sources[0x47]	2510	1			T10	5		T3	4		T21	1
valid_sources[0x48]	2335	1			T64	1		T3	2		T11	1
valid_sources[0x49]	2464	1			T3	5		T21	1		T11	2
valid_sources[0x4a]	2301	1			T10	4		T3	3		T22	1
valid_sources[0x4b]	2260	1			T57	1		T3	2		T28	4
valid_sources[0x4c]	2965	1			T4	1		T82	1		T72	2
valid_sources[0x4d]	1998	1			T61	1		T3	2		T11	4
valid_sources[0x4e]	2439	1			T3	2		T11	1		T52	1
valid_sources[0x4f]	2479	1			T10	2		T3	2		T21	1
valid_sources[0x50]	2747	1			T3	1		T11	1		T52	1
valid_sources[0x51]	2833	1			T3	3		T11	3		T204	1
valid_sources[0x52]	1871	1			T72	1		T25	2		T11	2
valid_sources[0x53]	2249	1			T9	2		T1	4		T3	3
valid_sources[0x54]	2119	1			T30	5		T10	1		T65	1
valid_sources[0x55]	2285	1			T10	2		T61	1		T155	2
valid_sources[0x56]	2186	1			T1	1		T53	6		T10	1
valid_sources[0x57]	1967	1			T5	3		T10	6		T61	1
valid_sources[0x58]	2025	1			T35	3		T60	7		T3	2
valid_sources[0x59]	2163	1			T4	1		T69	1		T10	5
valid_sources[0x5a]	4141	1			T60	2		T10	4		T65	2
valid_sources[0x5b]	3718	1			T30	3		T82	1		T73	1
valid_sources[0x5c]	2196	1			T10	2		T61	1		T3	3
valid_sources[0x5d]	2183	1			T85	1		T72	3		T21	8
valid_sources[0x5e]	2245	1			T84	13		T10	1		T21	4
valid_sources[0x5f]	2269	1			T9	10		T10	3		T3	1
valid_sources[0x60]	2668	1			T53	10		T61	2		T25	1
valid_sources[0x61]	2060	1			T1	7		T3	2		T21	2
valid_sources[0x62]	2819	1			T10	1		T3	1		T155	2
valid_sources[0x63]	2535	1			T85	1		T61	1		T3	1
valid_sources[0x64]	2748	1			T4	1		T69	7		T10	6
valid_sources[0x65]	2046	1			T1	3		T57	1		T85	2
valid_sources[0x66]	2004	1			T1	2		T61	1		T3	2
valid_sources[0x67]	2087	1			T65	3		T3	2		T11	1
valid_sources[0x68]	2308	1			T4	1		T82	1		T10	1
valid_sources[0x69]	2017	1			T29	2		T55	21		T3	3
valid_sources[0x6a]	2146	1			T4	2		T3	4		T203	2
valid_sources[0x6b]	2758	1			T61	2		T11	1		T40	5
valid_sources[0x6c]	2647	1			T21	2		T25	2		T52	1
valid_sources[0x6d]	2002	1			T5	1		T61	1		T3	2
valid_sources[0x6e]	2029	1			T60	2		T10	1		T11	6
valid_sources[0x6f]	2772	1			T61	1		T3	1		T11	1
valid_sources[0x70]	2445	1			T4	1		T1	1		T10	1
valid_sources[0x71]	2365	1			T30	10		T60	1		T72	1
valid_sources[0x72]	3201	1			T3	1		T20	1		T21	2
valid_sources[0x73]	2232	1			T29	1		T9	1		T10	1
valid_sources[0x74]	3345	1			T1	27		T10	4		T72	1
valid_sources[0x75]	2274	1			T4	1		T1	3		T69	1
valid_sources[0x76]	2185	1			T72	3		T3	1		T20	2
valid_sources[0x77]	1929	1			T4	1		T58	3		T60	2
valid_sources[0x78]	2408	1			T4	1		T10	1		T72	4
valid_sources[0x79]	1811	1			T72	1		T61	1		T22	1
valid_sources[0x7a]	2364	1			T61	1		T65	3		T20	1
valid_sources[0x7b]	2811	1			T1	3		T3	2		T20	1
valid_sources[0x7c]	2219	1			T3	5		T21	2		T22	1
valid_sources[0x7d]	2722	1			T60	1		T82	2		T10	2
valid_sources[0x7e]	2549	1			T4	1		T82	2		T86	3
valid_sources[0x7f]	1809	1			T29	1		T60	1		T3	3
valid_sources[0x80]	2711	1			T4	1		T1	1		T53	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

122133

1

T4

22

T5

3

T29

3

values[0x0]

all_enables

biggest_size

168551

1

T4

5

T5

2

T30

6

values[0x1]

all_enables

biggest_size

144602

1

T4

4

T5

2

T30

1