Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T30,T55,T85
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T30,T9
1	0	Covered	T6,T56,T70
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	178629536	7955	0	0
GateOpen_A	178629536	14405	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178629536	7955	0	0
T4	15995	4	0	0
T5	30445	0	0	0
T6	3530	8	0	0
T22	0	4	0	0
T25	0	25	0	0
T29	6404	0	0	0
T30	4130	30	0	0
T31	4912	0	0	0
T32	8587	0	0	0
T33	6860	0	0	0
T34	4110	0	0	0
T35	3826	0	0	0
T53	0	4	0	0
T55	0	27	0	0
T56	0	16	0	0
T70	0	1	0	0
T72	0	4	0	0
T85	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	178629536	14405	0	0
T1	0	4	0	0
T4	15995	4	0	0
T5	30445	4	0	0
T6	3530	12	0	0
T9	0	8	0	0
T29	6404	4	0	0
T30	4130	30	0	0
T31	4912	4	0	0
T32	8587	4	0	0
T33	6860	4	0	0
T34	4110	0	0	0
T35	3826	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T30,T55,T85
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T30,T9
1	0	Covered	T6,T56,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	19266794	1881	0	0
GateOpen_A	19266794	3490	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266794	1881	0	0
T4	1767	1	0	0
T5	3604	0	0	0
T6	376	2	0	0
T22	0	1	0	0
T25	0	8	0	0
T29	699	0	0	0
T30	448	6	0	0
T31	540	0	0	0
T32	946	0	0	0
T33	790	0	0	0
T34	463	0	0	0
T35	425	0	0	0
T53	0	1	0	0
T55	0	6	0	0
T56	0	4	0	0
T72	0	1	0	0
T85	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266794	3490	0	0
T1	0	1	0	0
T4	1767	1	0	0
T5	3604	1	0	0
T6	376	3	0	0
T9	0	2	0	0
T29	699	1	0	0
T30	448	6	0	0
T31	540	1	0	0
T32	946	1	0	0
T33	790	1	0	0
T34	463	0	0	0
T35	425	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T30,T55,T85
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T30,T9
1	0	Covered	T6,T56,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	38533980	2019	0	0
GateOpen_A	38533980	3628	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38533980	2019	0	0
T4	3533	1	0	0
T5	7208	0	0	0
T6	752	2	0	0
T22	0	1	0	0
T25	0	8	0	0
T29	1397	0	0	0
T30	896	7	0	0
T31	1079	0	0	0
T32	1891	0	0	0
T33	1579	0	0	0
T34	926	0	0	0
T35	852	0	0	0
T53	0	1	0	0
T55	0	8	0	0
T56	0	4	0	0
T72	0	1	0	0
T85	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38533980	3628	0	0
T1	0	1	0	0
T4	3533	1	0	0
T5	7208	1	0	0
T6	752	3	0	0
T9	0	2	0	0
T29	1397	1	0	0
T30	896	7	0	0
T31	1079	1	0	0
T32	1891	1	0	0
T33	1579	1	0	0
T34	926	0	0	0
T35	852	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T30,T55,T85
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T30,T9
1	0	Covered	T6,T56,T26
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	78933332	2036	0	0
GateOpen_A	78933332	3651	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78933332	2036	0	0
T4	7130	1	0	0
T5	13088	0	0	0
T6	1623	2	0	0
T22	0	1	0	0
T25	0	9	0	0
T29	2872	0	0	0
T30	1857	8	0	0
T31	2196	0	0	0
T32	3833	0	0	0
T33	2994	0	0	0
T34	1814	0	0	0
T35	1699	0	0	0
T53	0	1	0	0
T55	0	7	0	0
T56	0	4	0	0
T72	0	1	0	0
T85	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78933332	3651	0	0
T1	0	1	0	0
T4	7130	1	0	0
T5	13088	1	0	0
T6	1623	3	0	0
T9	0	2	0	0
T29	2872	1	0	0
T30	1857	8	0	0
T31	2196	1	0	0
T32	3833	1	0	0
T33	2994	1	0	0
T34	1814	0	0	0
T35	1699	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T30,T55,T85
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T30,T9
1	0	Covered	T6,T56,T70
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	41895430	2019	0	0
GateOpen_A	41895430	3636	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41895430	2019	0	0
T4	3565	1	0	0
T5	6545	0	0	0
T6	779	2	0	0
T22	0	1	0	0
T29	1436	0	0	0
T30	929	9	0	0
T31	1097	0	0	0
T32	1917	0	0	0
T33	1497	0	0	0
T34	907	0	0	0
T35	850	0	0	0
T53	0	1	0	0
T55	0	6	0	0
T56	0	4	0	0
T70	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41895430	3636	0	0
T1	0	1	0	0
T4	3565	1	0	0
T5	6545	1	0	0
T6	779	3	0	0
T9	0	2	0	0
T29	1436	1	0	0
T30	929	9	0	0
T31	1097	1	0	0
T32	1917	1	0	0
T33	1497	1	0	0
T34	907	0	0	0
T35	850	0	0	0