Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	192382315	35063	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192382315	35063	0	0
T3	531830	307	0	0
T11	0	508	0	0
T12	0	62	0	0
T13	0	118	0	0
T14	0	39	0	0
T15	0	80	0	0
T16	0	197	0	0
T17	0	422	0	0
T18	0	109	0	0
T19	0	180	0	0
T20	144090	0	0	0
T21	149395	0	0	0
T22	7865	0	0	0
T23	4775	0	0	0
T24	4285	0	0	0
T25	8995	0	0	0
T26	7175	0	0	0
T27	7565	0	0	0
T28	7840	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38476463	5133	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	5133	0	0
T3	106366	46	0	0
T11	0	74	0	0
T12	0	9	0	0
T13	0	15	0	0
T14	0	6	0	0
T15	0	13	0	0
T16	0	26	0	0
T17	0	54	0	0
T18	0	14	0	0
T19	0	28	0	0
T20	28818	0	0	0
T21	29879	0	0	0
T22	1573	0	0	0
T23	955	0	0	0
T24	857	0	0	0
T25	1799	0	0	0
T26	1435	0	0	0
T27	1513	0	0	0
T28	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38476463	5004	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	5004	0	0
T3	106366	45	0	0
T11	0	64	0	0
T12	0	9	0	0
T13	0	17	0	0
T14	0	6	0	0
T15	0	13	0	0
T16	0	24	0	0
T17	0	54	0	0
T18	0	14	0	0
T19	0	29	0	0
T20	28818	0	0	0
T21	29879	0	0	0
T22	1573	0	0	0
T23	955	0	0	0
T24	857	0	0	0
T25	1799	0	0	0
T26	1435	0	0	0
T27	1513	0	0	0
T28	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38476463	7028	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	7028	0	0
T3	106366	62	0	0
T11	0	99	0	0
T12	0	14	0	0
T13	0	24	0	0
T14	0	8	0	0
T15	0	17	0	0
T16	0	40	0	0
T17	0	88	0	0
T18	0	22	0	0
T19	0	35	0	0
T20	28818	0	0	0
T21	29879	0	0	0
T22	1573	0	0	0
T23	955	0	0	0
T24	857	0	0	0
T25	1799	0	0	0
T26	1435	0	0	0
T27	1513	0	0	0
T28	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38476463	7079	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	7079	0	0
T3	106366	62	0	0
T11	0	104	0	0
T12	0	12	0	0
T13	0	24	0	0
T14	0	8	0	0
T15	0	16	0	0
T16	0	39	0	0
T17	0	85	0	0
T18	0	23	0	0
T19	0	38	0	0
T20	28818	0	0	0
T21	29879	0	0	0
T22	1573	0	0	0
T23	955	0	0	0
T24	857	0	0	0
T25	1799	0	0	0
T26	1435	0	0	0
T27	1513	0	0	0
T28	1568	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38476463	10819	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	10819	0	0
T3	106366	92	0	0
T11	0	167	0	0
T12	0	18	0	0
T13	0	38	0	0
T14	0	11	0	0
T15	0	21	0	0
T16	0	68	0	0
T17	0	141	0	0
T18	0	36	0	0
T19	0	50	0	0
T20	28818	0	0	0
T21	29879	0	0	0
T22	1573	0	0	0
T23	955	0	0	0
T24	857	0	0	0
T25	1799	0	0	0
T26	1435	0	0	0
T27	1513	0	0	0
T28	1568	0	0	0