Unified Coverage Report :: Module

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	22400	22400	0	0
OutputsKnown_A	1580966565	1496621280	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	230858778	215176770	0	14400
gen_flops.gen_stable_chks.OutputDelay_A	504657071	476094564	0	16800
gen_flops.gen_stable_chks.OutputIfUnstable_A	504657071	124776	0	0
gen_no_flops.OutputDelay_A	845450716	805258883	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	22400	22400
T4	28	28
T5	28	28
T6	28	28
T29	28	28
T30	28	28
T31	28	28
T32	28	28
T33	28	28
T34	28	28
T35	28	28

OutputsKnown_A

Name	Attempts	Real Successes
Total	1580966565	1496621280
T4	102440	100176
T5	179583	177145
T6	44889	39477
T29	50416	47306
T30	50445	47384
T31	59075	57085
T32	61741	59848
T33	81565	77266
T34	49370	42529
T35	46208	42125

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	230858778	215176770	14400
T4	5346	5190	18
T5	5724	5616	18
T6	10512	9174	18
T29	6096	5646	18
T30	11598	10824	18
T31	13452	12942	18
T32	5742	5526	18
T33	18708	17592	18
T34	11334	9618	18
T35	10614	9582	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	504657071	476094564	16800
T4	38620	37571	21
T5	69527	68355	21
T6	11887	10305	21
T29	16868	15651	21
T30	13455	12557	21
T31	15827	15230	21
T32	21714	20928	21
T33	21701	20406	21
T34	13148	11157	21
T35	12312	11115	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	504657071	124776
T4	29708	12
T5	69527	68
T6	11887	35
T9	27442	0
T29	16868	16
T30	13455	72
T31	15827	89
T32	21714	28
T33	21701	203
T34	13148	122
T35	12312	51
T57	0	42
T58	0	129
T62	0	5
T82	0	20
T83	0	41
T84	0	35
T86	0	11

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	845450716	805258883
T4	58474	57376
T5	104332	103135
T6	22490	19959
T29	27452	25970
T30	25392	23964
T31	29796	28874
T32	34285	33355
T33	41156	39229
T34	24888	21715
T35	23282	21389

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	78932889	74489009	0	0
gen_flops.gen_stable_chks.OutputDelay_A	78932889	74482118	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	78932889	17289	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78932889	74489009
T4	7130	6940
T5	13087	12870
T6	1623	1406
T29	2872	2668
T30	1857	1736
T31	2195	2115
T32	3832	3697
T33	2993	2817
T34	1814	1542
T35	1698	1536

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	78932889	74482118	2400
T4	7130	6937	3
T5	13087	12867	3
T6	1623	1403	3
T29	2872	2665	3
T30	1857	1733	3
T31	2195	2112	3
T32	3832	3694	3
T33	2993	2814	3
T34	1814	1539	3
T35	1698	1533	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	78932889	17289
T5	13087	17
T6	1623	0
T9	8900	0
T29	2872	0
T30	1857	0
T31	2195	0
T32	3832	4
T33	2993	66
T34	1814	47
T35	1698	13
T57	0	17
T58	0	57
T82	0	6
T83	0	20
T84	0	24

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_no_flops.OutputDelay_A	38476463	35869859	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_no_flops.OutputDelay_A	38476463	35869859	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T33 T34  | T5 T33 T34  | T5 T33 T34  | T5 T33 T34 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T33 T34

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T33,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T33,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T33,T34

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T33,T34

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T34
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T33,T34
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_stable_chks.OutputDelay_A	38476463	35862795	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	38476463	10408	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	38476463	10408
T5	954	16
T6	1752	0
T9	9271	0
T29	1016	0
T30	1933	0
T31	2242	0
T32	957	0
T33	3118	32
T34	1889	18
T35	1769	8
T57	0	14
T58	0	41
T62	0	5
T82	0	7
T84	0	4
T86	0	11

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_stable_chks.OutputDelay_A	38476463	35862795	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	38476463	12109	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	38476463	12109
T5	954	15
T6	1752	0
T9	9271	0
T29	1016	0
T30	1933	0
T31	2242	0
T32	957	8
T33	3118	28
T34	1889	19
T35	1769	8
T57	0	11
T58	0	31
T82	0	7
T83	0	21
T84	0	7

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	84842092	0	0
gen_no_flops.OutputDelay_A	87192814	84842092	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	84842092
T4	7427	7358
T5	13633	13550
T6	1690	1564
T29	2991	2908
T30	1933	1864
T31	2287	2247
T32	3992	3923
T33	3118	3078
T34	1889	1748
T35	1769	1686

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	87192814	84842092
T4	7427	7358
T5	13633	13550
T6	1690	1564
T29	2991	2908
T30	1933	1864
T31	2287	2247
T32	3992	3923
T33	3118	3078
T34	1889	1748
T35	1769	1686

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	78932889	76712616	0	0
gen_no_flops.OutputDelay_A	78932889	76712616	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78932889	76712616
T4	7130	7064
T5	13087	13007
T6	1623	1502
T29	2872	2792
T30	1857	1791
T31	2195	2156
T32	3832	3766
T33	2993	2955
T34	1814	1679
T35	1698	1618

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	78932889	76712616
T4	7130	7064
T5	13087	13007
T6	1623	1502
T29	2872	2792
T30	1857	1791
T31	2195	2156
T32	3832	3766
T33	2993	2955
T34	1814	1679
T35	1698	1618

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38533562	38533562	0	0
gen_no_flops.OutputDelay_A	38533562	38533562	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38533562	38533562
T4	3532	3532
T5	7208	7208
T6	751	751
T29	1396	1396
T30	896	896
T31	1078	1078
T32	1890	1890
T33	1579	1579
T34	926	926
T35	851	851

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38533562	38533562
T4	3532	3532
T5	7208	7208
T6	751	751
T29	1396	1396
T30	896	896
T31	1078	1078
T32	1890	1890
T33	1579	1579
T34	926	926
T35	851	851

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	19266395	19266395	0	0
gen_no_flops.OutputDelay_A	19266395	19266395	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	19266395	19266395
T4	1766	1766
T5	3604	3604
T6	376	376
T29	698	698
T30	448	448
T31	539	539
T32	945	945
T33	789	789
T34	462	462
T35	425	425

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	19266395	19266395
T4	1766	1766
T5	3604	3604
T6	376	376
T29	698	698
T30	448	448
T31	539	539
T32	945	945
T33	789	789
T34	462	462
T35	425	425

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	41895022	40770548	0	0
gen_no_flops.OutputDelay_A	41895022	40770548	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	41895022	40770548
T4	3565	3532
T5	6544	6504
T6	778	718
T29	1435	1396
T30	928	895
T31	1097	1078
T32	1916	1883
T33	1497	1478
T34	907	840
T35	849	809

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	41895022	40770548
T4	3565	3532
T5	6544	6504
T6	778	718
T29	1435	1396
T30	928	895
T31	1097	1078
T32	1916	1883
T33	1497	1478
T34	907	840
T35	849	809

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	38476463	35862795	0	2400

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	38476463	35862795	0	2400

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	38476463	35862795	0	2400

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	38476463	35862795	0	2400

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	38476463	35862795	0	2400

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	38476463	35862795	0	2400

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	38476463	35862795	2400
T4	891	865	3
T5	954	936	3
T6	1752	1529	3
T29	1016	941	3
T30	1933	1804	3
T31	2242	2157	3
T32	957	921	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_no_flops.OutputDelay_A	38476463	35869859	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_no_flops.OutputDelay_A	38476463	35869859	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_no_flops.OutputDelay_A	38476463	35869859	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	38476463	35869859	0	0
gen_no_flops.OutputDelay_A	38476463	35869859	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	38476463	35869859
T4	891	868
T5	954	939
T6	1752	1532
T29	1016	944
T30	1933	1807
T31	2242	2160
T32	957	924
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_flops.gen_stable_chks.OutputDelay_A	87192814	82471714	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	87192814	21285	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	87192814	82471714	2400
T4	7427	7226	3
T5	13633	13404	3
T6	1690	1461	3
T29	2991	2776	3
T30	1933	1804	3
T31	2287	2201	3
T32	3992	3848	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	87192814	21285
T4	7427	3
T5	13633	3
T6	1690	12
T29	2991	5
T30	1933	17
T31	2287	28
T32	3992	5
T33	3118	23
T34	1889	10
T35	1769	5

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_no_flops.OutputDelay_A	87192814	82478629	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_flops.gen_stable_chks.OutputDelay_A	87192814	82471714	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	87192814	21308	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	87192814	82471714	2400
T4	7427	7226	3
T5	13633	13404	3
T6	1690	1461	3
T29	2991	2776	3
T30	1933	1804	3
T31	2287	2201	3
T32	3992	3848	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	87192814	21308
T4	7427	3
T5	13633	5
T6	1690	9
T29	2991	5
T30	1933	19
T31	2287	32
T32	3992	3
T33	3118	16
T34	1889	9
T35	1769	7

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_no_flops.OutputDelay_A	87192814	82478629	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_flops.gen_stable_chks.OutputDelay_A	87192814	82471714	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	87192814	21191	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	87192814	82471714	2400
T4	7427	7226	3
T5	13633	13404	3
T6	1690	1461	3
T29	2991	2776	3
T30	1933	1804	3
T31	2287	2201	3
T32	3992	3848	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	87192814	21191
T4	7427	3
T5	13633	7
T6	1690	9
T29	2991	3
T30	1933	19
T31	2287	20
T32	3992	5
T33	3118	17
T34	1889	12
T35	1769	5

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_no_flops.OutputDelay_A	87192814	82478629	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_flops.gen_stable_chks.OutputDelay_A	87192814	82471714	0	2400
gen_flops.gen_stable_chks.OutputIfUnstable_A	87192814	21186	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	87192814	82471714	2400
T4	7427	7226	3
T5	13633	13404	3
T6	1690	1461	3
T29	2991	2776	3
T30	1933	1804	3
T31	2287	2201	3
T32	3992	3848	3
T33	3118	2932	3
T34	1889	1603	3
T35	1769	1597	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	87192814	21186
T4	7427	3
T5	13633	5
T6	1690	5
T29	2991	3
T30	1933	17
T31	2287	9
T32	3992	3
T33	3118	21
T34	1889	7
T35	1769	5

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T30 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T30

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	800	800	0	0
OutputsKnown_A	87192814	82478629	0	0
gen_no_flops.OutputDelay_A	87192814	82478629	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	800	800
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	87192814	82478629
T4	7427	7229
T5	13633	13407
T6	1690	1464
T29	2991	2779
T30	1933	1807
T31	2287	2204
T32	3992	3851
T33	3118	2935
T34	1889	1606
T35	1769	1600

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl