Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T9,T69,T10

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	38476463	35789937	0	0
AllClkBypReqTrue_A	38476463	77625	0	0
IoClkBypReqFalse_A	38476463	35738640	0	2400
IoClkBypReqTrue_A	38476463	124328	0	0
LcClkBypAckFalse_A	38476463	35796935	0	0
LcClkBypAckTrue_A	38476463	70627	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	35789937	0	0
T4	891	867	0	0
T5	954	807	0	0
T6	1752	1531	0	0
T29	1016	943	0	0
T30	1933	1806	0	0
T31	2242	2159	0	0
T32	957	919	0	0
T33	3118	2889	0	0
T34	1889	1434	0	0
T35	1769	1503	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	77625	0	0
T5	954	131	0	0
T6	1752	0	0	0
T9	9271	0	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	4	0	0
T33	3118	45	0	0
T34	1889	171	0	0
T35	1769	96	0	0
T57	0	90	0	0
T58	0	54	0	0
T82	0	59	0	0
T83	0	43	0	0
T84	0	31	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	35738640	0	2400
T4	891	865	0	3
T5	954	794	0	3
T6	1752	1529	0	3
T29	1016	941	0	3
T30	1933	1804	0	3
T31	2242	2157	0	3
T32	957	921	0	3
T33	3118	2388	0	3
T34	1889	1358	0	3
T35	1769	1496	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	124328	0	0
T5	954	142	0	0
T6	1752	0	0	0
T9	9271	0	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	544	0	0
T34	1889	245	0	0
T35	1769	101	0	0
T57	0	156	0	0
T58	0	536	0	0
T62	0	65	0	0
T82	0	54	0	0
T84	0	29	0	0
T86	0	134	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	35796935	0	0
T4	891	867	0	0
T5	954	847	0	0
T6	1752	1531	0	0
T29	1016	943	0	0
T30	1933	1806	0	0
T31	2242	2159	0	0
T32	957	923	0	0
T33	3118	2729	0	0
T34	1889	1460	0	0
T35	1769	1561	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	70627	0	0
T5	954	91	0	0
T6	1752	0	0	0
T9	9271	0	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	205	0	0
T34	1889	145	0	0
T35	1769	38	0	0
T57	0	87	0	0
T58	0	283	0	0
T62	0	32	0	0
T82	0	39	0	0
T84	0	19	0	0
T86	0	79	0	0