Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	348772972	9157	0	0
TransStop_A	348772972	4789	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348772972	9157	0	0
T4	29712	4	0	0
T5	54532	0	0	0
T6	6764	0	0	0
T22	0	4	0	0
T28	0	2	0	0
T29	11964	2	0	0
T30	7736	0	0	0
T31	9148	22	0	0
T32	15968	0	0	0
T33	12476	0	0	0
T34	7560	0	0	0
T35	7080	0	0	0
T53	0	4	0	0
T54	0	8	0	0
T60	0	15	0	0
T61	0	27	0	0
T66	0	25	0	0
T72	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	348772972	4789	0	0
T4	29712	4	0	0
T5	54532	0	0	0
T6	6764	0	0	0
T22	0	4	0	0
T28	0	3	0	0
T29	11964	2	0	0
T30	7736	0	0	0
T31	9148	11	0	0
T32	15968	0	0	0
T33	12476	0	0	0
T34	7560	0	0	0
T35	7080	0	0	0
T53	0	4	0	0
T60	0	4	0	0
T61	0	12	0	0
T66	0	16	0	0
T72	0	4	0	0
T155	0	7	0	0
T156	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	87193243	2270	0	0
TransStop_A	87193243	1205	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	2270	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T29	2991	0	0	0
T30	1934	0	0	0
T31	2287	7	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T60	0	4	0	0
T61	0	7	0	0
T66	0	8	0	0
T72	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	1205	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T29	2991	0	0	0
T30	1934	0	0	0
T31	2287	4	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T60	0	1	0	0
T61	0	3	0	0
T66	0	5	0	0
T72	0	1	0	0
T155	0	3	0	0
T156	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	87193243	2323	0	0
TransStop_A	87193243	1204	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	2323	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T29	2991	1	0	0
T30	1934	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T60	0	4	0	0
T61	0	9	0	0
T66	0	5	0	0
T72	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	1204	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T29	2991	1	0	0
T30	1934	0	0	0
T31	2287	2	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T60	0	1	0	0
T61	0	5	0	0
T66	0	3	0	0
T72	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	87193243	2305	0	0
TransStop_A	87193243	1188	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	2305	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T29	2991	0	0	0
T30	1934	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T60	0	2	0	0
T61	0	4	0	0
T66	0	6	0	0
T72	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	1188	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T29	2991	0	0	0
T30	1934	0	0	0
T31	2287	2	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T66	0	3	0	0
T72	0	1	0	0
T155	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	87193243	2259	0	0
TransStop_A	87193243	1192	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	2259	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T29	2991	1	0	0
T30	1934	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T60	0	5	0	0
T61	0	7	0	0
T66	0	6	0	0
T72	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87193243	1192	0	0
T4	7428	1	0	0
T5	13633	0	0	0
T6	1691	0	0	0
T22	0	1	0	0
T28	0	1	0	0
T29	2991	1	0	0
T30	1934	0	0	0
T31	2287	3	0	0
T32	3992	0	0	0
T33	3119	0	0	0
T34	1890	0	0	0
T35	1770	0	0	0
T53	0	1	0	0
T60	0	1	0	0
T61	0	2	0	0
T66	0	5	0	0
T72	0	1	0	0