Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	39397092	452803	0	0
clk_enables_rd_A	39397092	6664	0	0
clk_hints_rd_A	39397092	6670	0	0
extclk_ctrl_rd_A	39397092	9685	0	0
extclk_ctrl_regwen_rd_A	39397092	5471	0	0
jitter_enable_rd_A	39397092	14889	0	0
jitter_regwen_rd_A	39397092	5721	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	452803	0	0
T15	102786	3185	0	0
T16	0	6190	0	0
T67	0	3369	0	0
T79	0	3731	0	0
T95	0	4659	0	0
T96	0	3419	0	0
T97	0	8959	0	0
T98	0	4043	0	0
T99	0	15212	0	0
T100	0	3835	0	0
T101	1651	0	0	0
T102	1420	0	0	0
T103	1358	0	0	0
T104	1358	0	0	0
T105	666	0	0	0
T106	1021	0	0	0
T107	1440	0	0	0
T108	123460	0	0	0
T109	1508	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	6664	0	0
T2	19365	0	0	0
T16	0	208	0	0
T61	2264	0	0	0
T62	1592	0	0	0
T63	2051	0	0	0
T64	1570	0	0	0
T65	1845	0	0	0
T66	2059	0	0	0
T70	1017	0	0	0
T72	1570	4	0	0
T74	0	17	0	0
T79	0	188	0	0
T86	1076	0	0	0
T96	0	110	0	0
T171	0	6	0	0
T172	0	2	0	0
T173	0	2	0	0
T174	0	3	0	0
T175	0	6	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	6670	0	0
T2	19365	0	0	0
T16	0	193	0	0
T61	2264	0	0	0
T62	1592	0	0	0
T63	2051	0	0	0
T64	1570	0	0	0
T65	1845	0	0	0
T66	2059	0	0	0
T70	1017	0	0	0
T72	1570	8	0	0
T74	0	15	0	0
T79	0	259	0	0
T86	1076	0	0	0
T96	0	105	0	0
T98	0	182	0	0
T171	0	10	0	0
T172	0	4	0	0
T176	0	4	0	0
T177	0	14	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	9685	0	0
T1	106533	0	0	0
T9	9271	7	0	0
T10	0	20	0	0
T33	3118	77	0	0
T34	1889	21	0	0
T35	1769	13	0	0
T53	991	0	0	0
T54	1250	0	0	0
T55	1680	0	0	0
T56	1311	0	0	0
T57	1130	0	0	0
T62	0	10	0	0
T74	0	32	0	0
T86	0	26	0	0
T110	0	152	0	0
T178	0	18	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	5471	0	0
T1	106533	0	0	0
T9	9271	9	0	0
T10	0	9	0	0
T16	0	148	0	0
T53	991	0	0	0
T54	1250	0	0	0
T55	1680	0	0	0
T56	1311	0	0	0
T57	1130	0	0	0
T58	2705	0	0	0
T59	964	0	0	0
T60	2112	0	0	0
T79	0	199	0	0
T96	0	72	0	0
T110	0	60	0	0
T179	0	48	0	0
T180	0	19	0	0
T181	0	8	0	0
T182	0	10	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	14889	0	0
T2	19365	0	0	0
T16	0	384	0	0
T61	2264	0	0	0
T62	1592	0	0	0
T63	2051	0	0	0
T64	1570	0	0	0
T65	1845	0	0	0
T66	2059	0	0	0
T70	1017	0	0	0
T72	1570	85	0	0
T74	0	309	0	0
T79	0	881	0	0
T86	1076	0	0	0
T96	0	276	0	0
T171	0	242	0	0
T172	0	131	0	0
T173	0	108	0	0
T174	0	58	0	0
T176	0	132	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39397092	5721	0	0
T16	226709	220	0	0
T79	0	218	0	0
T96	0	111	0	0
T98	0	156	0	0
T183	0	201	0	0
T184	0	259	0	0
T185	0	141	0	0
T186	0	157	0	0
T187	0	243	0	0
T188	0	73	0	0
T189	13307	0	0	0
T190	1164	0	0	0
T191	1411	0	0	0
T192	1308	0	0	0
T193	101359	0	0	0
T194	1020	0	0	0
T195	1256	0	0	0
T196	1167	0	0	0
T197	804	0	0	0