Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	115429389	420	0	0
StatusRise_A	115429389	420	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115429389	420	0	0
T1	319599	0	0	0
T6	5256	6	0	0
T9	27813	0	0	0
T26	0	13	0	0
T29	3048	0	0	0
T30	5799	0	0	0
T31	6726	0	0	0
T32	2871	0	0	0
T33	9354	0	0	0
T34	5667	0	0	0
T35	5307	0	0	0
T49	0	7	0	0
T56	0	11	0	0
T70	0	2	0	0
T105	0	2	0	0
T125	0	2	0	0
T194	0	7	0	0
T198	0	15	0	0
T199	0	10	0	0
T200	0	8	0	0
T201	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115429389	420	0	0
T1	319599	0	0	0
T6	5256	6	0	0
T9	27813	0	0	0
T26	0	13	0	0
T29	3048	0	0	0
T30	5799	0	0	0
T31	6726	0	0	0
T32	2871	0	0	0
T33	9354	0	0	0
T34	5667	0	0	0
T35	5307	0	0	0
T49	0	7	0	0
T56	0	11	0	0
T70	0	2	0	0
T105	0	2	0	0
T125	0	2	0	0
T194	0	7	0	0
T198	0	15	0	0
T199	0	10	0	0
T200	0	8	0	0
T201	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38476463	136	0	0
StatusRise_A	38476463	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	136	0	0
T1	106533	0	0	0
T6	1752	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	2	0	0
T56	0	3	0	0
T70	0	1	0	0
T105	0	1	0	0
T194	0	3	0	0
T198	0	6	0	0
T199	0	3	0	0
T200	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	136	0	0
T1	106533	0	0	0
T6	1752	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	2	0	0
T56	0	3	0	0
T70	0	1	0	0
T105	0	1	0	0
T194	0	3	0	0
T198	0	6	0	0
T199	0	3	0	0
T200	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38476463	140	0	0
StatusRise_A	38476463	140	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	140	0	0
T1	106533	0	0	0
T6	1752	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	140	0	0
T1	106533	0	0	0
T6	1752	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38476463	144	0	0
StatusRise_A	38476463	144	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	144	0	0
T1	106533	0	0	0
T6	1752	2	0	0
T9	9271	0	0	0
T26	0	5	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	1	0	0
T56	0	4	0	0
T70	0	1	0	0
T105	0	1	0	0
T125	0	1	0	0
T198	0	5	0	0
T199	0	3	0	0
T200	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38476463	144	0	0
T1	106533	0	0	0
T6	1752	2	0	0
T9	9271	0	0	0
T26	0	5	0	0
T29	1016	0	0	0
T30	1933	0	0	0
T31	2242	0	0	0
T32	957	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	1	0	0
T56	0	4	0	0
T70	0	1	0	0
T105	0	1	0	0
T125	0	1	0	0
T198	0	5	0	0
T199	0	3	0	0
T200	0	4	0	0