Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	918945410	32422	0	0
CgEnOn_A	918945410	23241	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	918945410	32422	0	0
T1	416845	0	0	0
T4	45701	7	0	0
T5	84975	3	0	0
T6	17948	21	0	0
T9	39251	0	0	0
T26	0	20	0	0
T29	32144	3	0	0
T30	20752	46	0	0
T31	24618	10	0	0
T32	43008	3	0	0
T33	34002	3	0	0
T34	20476	3	0	0
T35	19110	3	0	0
T49	0	20	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	23	0	0
T125	0	5	0	0
T194	0	20	0	0
T198	0	20	0	0
T199	0	20	0	0
T200	0	10	0	0
T201	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	918945410	23241	0	0
T1	416845	0	0	0
T4	45701	4	0	0
T5	84975	0	0	0
T6	17948	18	0	0
T9	39251	0	0	0
T22	0	3	0	0
T25	0	45	0	0
T26	0	20	0	0
T29	32144	0	0	0
T30	20752	43	0	0
T31	24618	7	0	0
T32	43008	0	0	0
T33	34002	0	0	0
T34	20476	0	0	0
T35	19110	0	0	0
T49	0	20	0	0
T53	0	4	0	0
T54	0	2	0	0
T55	0	23	0	0
T56	0	35	0	0
T60	0	4	0	0
T72	0	4	0	0
T85	0	11	0	0
T125	0	5	0	0
T194	0	20	0	0
T198	0	20	0	0
T199	0	20	0	0
T200	0	10	0	0
T201	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	38533562	157	0	0
CgEnOn_A	38533562	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38533562	157	0	0
T1	35396	0	0	0
T6	751	2	0	0
T9	2943	0	0	0
T26	0	4	0	0
T29	1396	0	0	0
T30	896	0	0	0
T31	1078	0	0	0
T32	1890	0	0	0
T33	1579	0	0	0
T34	926	0	0	0
T35	851	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38533562	157	0	0
T1	35396	0	0	0
T6	751	2	0	0
T9	2943	0	0	0
T26	0	4	0	0
T29	1396	0	0	0
T30	896	0	0	0
T31	1078	0	0	0
T32	1890	0	0	0
T33	1579	0	0	0
T34	926	0	0	0
T35	851	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19266395	157	0	0
CgEnOn_A	19266395	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	157	0	0
T1	17698	0	0	0
T6	376	2	0	0
T9	1472	0	0	0
T26	0	4	0	0
T29	698	0	0	0
T30	448	0	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	157	0	0
T1	17698	0	0	0
T6	376	2	0	0
T9	1472	0	0	0
T26	0	4	0	0
T29	698	0	0	0
T30	448	0	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19266395	157	0	0
CgEnOn_A	19266395	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	157	0	0
T1	17698	0	0	0
T6	376	2	0	0
T9	1472	0	0	0
T26	0	4	0	0
T29	698	0	0	0
T30	448	0	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	157	0	0
T1	17698	0	0	0
T6	376	2	0	0
T9	1472	0	0	0
T26	0	4	0	0
T29	698	0	0	0
T30	448	0	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19266395	157	0	0
CgEnOn_A	19266395	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	157	0	0
T1	17698	0	0	0
T6	376	2	0	0
T9	1472	0	0	0
T26	0	4	0	0
T29	698	0	0	0
T30	448	0	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	157	0	0
T1	17698	0	0	0
T6	376	2	0	0
T9	1472	0	0	0
T26	0	4	0	0
T29	698	0	0	0
T30	448	0	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78932889	157	0	0
CgEnOn_A	78932889	145	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78932889	157	0	0
T1	70871	0	0	0
T6	1623	2	0	0
T9	8900	0	0	0
T26	0	4	0	0
T29	2872	0	0	0
T30	1857	0	0	0
T31	2195	0	0	0
T32	3832	0	0	0
T33	2993	0	0	0
T34	1814	0	0	0
T35	1698	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78932889	145	0	0
T1	70871	0	0	0
T6	1623	2	0	0
T9	8900	0	0	0
T26	0	4	0	0
T29	2872	0	0	0
T30	1857	0	0	0
T31	2195	0	0	0
T32	3832	0	0	0
T33	2993	0	0	0
T34	1814	0	0	0
T35	1698	0	0	0
T49	0	4	0	0
T56	0	4	0	0
T125	0	1	0	0
T194	0	4	0	0
T198	0	4	0	0
T199	0	4	0	0
T200	0	2	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87192814	140	0	0
CgEnOn_A	87192814	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	140	0	0
T1	103824	0	0	0
T6	1690	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	0	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	2	0	0
T56	0	3	0	0
T70	0	1	0	0
T105	0	1	0	0
T194	0	3	0	0
T198	0	6	0	0
T199	0	3	0	0
T200	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	138	0	0
T1	103824	0	0	0
T6	1690	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	0	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	2	0	0
T56	0	3	0	0
T70	0	1	0	0
T105	0	1	0	0
T194	0	3	0	0
T198	0	6	0	0
T199	0	3	0	0
T200	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87192814	140	0	0
CgEnOn_A	87192814	138	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	140	0	0
T1	103824	0	0	0
T6	1690	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	0	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	2	0	0
T56	0	3	0	0
T70	0	1	0	0
T105	0	1	0	0
T194	0	3	0	0
T198	0	6	0	0
T199	0	3	0	0
T200	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	138	0	0
T1	103824	0	0	0
T6	1690	2	0	0
T9	9271	0	0	0
T26	0	4	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	0	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T49	0	2	0	0
T56	0	3	0	0
T70	0	1	0	0
T105	0	1	0	0
T194	0	3	0	0
T198	0	6	0	0
T199	0	3	0	0
T200	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	41895022	152	0	0
CgEnOn_A	41895022	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41895022	152	0	0
T1	49836	0	0	0
T6	778	2	0	0
T9	4450	0	0	0
T26	0	5	0	0
T29	1435	0	0	0
T30	928	0	0	0
T31	1097	0	0	0
T32	1916	0	0	0
T33	1497	0	0	0
T34	907	0	0	0
T35	849	0	0	0
T49	0	1	0	0
T56	0	4	0	0
T70	0	1	0	0
T105	0	1	0	0
T125	0	1	0	0
T198	0	5	0	0
T199	0	3	0	0
T200	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41895022	144	0	0
T1	49836	0	0	0
T6	778	2	0	0
T9	4450	0	0	0
T26	0	5	0	0
T29	1435	0	0	0
T30	928	0	0	0
T31	1097	0	0	0
T32	1916	0	0	0
T33	1497	0	0	0
T34	907	0	0	0
T35	849	0	0	0
T49	0	1	0	0
T56	0	4	0	0
T70	0	1	0	0
T105	0	1	0	0
T125	0	1	0	0
T198	0	5	0	0
T199	0	3	0	0
T200	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T56,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19266395	5351	0	0
CgEnOn_A	19266395	3071	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	5351	0	0
T4	1766	2	0	0
T5	3604	1	0	0
T6	376	3	0	0
T29	698	1	0	0
T30	448	16	0	0
T31	539	1	0	0
T32	945	1	0	0
T33	789	1	0	0
T34	462	1	0	0
T35	425	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19266395	3071	0	0
T4	1766	1	0	0
T5	3604	0	0	0
T6	376	2	0	0
T22	0	1	0	0
T25	0	15	0	0
T29	698	0	0	0
T30	448	15	0	0
T31	539	0	0	0
T32	945	0	0	0
T33	789	0	0	0
T34	462	0	0	0
T35	425	0	0	0
T53	0	1	0	0
T55	0	7	0	0
T56	0	4	0	0
T72	0	1	0	0
T85	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T56,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	38533562	5356	0	0
CgEnOn_A	38533562	3076	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38533562	5356	0	0
T4	3532	2	0	0
T5	7208	1	0	0
T6	751	3	0	0
T29	1396	1	0	0
T30	896	15	0	0
T31	1078	1	0	0
T32	1890	1	0	0
T33	1579	1	0	0
T34	926	1	0	0
T35	851	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38533562	3076	0	0
T4	3532	1	0	0
T5	7208	0	0	0
T6	751	2	0	0
T22	0	1	0	0
T25	0	15	0	0
T29	1396	0	0	0
T30	896	14	0	0
T31	1078	0	0	0
T32	1890	0	0	0
T33	1579	0	0	0
T34	926	0	0	0
T35	851	0	0	0
T53	0	1	0	0
T55	0	8	0	0
T56	0	4	0	0
T72	0	1	0	0
T85	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T56,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	78932889	5399	0	0
CgEnOn_A	78932889	3107	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78932889	5399	0	0
T4	7130	2	0	0
T5	13087	1	0	0
T6	1623	3	0	0
T29	2872	1	0	0
T30	1857	15	0	0
T31	2195	1	0	0
T32	3832	1	0	0
T33	2993	1	0	0
T34	1814	1	0	0
T35	1698	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78932889	3107	0	0
T4	7130	1	0	0
T5	13087	0	0	0
T6	1623	2	0	0
T22	0	1	0	0
T25	0	15	0	0
T29	2872	0	0	0
T30	1857	14	0	0
T31	2195	0	0	0
T32	3832	0	0	0
T33	2993	0	0	0
T34	1814	0	0	0
T35	1698	0	0	0
T53	0	1	0	0
T55	0	8	0	0
T56	0	4	0	0
T72	0	1	0	0
T85	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T56,T70
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	41895022	5382	0	0
CgEnOn_A	41895022	3085	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41895022	5382	0	0
T4	3565	2	0	0
T5	6544	1	0	0
T6	778	3	0	0
T29	1435	1	0	0
T30	928	16	0	0
T31	1097	1	0	0
T32	1916	1	0	0
T33	1497	1	0	0
T34	907	1	0	0
T35	849	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	41895022	3085	0	0
T4	3565	1	0	0
T5	6544	0	0	0
T6	778	2	0	0
T22	0	1	0	0
T29	1435	0	0	0
T30	928	15	0	0
T31	1097	0	0	0
T32	1916	0	0	0
T33	1497	0	0	0
T34	907	0	0	0
T35	849	0	0	0
T53	0	1	0	0
T55	0	8	0	0
T56	0	4	0	0
T70	0	1	0	0
T72	0	1	0	0
T85	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Covered	T4,T31,T53
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87192814	2410	0	0
CgEnOn_A	87192814	2408	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2410	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	7	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T60	0	4	0	0
T61	0	7	0	0
T70	0	1	0	0
T72	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2408	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	7	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T60	0	4	0	0
T61	0	7	0	0
T70	0	1	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87192814	2463	0	0
CgEnOn_A	87192814	2461	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2463	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	1	0	0
T30	1933	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T60	0	4	0	0
T70	0	1	0	0
T72	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2461	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	1	0	0
T30	1933	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	3	0	0
T60	0	4	0	0
T70	0	1	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Covered	T4,T31,T53
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87192814	2445	0	0
CgEnOn_A	87192814	2443	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2445	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T56	0	3	0	0
T60	0	2	0	0
T61	0	4	0	0
T70	0	1	0	0
T72	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2443	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	0	0	0
T30	1933	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	3	0	0
T56	0	3	0	0
T60	0	2	0	0
T61	0	4	0	0
T70	0	1	0	0
T72	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T56
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	87192814	2399	0	0
CgEnOn_A	87192814	2397	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2399	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	1	0	0
T30	1933	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	3	0	0
T60	0	5	0	0
T70	0	1	0	0
T72	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	87192814	2397	0	0
T4	7427	1	0	0
T5	13633	0	0	0
T6	1690	2	0	0
T29	2991	1	0	0
T30	1933	0	0	0
T31	2287	5	0	0
T32	3992	0	0	0
T33	3118	0	0	0
T34	1889	0	0	0
T35	1769	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	3	0	0
T60	0	5	0	0
T70	0	1	0	0
T72	0	1	0	0