Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Total test records in report: 1005

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.2417891146			Sep 01 06:23:31 AM UTC 24	Sep 01 06:23:53 AM UTC 24	14014963 ps
T1002	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2660332295			Sep 01 06:23:31 AM UTC 24	Sep 01 06:23:53 AM UTC 24	13765965 ps
T1003	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.4127370110			Sep 01 06:23:31 AM UTC 24	Sep 01 06:23:53 AM UTC 24	18807260 ps
T1004	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1969292159			Sep 01 06:23:31 AM UTC 24	Sep 01 06:23:53 AM UTC 24	14175303 ps
T1005	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.3492877965			Sep 01 06:23:31 AM UTC 24	Sep 01 06:23:53 AM UTC 24	20168425 ps

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.2884639450
Short name	T5
Test name
Test status
Simulation time	136354369 ps
CPU time	1.82 seconds
Started	Sep 01 06:19:21 AM UTC 24
Finished	Sep 01 06:19:24 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884639450 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2884639450
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.1773852872
Short name	T3
Test name
Test status
Simulation time	2127358806 ps
CPU time	21.83 seconds
Started	Sep 01 06:19:21 AM UTC 24
Finished	Sep 01 06:19:45 AM UTC 24
Peak memory	210864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773852872 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1773852872
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.595570234
Short name	T4
Test name
Test status
Simulation time	74295245 ps
CPU time	1.59 seconds
Started	Sep 01 06:19:21 AM UTC 24
Finished	Sep 01 06:19:24 AM UTC 24
Peak memory	209652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595570234 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.595570234
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.1378870955
Short name	T12
Test name
Test status
Simulation time	1676186102 ps
CPU time	14.38 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:54 AM UTC 24
Peak memory	210668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378870955 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.1378870955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.4009086257
Short name	T15
Test name
Test status
Simulation time	5710433620 ps
CPU time	39.34 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	220396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009086257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.4009086257
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.422419657
Short name	T110
Test name
Test status
Simulation time	966426088 ps
CPU time	10.01 seconds
Started	Sep 01 06:19:44 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	210608 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422419657 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.422419657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1046022598
Short name	T87
Test name
Test status
Simulation time	178008454 ps
CPU time	2.25 seconds
Started	Sep 01 06:22:50 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	212872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046022 598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.1046022598
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.2593669063
Short name	T20
Test name
Test status
Simulation time	355814612 ps
CPU time	5.64 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:45 AM UTC 24
Peak memory	242900 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593669063 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.2593669063
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.3617666434
Short name	T60
Test name
Test status
Simulation time	100605636 ps
CPU time	1.94 seconds
Started	Sep 01 06:19:33 AM UTC 24
Finished	Sep 01 06:19:36 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617666434 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.3617666434
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.151753750
Short name	T6
Test name
Test status
Simulation time	18077669 ps
CPU time	1.16 seconds
Started	Sep 01 06:19:25 AM UTC 24
Finished	Sep 01 06:19:27 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151753750 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.151753750
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2657436491
Short name	T33
Test name
Test status
Simulation time	31208914 ps
CPU time	1.48 seconds
Started	Sep 01 06:19:25 AM UTC 24
Finished	Sep 01 06:19:28 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657436491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.2657436491
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1675383133
Short name	T143
Test name
Test status
Simulation time	592702445 ps
CPU time	4.29 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:23:01 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675383133 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.1675383133
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.265233722
Short name	T74
Test name
Test status
Simulation time	3349789953 ps
CPU time	25.6 seconds
Started	Sep 01 06:19:32 AM UTC 24
Finished	Sep 01 06:19:59 AM UTC 24
Peak memory	210800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265233722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.265233722
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.807254211
Short name	T91
Test name
Test status
Simulation time	430949711 ps
CPU time	3.36 seconds
Started	Sep 01 06:22:48 AM UTC 24
Finished	Sep 01 06:22:56 AM UTC 24
Peak memory	212676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=807254211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_e rrors_with_csr_rw.807254211
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.2481771807
Short name	T847
Test name
Test status
Simulation time	73232827651 ps
CPU time	307.06 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:26:15 AM UTC 24
Peak memory	212972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481771807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2481771807
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.3317269583
Short name	T59
Test name
Test status
Simulation time	160801564 ps
CPU time	1.91 seconds
Started	Sep 01 06:19:32 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317269583 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.3317269583
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.983779140
Short name	T211
Test name
Test status
Simulation time	31443987 ps
CPU time	1.48 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983779140 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.983779140
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.4093423559
Short name	T122
Test name
Test status
Simulation time	30863398 ps
CPU time	1.48 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093423559 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.4093423559
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1060484318
Short name	T166
Test name
Test status
Simulation time	191287517 ps
CPU time	2.03 seconds
Started	Sep 01 06:23:11 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	222048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060484 318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.1060484318
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.3838270101
Short name	T7
Test name
Test status
Simulation time	911728191 ps
CPU time	8.11 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:34 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838270101 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3838270101
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3986218082
Short name	T115
Test name
Test status
Simulation time	29713854 ps
CPU time	1.58 seconds
Started	Sep 01 06:22:50 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	211884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986218082 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.3986218082
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1223445102
Short name	T151
Test name
Test status
Simulation time	99887916 ps
CPU time	2.19 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:14 AM UTC 24
Peak memory	212680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223445102 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.1223445102
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.4275483706
Short name	T464
Test name
Test status
Simulation time	7612023894 ps
CPU time	38.2 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:21:18 AM UTC 24
Peak memory	210928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275483706 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.4275483706
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2570427532
Short name	T960
Test name
Test status
Simulation time	79762085 ps
CPU time	1.45 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	211696 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570427 532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.2570427532
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.589905584
Short name	T34
Test name
Test status
Simulation time	18917592 ps
CPU time	1.25 seconds
Started	Sep 01 06:19:28 AM UTC 24
Finished	Sep 01 06:19:30 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589905584 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.589905584
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.4208102637
Short name	T96
Test name
Test status
Simulation time	1312932262 ps
CPU time	20.01 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	222120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4208102637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.4208102637
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2110164657
Short name	T88
Test name
Test status
Simulation time	107365425 ps
CPU time	2.07 seconds
Started	Sep 01 06:22:48 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110164 657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.2110164657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.709743713
Short name	T78
Test name
Test status
Simulation time	18791402789 ps
CPU time	143.06 seconds
Started	Sep 01 06:19:28 AM UTC 24
Finished	Sep 01 06:21:54 AM UTC 24
Peak memory	220296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709743713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.709743713
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.841115569
Short name	T148
Test name
Test status
Simulation time	60540416 ps
CPU time	1.48 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841115569 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.841115569
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.4250895175
Short name	T9
Test name
Test status
Simulation time	92738206 ps
CPU time	1.96 seconds
Started	Sep 01 06:19:28 AM UTC 24
Finished	Sep 01 06:19:32 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250895175 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.4250895175
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.444754695
Short name	T864
Test name
Test status
Simulation time	1114701231 ps
CPU time	6.17 seconds
Started	Sep 01 06:22:49 AM UTC 24
Finished	Sep 01 06:22:59 AM UTC 24
Peak memory	212316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444754695 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.444754695
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.4013500741
Short name	T850
Test name
Test status
Simulation time	17719552 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:49 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	212220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013500741 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.4013500741
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2031029118
Short name	T145
Test name
Test status
Simulation time	272242582 ps
CPU time	1.78 seconds
Started	Sep 01 06:22:50 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2031029118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 0.clkmgr_csr_mem_rw_with_rand_reset.2031029118
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.3955382301
Short name	T117
Test name
Test status
Simulation time	22663909 ps
CPU time	1.06 seconds
Started	Sep 01 06:22:49 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955382301 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.3955382301
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.2611352668
Short name	T851
Test name
Test status
Simulation time	50310142 ps
CPU time	0.8 seconds
Started	Sep 01 06:22:49 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	211364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611352668 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.2611352668
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3617484100
Short name	T114
Test name
Test status
Simulation time	92797426 ps
CPU time	1.25 seconds
Started	Sep 01 06:22:50 AM UTC 24
Finished	Sep 01 06:22:52 AM UTC 24
Peak memory	211876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617 484100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.3617484100
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.2985451771
Short name	T854
Test name
Test status
Simulation time	32581769 ps
CPU time	1.92 seconds
Started	Sep 01 06:22:48 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	212156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985451771 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.2985451771
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3984518403
Short name	T140
Test name
Test status
Simulation time	255276434 ps
CPU time	3.3 seconds
Started	Sep 01 06:22:49 AM UTC 24
Finished	Sep 01 06:22:56 AM UTC 24
Peak memory	212364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984518403 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.3984518403
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3382574040
Short name	T852
Test name
Test status
Simulation time	36279586 ps
CPU time	1.35 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382574040 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.3382574040
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.1025956680
Short name	T856
Test name
Test status
Simulation time	210444411 ps
CPU time	3.48 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:56 AM UTC 24
Peak memory	212672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025956680 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.1025956680
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1382748166
Short name	T849
Test name
Test status
Simulation time	15653010 ps
CPU time	1.08 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382748166 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.1382748166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3949355016
Short name	T855
Test name
Test status
Simulation time	23264828 ps
CPU time	1.25 seconds
Started	Sep 01 06:22:53 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3949355016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.clkmgr_csr_mem_rw_with_rand_reset.3949355016
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.842125285
Short name	T116
Test name
Test status
Simulation time	31355942 ps
CPU time	0.81 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842125285 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.842125285
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.2043788250
Short name	T848
Test name
Test status
Simulation time	22728840 ps
CPU time	0.73 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043788250 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.2043788250
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2601493972
Short name	T118
Test name
Test status
Simulation time	60800426 ps
CPU time	1.62 seconds
Started	Sep 01 06:22:53 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	211876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601 493972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.2601493972
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.969271362
Short name	T89
Test name
Test status
Simulation time	296835159 ps
CPU time	3.6 seconds
Started	Sep 01 06:22:50 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	221952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=969271362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_e rrors_with_csr_rw.969271362
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.363688287
Short name	T853
Test name
Test status
Simulation time	33600614 ps
CPU time	1.93 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	211944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363688287 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.363688287
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3601394
Short name	T139
Test name
Test status
Simulation time	209374085 ps
CPU time	2.14 seconds
Started	Sep 01 06:22:51 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	212420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601394 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.3601394
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.4139167444
Short name	T894
Test name
Test status
Simulation time	27380474 ps
CPU time	0.89 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4139167444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.clkmgr_csr_mem_rw_with_rand_reset.4139167444
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1510637567
Short name	T875
Test name
Test status
Simulation time	46370323 ps
CPU time	0.85 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:17 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510637567 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.1510637567
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.2855404697
Short name	T891
Test name
Test status
Simulation time	41132592 ps
CPU time	0.7 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:17 AM UTC 24
Peak memory	211432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855404697 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.2855404697
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2969112186
Short name	T895
Test name
Test status
Simulation time	110451063 ps
CPU time	1.18 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969 112186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.2969112186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1343921144
Short name	T169
Test name
Test status
Simulation time	430187438 ps
CPU time	2.49 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:09 AM UTC 24
Peak memory	229128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343921 144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.1343921144
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2670672837
Short name	T160
Test name
Test status
Simulation time	286598518 ps
CPU time	2.15 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:08 AM UTC 24
Peak memory	229284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2670672837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg _errors_with_csr_rw.2670672837
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.1299260253
Short name	T903
Test name
Test status
Simulation time	215306365 ps
CPU time	2.99 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:19 AM UTC 24
Peak memory	212476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299260253 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.1299260253
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2453395146
Short name	T153
Test name
Test status
Simulation time	135902625 ps
CPU time	2.59 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:19 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453395146 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.2453395146
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.807594665
Short name	T892
Test name
Test status
Simulation time	109165608 ps
CPU time	1.37 seconds
Started	Sep 01 06:23:08 AM UTC 24
Finished	Sep 01 06:23:17 AM UTC 24
Peak memory	211796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=807594665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 11.clkmgr_csr_mem_rw_with_rand_reset.807594665
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.2395923857
Short name	T933
Test name
Test status
Simulation time	44427343 ps
CPU time	0.85 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395923857 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.2395923857
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.1907503153
Short name	T930
Test name
Test status
Simulation time	14003976 ps
CPU time	0.67 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907503153 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.1907503153
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1039948095
Short name	T899
Test name
Test status
Simulation time	94120811 ps
CPU time	1.32 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	211932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039 948095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.1039948095
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1509391206
Short name	T901
Test name
Test status
Simulation time	144623951 ps
CPU time	1.96 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:19 AM UTC 24
Peak memory	228944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509391 206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.1509391206
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.559729881
Short name	T163
Test name
Test status
Simulation time	271430091 ps
CPU time	2.56 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:19 AM UTC 24
Peak memory	222244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=559729881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_ errors_with_csr_rw.559729881
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.460856437
Short name	T951
Test name
Test status
Simulation time	650212357 ps
CPU time	3.25 seconds
Started	Sep 01 06:23:06 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	212648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460856437 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.460856437
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3149947577
Short name	T906
Test name
Test status
Simulation time	93621961 ps
CPU time	0.97 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3149947577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.clkmgr_csr_mem_rw_with_rand_reset.3149947577
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.960522608
Short name	T904
Test name
Test status
Simulation time	24220526 ps
CPU time	0.67 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:22 AM UTC 24
Peak memory	211868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960522608 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.960522608
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.213068428
Short name	T887
Test name
Test status
Simulation time	121566415 ps
CPU time	0.8 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:12 AM UTC 24
Peak memory	211440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213068428 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.213068428
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2369613288
Short name	T914
Test name
Test status
Simulation time	84710339 ps
CPU time	1.28 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369 613288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.2369613288
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1598385138
Short name	T890
Test name
Test status
Simulation time	56703897 ps
CPU time	1.13 seconds
Started	Sep 01 06:23:08 AM UTC 24
Finished	Sep 01 06:23:17 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598385 138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.1598385138
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3035724804
Short name	T170
Test name
Test status
Simulation time	66997325 ps
CPU time	1.47 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:13 AM UTC 24
Peak memory	220756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3035724804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg _errors_with_csr_rw.3035724804
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.4022661634
Short name	T888
Test name
Test status
Simulation time	44000919 ps
CPU time	2.1 seconds
Started	Sep 01 06:23:09 AM UTC 24
Finished	Sep 01 06:23:13 AM UTC 24
Peak memory	212584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022661634 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.4022661634
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.628283851
Short name	T900
Test name
Test status
Simulation time	203074427 ps
CPU time	1.82 seconds
Started	Sep 01 06:23:16 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	211860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=628283851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.clkmgr_csr_mem_rw_with_rand_reset.628283851
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.434667212
Short name	T893
Test name
Test status
Simulation time	24799274 ps
CPU time	0.83 seconds
Started	Sep 01 06:23:16 AM UTC 24
Finished	Sep 01 06:23:17 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434667212 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.434667212
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.3696171602
Short name	T889
Test name
Test status
Simulation time	68580319 ps
CPU time	0.7 seconds
Started	Sep 01 06:23:14 AM UTC 24
Finished	Sep 01 06:23:17 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696171602 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.3696171602
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.2095139813
Short name	T897
Test name
Test status
Simulation time	129253971 ps
CPU time	1.36 seconds
Started	Sep 01 06:23:16 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	211984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095 139813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.2095139813
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3837292023
Short name	T928
Test name
Test status
Simulation time	108633329 ps
CPU time	2.59 seconds
Started	Sep 01 06:23:11 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	221968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3837292023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg _errors_with_csr_rw.3837292023
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.2026199100
Short name	T898
Test name
Test status
Simulation time	33572931 ps
CPU time	1.75 seconds
Started	Sep 01 06:23:14 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	209464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026199100 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.2026199100
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.959782583
Short name	T902
Test name
Test status
Simulation time	118635064 ps
CPU time	2.3 seconds
Started	Sep 01 06:23:14 AM UTC 24
Finished	Sep 01 06:23:19 AM UTC 24
Peak memory	210924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959782583 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.959782583
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.430187068
Short name	T919
Test name
Test status
Simulation time	121264578 ps
CPU time	1.9 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	220616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=430187068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.clkmgr_csr_mem_rw_with_rand_reset.430187068
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.3807033401
Short name	T916
Test name
Test status
Simulation time	38313528 ps
CPU time	0.9 seconds
Started	Sep 01 06:23:18 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807033401 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.3807033401
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.1193610922
Short name	T917
Test name
Test status
Simulation time	15406377 ps
CPU time	0.88 seconds
Started	Sep 01 06:23:18 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193610922 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.1193610922
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3458707150
Short name	T926
Test name
Test status
Simulation time	207669932 ps
CPU time	1.69 seconds
Started	Sep 01 06:23:18 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	211984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458 707150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.3458707150
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.559669270
Short name	T938
Test name
Test status
Simulation time	84145074 ps
CPU time	1.32 seconds
Started	Sep 01 06:23:16 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5596692 70 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.559669270
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1641241708
Short name	T923
Test name
Test status
Simulation time	126351415 ps
CPU time	1.64 seconds
Started	Sep 01 06:23:18 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	220756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1641241708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg _errors_with_csr_rw.1641241708
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.1649897940
Short name	T921
Test name
Test status
Simulation time	29785813 ps
CPU time	1.5 seconds
Started	Sep 01 06:23:18 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	211984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649897940 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.1649897940
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3040525552
Short name	T154
Test name
Test status
Simulation time	186580993 ps
CPU time	2.06 seconds
Started	Sep 01 06:23:18 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	212348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040525552 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.3040525552
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.321099089
Short name	T918
Test name
Test status
Simulation time	96082232 ps
CPU time	1.14 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=321099089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 15.clkmgr_csr_mem_rw_with_rand_reset.321099089
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.1963911657
Short name	T908
Test name
Test status
Simulation time	12043646 ps
CPU time	0.67 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211320 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963911657 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.1963911657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.3222514535
Short name	T909
Test name
Test status
Simulation time	25768624 ps
CPU time	0.62 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222514535 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.3222514535
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3651147555
Short name	T915
Test name
Test status
Simulation time	27585785 ps
CPU time	0.95 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651 147555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.3651147555
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1521861636
Short name	T168
Test name
Test status
Simulation time	84931329 ps
CPU time	1.5 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	227512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521861 636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.1521861636
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.837586524
Short name	T932
Test name
Test status
Simulation time	161062423 ps
CPU time	2.86 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	212684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=837586524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_ errors_with_csr_rw.837586524
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.1179682181
Short name	T929
Test name
Test status
Simulation time	194527046 ps
CPU time	2.42 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	212392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179682181 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.1179682181
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.903540269
Short name	T939
Test name
Test status
Simulation time	778163871 ps
CPU time	3.29 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903540269 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.903540269
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3057311743
Short name	T961
Test name
Test status
Simulation time	369014342 ps
CPU time	1.93 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	211768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3057311743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.clkmgr_csr_mem_rw_with_rand_reset.3057311743
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.910508442
Short name	T952
Test name
Test status
Simulation time	68102523 ps
CPU time	0.92 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910508442 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.910508442
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.585248774
Short name	T950
Test name
Test status
Simulation time	35133011 ps
CPU time	0.68 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585248774 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.585248774
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.847073349
Short name	T959
Test name
Test status
Simulation time	184707381 ps
CPU time	1.7 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	211948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8470 73349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.847073349
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.578485128
Short name	T920
Test name
Test status
Simulation time	159068812 ps
CPU time	1.42 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5784851 28 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.578485128
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.608927339
Short name	T925
Test name
Test status
Simulation time	97294674 ps
CPU time	1.75 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	220768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=608927339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_ errors_with_csr_rw.608927339
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.3572880916
Short name	T924
Test name
Test status
Simulation time	81285511 ps
CPU time	1.65 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	212008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572880916 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.3572880916
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1187312972
Short name	T147
Test name
Test status
Simulation time	440996424 ps
CPU time	2.92 seconds
Started	Sep 01 06:23:21 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187312972 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.1187312972
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.2557002690
Short name	T935
Test name
Test status
Simulation time	20334954 ps
CPU time	0.95 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2557002690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.clkmgr_csr_mem_rw_with_rand_reset.2557002690
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.839034939
Short name	T954
Test name
Test status
Simulation time	16877376 ps
CPU time	0.75 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839034939 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.839034939
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.1873379398
Short name	T953
Test name
Test status
Simulation time	22196066 ps
CPU time	0.67 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873379398 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.1873379398
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.1666831230
Short name	T957
Test name
Test status
Simulation time	70742692 ps
CPU time	1 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666 831230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.1666831230
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1595115480
Short name	T964
Test name
Test status
Simulation time	387247592 ps
CPU time	2.42 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:29 AM UTC 24
Peak memory	212684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595115 480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.1595115480
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.236822214
Short name	T965
Test name
Test status
Simulation time	110478512 ps
CPU time	2.46 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:29 AM UTC 24
Peak memory	222248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=236822214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_ errors_with_csr_rw.236822214
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.2833003845
Short name	T968
Test name
Test status
Simulation time	474426811 ps
CPU time	3.61 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:30 AM UTC 24
Peak memory	212712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833003845 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.2833003845
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.4204061256
Short name	T152
Test name
Test status
Simulation time	124704508 ps
CPU time	2.56 seconds
Started	Sep 01 06:23:24 AM UTC 24
Finished	Sep 01 06:23:29 AM UTC 24
Peak memory	212616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204061256 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.4204061256
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1373790616
Short name	T973
Test name
Test status
Simulation time	84175655 ps
CPU time	1.07 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1373790616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 18.clkmgr_csr_mem_rw_with_rand_reset.1373790616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.3351296862
Short name	T956
Test name
Test status
Simulation time	15323474 ps
CPU time	0.72 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	212340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351296862 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.3351296862
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.1666124160
Short name	T955
Test name
Test status
Simulation time	25993213 ps
CPU time	0.63 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666124160 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.1666124160
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.4278035077
Short name	T958
Test name
Test status
Simulation time	21481157 ps
CPU time	0.93 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278 035077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.4278035077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.632620348
Short name	T962
Test name
Test status
Simulation time	159041427 ps
CPU time	1.78 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	221260 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=632620348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_ errors_with_csr_rw.632620348
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.1238436196
Short name	T966
Test name
Test status
Simulation time	182464280 ps
CPU time	3.08 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:30 AM UTC 24
Peak memory	212532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238436196 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.1238436196
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2246564305
Short name	T150
Test name
Test status
Simulation time	123660082 ps
CPU time	2.28 seconds
Started	Sep 01 06:23:25 AM UTC 24
Finished	Sep 01 06:23:29 AM UTC 24
Peak memory	212356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246564305 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.2246564305
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1703329965
Short name	T979
Test name
Test status
Simulation time	23079633 ps
CPU time	0.91 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1703329965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 19.clkmgr_csr_mem_rw_with_rand_reset.1703329965
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.2614754318
Short name	T927
Test name
Test status
Simulation time	17061846 ps
CPU time	0.78 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614754318 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.2614754318
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.2927692990
Short name	T969
Test name
Test status
Simulation time	24282539 ps
CPU time	0.64 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927692990 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.2927692990
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.462452739
Short name	T976
Test name
Test status
Simulation time	28271601 ps
CPU time	0.85 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4624 52739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.462452739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3068537529
Short name	T981
Test name
Test status
Simulation time	148152178 ps
CPU time	1.72 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:33 AM UTC 24
Peak memory	220760 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068537 529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.3068537529
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1968258501
Short name	T980
Test name
Test status
Simulation time	171872465 ps
CPU time	1.75 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:33 AM UTC 24
Peak memory	220756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1968258501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg _errors_with_csr_rw.1968258501
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.3909545969
Short name	T982
Test name
Test status
Simulation time	970177598 ps
CPU time	5.57 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:36 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909545969 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.3909545969
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1118884786
Short name	T202
Test name
Test status
Simulation time	343045446 ps
CPU time	2.82 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:34 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118884786 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.1118884786
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3494159717
Short name	T120
Test name
Test status
Simulation time	77186230 ps
CPU time	1.14 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	211984 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3494159717 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.3494159717
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1070000363
Short name	T878
Test name
Test status
Simulation time	265281247 ps
CPU time	6.52 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	212564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070000363 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.1070000363
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1427378821
Short name	T858
Test name
Test status
Simulation time	20361775 ps
CPU time	0.99 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	212220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427378821 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.1427378821
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3662798313
Short name	T861
Test name
Test status
Simulation time	38829033 ps
CPU time	1.55 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3662798313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 2.clkmgr_csr_mem_rw_with_rand_reset.3662798313
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.1202644368
Short name	T119
Test name
Test status
Simulation time	17379534 ps
CPU time	0.92 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202644368 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.1202644368
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.1867148603
Short name	T857
Test name
Test status
Simulation time	11476963 ps
CPU time	0.68 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867148603 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.1867148603
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.25195925
Short name	T121
Test name
Test status
Simulation time	113806855 ps
CPU time	1.27 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	211816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519 5925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.25195925
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2260282966
Short name	T90
Test name
Test status
Simulation time	124398244 ps
CPU time	1.34 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260282 966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.2260282966
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.84539369
Short name	T92
Test name
Test status
Simulation time	123793783 ps
CPU time	1.88 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	229304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=84539369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_er rors_with_csr_rw.84539369
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.3227191087
Short name	T860
Test name
Test status
Simulation time	29348507 ps
CPU time	1.57 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	212004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227191087 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.3227191087
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3086312045
Short name	T142
Test name
Test status
Simulation time	379721705 ps
CPU time	2.93 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:59 AM UTC 24
Peak memory	212248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086312045 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.3086312045
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.1035313631
Short name	T970
Test name
Test status
Simulation time	21705328 ps
CPU time	0.66 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035313631 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.1035313631
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.4289236649
Short name	T975
Test name
Test status
Simulation time	90691092 ps
CPU time	0.75 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289236649 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.4289236649
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.3303912661
Short name	T972
Test name
Test status
Simulation time	12694858 ps
CPU time	0.73 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303912661 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.3303912661
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.2356708210
Short name	T977
Test name
Test status
Simulation time	26551621 ps
CPU time	0.73 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356708210 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.2356708210
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.2777658156
Short name	T974
Test name
Test status
Simulation time	22759063 ps
CPU time	0.63 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777658156 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.2777658156
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.1096058420
Short name	T971
Test name
Test status
Simulation time	13525383 ps
CPU time	0.62 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096058420 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.1096058420
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.335283364
Short name	T978
Test name
Test status
Simulation time	18398865 ps
CPU time	0.7 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:32 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335283364 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.335283364
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.2399541468
Short name	T984
Test name
Test status
Simulation time	15378121 ps
CPU time	0.61 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399541468 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.2399541468
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.3151023556
Short name	T986
Test name
Test status
Simulation time	37887721 ps
CPU time	0.66 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151023556 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.3151023556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.1677361053
Short name	T983
Test name
Test status
Simulation time	11374024 ps
CPU time	0.59 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677361053 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.1677361053
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1627663898
Short name	T944
Test name
Test status
Simulation time	51831825 ps
CPU time	1.61 seconds
Started	Sep 01 06:22:55 AM UTC 24
Finished	Sep 01 06:23:26 AM UTC 24
Peak memory	211940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627663898 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.1627663898
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.200975384
Short name	T865
Test name
Test status
Simulation time	457462002 ps
CPU time	4.37 seconds
Started	Sep 01 06:22:55 AM UTC 24
Finished	Sep 01 06:23:01 AM UTC 24
Peak memory	212544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200975384 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.200975384
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.4226627860
Short name	T862
Test name
Test status
Simulation time	305002010 ps
CPU time	1.48 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226627860 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.4226627860
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.359219419
Short name	T945
Test name
Test status
Simulation time	148288377 ps
CPU time	1.47 seconds
Started	Sep 01 06:22:55 AM UTC 24
Finished	Sep 01 06:23:26 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=359219419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.clkmgr_csr_mem_rw_with_rand_reset.359219419
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.1468761117
Short name	T931
Test name
Test status
Simulation time	17353106 ps
CPU time	0.93 seconds
Started	Sep 01 06:22:55 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468761117 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.1468761117
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.1346150377
Short name	T859
Test name
Test status
Simulation time	50384306 ps
CPU time	0.73 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346150377 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.1346150377
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1620242664
Short name	T937
Test name
Test status
Simulation time	57419037 ps
CPU time	1.06 seconds
Started	Sep 01 06:22:55 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620 242664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.1620242664
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.736198
Short name	T93
Test name
Test status
Simulation time	98496644 ps
CPU time	1.76 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	220756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.736198
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3870018152
Short name	T94
Test name
Test status
Simulation time	297848936 ps
CPU time	2.9 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:59 AM UTC 24
Peak memory	223952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3870018152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_ errors_with_csr_rw.3870018152
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.2650051852
Short name	T863
Test name
Test status
Simulation time	276457693 ps
CPU time	2.29 seconds
Started	Sep 01 06:22:54 AM UTC 24
Finished	Sep 01 06:22:59 AM UTC 24
Peak memory	212400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650051852 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.2650051852
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.2816536975
Short name	T985
Test name
Test status
Simulation time	15155305 ps
CPU time	0.61 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2816536975 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.2816536975
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.1161617671
Short name	T987
Test name
Test status
Simulation time	15428825 ps
CPU time	0.61 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161617671 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.1161617671
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.2082522889
Short name	T988
Test name
Test status
Simulation time	12738621 ps
CPU time	0.65 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082522889 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.2082522889
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.850732879
Short name	T989
Test name
Test status
Simulation time	13254054 ps
CPU time	0.64 seconds
Started	Sep 01 06:23:30 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	211164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850732879 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.850732879
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.4129930296
Short name	T990
Test name
Test status
Simulation time	23189188 ps
CPU time	0.63 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:52 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129930296 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.4129930296
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.2798654029
Short name	T1000
Test name
Test status
Simulation time	49862823 ps
CPU time	0.9 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211468 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798654029 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.2798654029
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.293904283
Short name	T993
Test name
Test status
Simulation time	12290935 ps
CPU time	0.62 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:52 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293904283 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.293904283
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.3579871163
Short name	T994
Test name
Test status
Simulation time	34020735 ps
CPU time	0.71 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:52 AM UTC 24
Peak memory	211104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579871163 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.3579871163
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.3380095306
Short name	T996
Test name
Test status
Simulation time	20525740 ps
CPU time	0.84 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380095306 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.3380095306
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.3698364852
Short name	T992
Test name
Test status
Simulation time	11685722 ps
CPU time	0.65 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:52 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698364852 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.3698364852
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1582256497
Short name	T948
Test name
Test status
Simulation time	316661822 ps
CPU time	1.72 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:26 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582256497 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.1582256497
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2292851403
Short name	T967
Test name
Test status
Simulation time	933351980 ps
CPU time	5.57 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:30 AM UTC 24
Peak memory	212572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292851403 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.2292851403
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.386599065
Short name	T936
Test name
Test status
Simulation time	18634357 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386599065 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.386599065
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.814491197
Short name	T940
Test name
Test status
Simulation time	36627196 ps
CPU time	0.88 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=814491197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.clkmgr_csr_mem_rw_with_rand_reset.814491197
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.877534541
Short name	T896
Test name
Test status
Simulation time	32073367 ps
CPU time	0.76 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:18 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877534541 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.877534541
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.1085295433
Short name	T934
Test name
Test status
Simulation time	14141349 ps
CPU time	0.68 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085295433 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.1085295433
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2429101390
Short name	T947
Test name
Test status
Simulation time	316218998 ps
CPU time	1.67 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:26 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429 101390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.2429101390
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.308977636
Short name	T941
Test name
Test status
Simulation time	103746961 ps
CPU time	1.33 seconds
Started	Sep 01 06:22:55 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089776 36 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.308977636
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.364351036
Short name	T164
Test name
Test status
Simulation time	254103552 ps
CPU time	2.67 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:20 AM UTC 24
Peak memory	222044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=364351036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_e rrors_with_csr_rw.364351036
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.988770192
Short name	T910
Test name
Test status
Simulation time	441034790 ps
CPU time	3.76 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:28 AM UTC 24
Peak memory	212736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988770192 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.988770192
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3358286376
Short name	T946
Test name
Test status
Simulation time	204122373 ps
CPU time	1.65 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:26 AM UTC 24
Peak memory	211944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358286376 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.3358286376
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.1687091873
Short name	T995
Test name
Test status
Simulation time	11705755 ps
CPU time	0.78 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687091873 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.1687091873
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.2824156998
Short name	T991
Test name
Test status
Simulation time	19504361 ps
CPU time	0.62 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:52 AM UTC 24
Peak memory	211544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824156998 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.2824156998
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.2417891146
Short name	T1001
Test name
Test status
Simulation time	14014963 ps
CPU time	0.81 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417891146 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.2417891146
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.474319699
Short name	T999
Test name
Test status
Simulation time	36858611 ps
CPU time	0.66 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474319699 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.474319699
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2660332295
Short name	T1002
Test name
Test status
Simulation time	13765965 ps
CPU time	0.74 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660332295 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.2660332295
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.4091952489
Short name	T997
Test name
Test status
Simulation time	30074536 ps
CPU time	0.65 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091952489 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.4091952489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.168611932
Short name	T998
Test name
Test status
Simulation time	29732063 ps
CPU time	0.66 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168611932 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.168611932
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.3492877965
Short name	T1005
Test name
Test status
Simulation time	20168425 ps
CPU time	0.81 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492877965 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.3492877965
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.4127370110
Short name	T1003
Test name
Test status
Simulation time	18807260 ps
CPU time	0.68 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4127370110 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.4127370110
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1969292159
Short name	T1004
Test name
Test status
Simulation time	14175303 ps
CPU time	0.63 seconds
Started	Sep 01 06:23:31 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969292159 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.1969292159
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3104870484
Short name	T882
Test name
Test status
Simulation time	251606510 ps
CPU time	1.84 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:04 AM UTC 24
Peak memory	212000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3104870484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.clkmgr_csr_mem_rw_with_rand_reset.3104870484
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.877299184
Short name	T877
Test name
Test status
Simulation time	74679654 ps
CPU time	0.91 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877299184 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.877299184
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.58954769
Short name	T874
Test name
Test status
Simulation time	18196874 ps
CPU time	0.79 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58954769 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.58954769
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1873309917
Short name	T881
Test name
Test status
Simulation time	60074652 ps
CPU time	1.44 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873 309917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.1873309917
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.263228177
Short name	T943
Test name
Test status
Simulation time	49004264 ps
CPU time	1.09 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	211740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632281 77 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.263228177
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1461025695
Short name	T949
Test name
Test status
Simulation time	109744781 ps
CPU time	2.41 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	212728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1461025695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_ errors_with_csr_rw.1461025695
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.4165177123
Short name	T963
Test name
Test status
Simulation time	953849175 ps
CPU time	3.92 seconds
Started	Sep 01 06:22:56 AM UTC 24
Finished	Sep 01 06:23:29 AM UTC 24
Peak memory	212588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165177123 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.4165177123
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1670327742
Short name	T144
Test name
Test status
Simulation time	129246930 ps
CPU time	1.78 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:04 AM UTC 24
Peak memory	211956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670327742 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.1670327742
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1246585266
Short name	T880
Test name
Test status
Simulation time	330892600 ps
CPU time	1.97 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1246585266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.clkmgr_csr_mem_rw_with_rand_reset.1246585266
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.3379651005
Short name	T868
Test name
Test status
Simulation time	53434132 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:02 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379651005 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.3379651005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.831652573
Short name	T867
Test name
Test status
Simulation time	11750002 ps
CPU time	0.64 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:02 AM UTC 24
Peak memory	211384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831652573 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.831652573
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4153474491
Short name	T872
Test name
Test status
Simulation time	36525603 ps
CPU time	1.32 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:02 AM UTC 24
Peak memory	211880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153 474491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.4153474491
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.3463049387
Short name	T157
Test name
Test status
Simulation time	60342156 ps
CPU time	1.19 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463049 387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.3463049387
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.269933425
Short name	T162
Test name
Test status
Simulation time	99501953 ps
CPU time	1.59 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=269933425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_e rrors_with_csr_rw.269933425
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.224180381
Short name	T884
Test name
Test status
Simulation time	91993031 ps
CPU time	2.21 seconds
Started	Sep 01 06:22:58 AM UTC 24
Finished	Sep 01 06:23:04 AM UTC 24
Peak memory	212452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224180381 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.224180381
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.415340983
Short name	T876
Test name
Test status
Simulation time	67159267 ps
CPU time	1.55 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415340983 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.415340983
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2826960728
Short name	T879
Test name
Test status
Simulation time	149944720 ps
CPU time	1.54 seconds
Started	Sep 01 06:23:01 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2826960728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.clkmgr_csr_mem_rw_with_rand_reset.2826960728
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.580110459
Short name	T871
Test name
Test status
Simulation time	29926947 ps
CPU time	0.8 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:02 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580110459 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.580110459
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.2305208739
Short name	T870
Test name
Test status
Simulation time	20315591 ps
CPU time	0.64 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:02 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305208739 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.2305208739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.4156989141
Short name	T873
Test name
Test status
Simulation time	29400283 ps
CPU time	0.89 seconds
Started	Sep 01 06:23:01 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156 989141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.4156989141
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.569953287
Short name	T159
Test name
Test status
Simulation time	138576433 ps
CPU time	1.96 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	210924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5699532 87 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.569953287
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1637015926
Short name	T158
Test name
Test status
Simulation time	125582952 ps
CPU time	1.77 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	221256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1637015926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_ errors_with_csr_rw.1637015926
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.3408145025
Short name	T883
Test name
Test status
Simulation time	165867986 ps
CPU time	2.58 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:04 AM UTC 24
Peak memory	212732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408145025 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.3408145025
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2665016481
Short name	T149
Test name
Test status
Simulation time	77211936 ps
CPU time	1.7 seconds
Started	Sep 01 06:22:59 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	211956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665016481 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.2665016481
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2417674451
Short name	T913
Test name
Test status
Simulation time	44884094 ps
CPU time	1.28 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2417674451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.clkmgr_csr_mem_rw_with_rand_reset.2417674451
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.2638777392
Short name	T869
Test name
Test status
Simulation time	38443441 ps
CPU time	0.76 seconds
Started	Sep 01 06:23:02 AM UTC 24
Finished	Sep 01 06:23:07 AM UTC 24
Peak memory	212172 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638777392 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.2638777392
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.1458133073
Short name	T866
Test name
Test status
Simulation time	12346717 ps
CPU time	0.63 seconds
Started	Sep 01 06:23:02 AM UTC 24
Finished	Sep 01 06:23:07 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458133073 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.1458133073
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.560178396
Short name	T912
Test name
Test status
Simulation time	113943485 ps
CPU time	1.28 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5601 78396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.560178396
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.3795838991
Short name	T161
Test name
Test status
Simulation time	101567018 ps
CPU time	1.69 seconds
Started	Sep 01 06:23:01 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	220756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795838 991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.3795838991
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.1109342052
Short name	T167
Test name
Test status
Simulation time	104225566 ps
CPU time	2.3 seconds
Started	Sep 01 06:23:01 AM UTC 24
Finished	Sep 01 06:23:04 AM UTC 24
Peak memory	229328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1109342052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_ errors_with_csr_rw.1109342052
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.2831682024
Short name	T886
Test name
Test status
Simulation time	126265897 ps
CPU time	2.06 seconds
Started	Sep 01 06:23:02 AM UTC 24
Finished	Sep 01 06:23:08 AM UTC 24
Peak memory	212688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831682024 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.2831682024
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.861977596
Short name	T141
Test name
Test status
Simulation time	78681304 ps
CPU time	1.59 seconds
Started	Sep 01 06:23:02 AM UTC 24
Finished	Sep 01 06:23:08 AM UTC 24
Peak memory	211956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861977596 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.861977596
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.2266870396
Short name	T885
Test name
Test status
Simulation time	102741755 ps
CPU time	1.58 seconds
Started	Sep 01 06:23:05 AM UTC 24
Finished	Sep 01 06:23:08 AM UTC 24
Peak memory	212000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2266870396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.clkmgr_csr_mem_rw_with_rand_reset.2266870396
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.1509745514
Short name	T907
Test name
Test status
Simulation time	26504459 ps
CPU time	0.8 seconds
Started	Sep 01 06:23:04 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509745514 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.1509745514
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.1120571668
Short name	T905
Test name
Test status
Simulation time	14657318 ps
CPU time	0.63 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:22 AM UTC 24
Peak memory	211488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120571668 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.1120571668
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.578025491
Short name	T911
Test name
Test status
Simulation time	36110142 ps
CPU time	0.98 seconds
Started	Sep 01 06:23:04 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5780 25491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.578025491
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3650128252
Short name	T165
Test name
Test status
Simulation time	99922976 ps
CPU time	1.1 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:13 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650128 252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.3650128252
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2044816207
Short name	T922
Test name
Test status
Simulation time	284329630 ps
CPU time	2.29 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	212700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2044816207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_ errors_with_csr_rw.2044816207
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.1852749162
Short name	T942
Test name
Test status
Simulation time	460133492 ps
CPU time	3.66 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:25 AM UTC 24
Peak memory	212520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852749162 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.1852749162
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.4220225559
Short name	T146
Test name
Test status
Simulation time	86158386 ps
CPU time	1.49 seconds
Started	Sep 01 06:23:03 AM UTC 24
Finished	Sep 01 06:23:23 AM UTC 24
Peak memory	211948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220225559 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.4220225559
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3566761665
Short name	T35
Test name
Test status
Simulation time	17717730 ps
CPU time	1.19 seconds
Started	Sep 01 06:19:28 AM UTC 24
Finished	Sep 01 06:19:31 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566761665 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.3566761665
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.715816104
Short name	T1
Test name
Test status
Simulation time	1098269900 ps
CPU time	10.17 seconds
Started	Sep 01 06:19:21 AM UTC 24
Finished	Sep 01 06:19:33 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715816104 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.715816104
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.2750115591
Short name	T29
Test name
Test status
Simulation time	29934915 ps
CPU time	1.22 seconds
Started	Sep 01 06:19:25 AM UTC 24
Finished	Sep 01 06:19:27 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750115591 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.2750115591
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.932610889
Short name	T32
Test name
Test status
Simulation time	39942032 ps
CPU time	1.29 seconds
Started	Sep 01 06:19:25 AM UTC 24
Finished	Sep 01 06:19:28 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932610889 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.932610889
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.949024322
Short name	T30
Test name
Test status
Simulation time	19363291 ps
CPU time	1.3 seconds
Started	Sep 01 06:19:25 AM UTC 24
Finished	Sep 01 06:19:27 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949024322 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.949024322
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.834452950
Short name	T69
Test name
Test status
Simulation time	997299734 ps
CPU time	6.76 seconds
Started	Sep 01 06:19:28 AM UTC 24
Finished	Sep 01 06:19:36 AM UTC 24
Peak memory	242604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834452950 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.834452950
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.746785230
Short name	T31
Test name
Test status
Simulation time	22892862 ps
CPU time	1.43 seconds
Started	Sep 01 06:19:25 AM UTC 24
Finished	Sep 01 06:19:27 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746785230 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.746785230
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.1513754836
Short name	T73
Test name
Test status
Simulation time	18168711 ps
CPU time	1.24 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:40 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513754836 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.1513754836
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2832522082
Short name	T82
Test name
Test status
Simulation time	13805500 ps
CPU time	1.15 seconds
Started	Sep 01 06:19:35 AM UTC 24
Finished	Sep 01 06:19:38 AM UTC 24
Peak memory	210580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832522082 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.2832522082
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.2797005602
Short name	T56
Test name
Test status
Simulation time	27334092 ps
CPU time	1.17 seconds
Started	Sep 01 06:19:33 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797005602 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2797005602
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.350434885
Short name	T84
Test name
Test status
Simulation time	47073619 ps
CPU time	1.36 seconds
Started	Sep 01 06:19:35 AM UTC 24
Finished	Sep 01 06:19:38 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350434885 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.350434885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.1797612966
Short name	T57
Test name
Test status
Simulation time	45272084 ps
CPU time	1.37 seconds
Started	Sep 01 06:19:32 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	209972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797612966 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1797612966
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.831674486
Short name	T11
Test name
Test status
Simulation time	1520564608 ps
CPU time	16.4 seconds
Started	Sep 01 06:19:32 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	210168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831674486 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.831674486
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.259591168
Short name	T52
Test name
Test status
Simulation time	1581280459 ps
CPU time	19.67 seconds
Started	Sep 01 06:19:33 AM UTC 24
Finished	Sep 01 06:19:54 AM UTC 24
Peak memory	210460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259591168 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.259591168
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3740801257
Short name	T83
Test name
Test status
Simulation time	15804266 ps
CPU time	1.22 seconds
Started	Sep 01 06:19:35 AM UTC 24
Finished	Sep 01 06:19:38 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740801257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.3740801257
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2499481255
Short name	T58
Test name
Test status
Simulation time	27080252 ps
CPU time	1.24 seconds
Started	Sep 01 06:19:33 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499481255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.2499481255
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.1264025281
Short name	T55
Test name
Test status
Simulation time	17701206 ps
CPU time	1.21 seconds
Started	Sep 01 06:19:33 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264025281 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1264025281
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.3703791386
Short name	T10
Test name
Test status
Simulation time	448661562 ps
CPU time	4.03 seconds
Started	Sep 01 06:19:35 AM UTC 24
Finished	Sep 01 06:19:41 AM UTC 24
Peak memory	210296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703791386 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3703791386
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.341808286
Short name	T53
Test name
Test status
Simulation time	39683853 ps
CPU time	1.06 seconds
Started	Sep 01 06:19:32 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341808286 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.341808286
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.2768996618
Short name	T54
Test name
Test status
Simulation time	48149179 ps
CPU time	1.09 seconds
Started	Sep 01 06:19:33 AM UTC 24
Finished	Sep 01 06:19:35 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768996618 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2768996618
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.142609404
Short name	T190
Test name
Test status
Simulation time	43140838 ps
CPU time	1.24 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:20:23 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142609404 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.142609404
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.262518560
Short name	T257
Test name
Test status
Simulation time	13238860 ps
CPU time	1.12 seconds
Started	Sep 01 06:20:18 AM UTC 24
Finished	Sep 01 06:20:21 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262518560 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.262518560
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.1353152553
Short name	T105
Test name
Test status
Simulation time	27827714 ps
CPU time	1.12 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353152553 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.1353152553
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.1277513471
Short name	T259
Test name
Test status
Simulation time	34410227 ps
CPU time	1.35 seconds
Started	Sep 01 06:20:18 AM UTC 24
Finished	Sep 01 06:20:21 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277513471 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.1277513471
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.231461893
Short name	T101
Test name
Test status
Simulation time	17227472 ps
CPU time	1.13 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231461893 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.231461893
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.3738118116
Short name	T18
Test name
Test status
Simulation time	921686947 ps
CPU time	11.35 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738118116 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3738118116
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.2135984241
Short name	T189
Test name
Test status
Simulation time	532354768 ps
CPU time	4.53 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:22 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135984241 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.2135984241
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.2886682716
Short name	T260
Test name
Test status
Simulation time	50224656 ps
CPU time	1.64 seconds
Started	Sep 01 06:20:18 AM UTC 24
Finished	Sep 01 06:20:21 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886682716 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.2886682716
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2139639160
Short name	T258
Test name
Test status
Simulation time	46067063 ps
CPU time	1.38 seconds
Started	Sep 01 06:20:18 AM UTC 24
Finished	Sep 01 06:20:21 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139639160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.2139639160
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1725956164
Short name	T109
Test name
Test status
Simulation time	15105524 ps
CPU time	1.12 seconds
Started	Sep 01 06:20:18 AM UTC 24
Finished	Sep 01 06:20:20 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725956164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.1725956164
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.2818522127
Short name	T103
Test name
Test status
Simulation time	13612485 ps
CPU time	1.04 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818522127 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.2818522127
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.504660244
Short name	T179
Test name
Test status
Simulation time	1127767653 ps
CPU time	6.26 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:20:27 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504660244 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.504660244
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.1274246385
Short name	T104
Test name
Test status
Simulation time	25668169 ps
CPU time	1.38 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274246385 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1274246385
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.666982033
Short name	T314
Test name
Test status
Simulation time	1907365946 ps
CPU time	18.75 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:20:40 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666982033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.666982033
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.2057902917
Short name	T842
Test name
Test status
Simulation time	51549086932 ps
CPU time	197.79 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:23:41 AM UTC 24
Peak memory	221228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057902917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.2057902917
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.892372120
Short name	T106
Test name
Test status
Simulation time	42589045 ps
CPU time	1.22 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892372120 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.892372120
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.3856167000
Short name	T266
Test name
Test status
Simulation time	200077796 ps
CPU time	1.44 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:27 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856167000 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.3856167000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2742586625
Short name	T195
Test name
Test status
Simulation time	30643565 ps
CPU time	1.23 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742586625 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.2742586625
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.3351465673
Short name	T194
Test name
Test status
Simulation time	42565328 ps
CPU time	1.19 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351465673 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3351465673
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.3276539731
Short name	T264
Test name
Test status
Simulation time	32934271 ps
CPU time	1.19 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:27 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276539731 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.3276539731
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.3245294539
Short name	T191
Test name
Test status
Simulation time	14869248 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:20:23 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245294539 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.3245294539
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.712029016
Short name	T42
Test name
Test status
Simulation time	2380968383 ps
CPU time	12.06 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:20:34 AM UTC 24
Peak memory	210712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712029016 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.712029016
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.2853122763
Short name	T287
Test name
Test status
Simulation time	1100982726 ps
CPU time	12.25 seconds
Started	Sep 01 06:20:21 AM UTC 24
Finished	Sep 01 06:20:34 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853122763 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.2853122763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.1791277820
Short name	T196
Test name
Test status
Simulation time	73000306 ps
CPU time	1.42 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791277820 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.1791277820
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.495167877
Short name	T261
Test name
Test status
Simulation time	175547128 ps
CPU time	1.63 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:25 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495167877 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.495167877
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2374163758
Short name	T197
Test name
Test status
Simulation time	89380260 ps
CPU time	1.45 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374163758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.2374163758
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.4013640274
Short name	T107
Test name
Test status
Simulation time	15030201 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013640274 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.4013640274
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.808548554
Short name	T192
Test name
Test status
Simulation time	52363115 ps
CPU time	1.46 seconds
Started	Sep 01 06:20:20 AM UTC 24
Finished	Sep 01 06:20:23 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808548554 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.808548554
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.1309788516
Short name	T268
Test name
Test status
Simulation time	231142649 ps
CPU time	2.92 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309788516 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.1309788516
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.1497939540
Short name	T768
Test name
Test status
Simulation time	37394622684 ps
CPU time	135.05 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	227252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497939540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.1497939540
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.1671865392
Short name	T130
Test name
Test status
Simulation time	27082034 ps
CPU time	1.16 seconds
Started	Sep 01 06:20:22 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671865392 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1671865392
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.2464247178
Short name	T274
Test name
Test status
Simulation time	110343858 ps
CPU time	1.6 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:30 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464247178 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.2464247178
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.1458880007
Short name	T275
Test name
Test status
Simulation time	182209536 ps
CPU time	2.07 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:30 AM UTC 24
Peak memory	210308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458880007 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.1458880007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.129395569
Short name	T201
Test name
Test status
Simulation time	14472940 ps
CPU time	1.13 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129395569 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.129395569
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.3667190622
Short name	T271
Test name
Test status
Simulation time	18623756 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667190622 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.3667190622
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.1562661701
Short name	T267
Test name
Test status
Simulation time	46892601 ps
CPU time	1.47 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:27 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562661701 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1562661701
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.2661365350
Short name	T38
Test name
Test status
Simulation time	441747088 ps
CPU time	5.49 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661365350 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.2661365350
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.4145505551
Short name	T297
Test name
Test status
Simulation time	1095106157 ps
CPU time	9.93 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:36 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145505551 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.4145505551
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.3399947080
Short name	T276
Test name
Test status
Simulation time	227785288 ps
CPU time	2.52 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:30 AM UTC 24
Peak memory	210492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399947080 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.3399947080
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.354151662
Short name	T273
Test name
Test status
Simulation time	191766228 ps
CPU time	1.82 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:30 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354151662 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.354151662
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3131556514
Short name	T272
Test name
Test status
Simulation time	41377355 ps
CPU time	1.31 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131556514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.3131556514
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.3949141987
Short name	T269
Test name
Test status
Simulation time	33012077 ps
CPU time	1.19 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949141987 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3949141987
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.2643515409
Short name	T293
Test name
Test status
Simulation time	715794297 ps
CPU time	6.41 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	210644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643515409 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2643515409
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.1424570114
Short name	T265
Test name
Test status
Simulation time	65164623 ps
CPU time	1.07 seconds
Started	Sep 01 06:20:25 AM UTC 24
Finished	Sep 01 06:20:27 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424570114 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1424570114
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.3824515483
Short name	T329
Test name
Test status
Simulation time	3260691325 ps
CPU time	15.59 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:44 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824515483 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.3824515483
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.3594820658
Short name	T270
Test name
Test status
Simulation time	20073529 ps
CPU time	1.22 seconds
Started	Sep 01 06:20:27 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	209808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594820658 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.3594820658
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.777720435
Short name	T288
Test name
Test status
Simulation time	16646651 ps
CPU time	1.03 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:34 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777720435 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.777720435
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2349251220
Short name	T133
Test name
Test status
Simulation time	57590282 ps
CPU time	1.47 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:33 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349251220 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2349251220
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.2663246406
Short name	T280
Test name
Test status
Simulation time	44289163 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663246406 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2663246406
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.3946203329
Short name	T284
Test name
Test status
Simulation time	46001972 ps
CPU time	1.36 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:33 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946203329 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.3946203329
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.487463382
Short name	T279
Test name
Test status
Simulation time	111429896 ps
CPU time	2.01 seconds
Started	Sep 01 06:20:29 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487463382 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.487463382
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.2392128535
Short name	T295
Test name
Test status
Simulation time	923812563 ps
CPU time	6.06 seconds
Started	Sep 01 06:20:29 AM UTC 24
Finished	Sep 01 06:20:36 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392128535 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.2392128535
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.2768667781
Short name	T339
Test name
Test status
Simulation time	2182983770 ps
CPU time	15.49 seconds
Started	Sep 01 06:20:29 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	211024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768667781 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.2768667781
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.364425965
Short name	T285
Test name
Test status
Simulation time	201749003 ps
CPU time	2.41 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:33 AM UTC 24
Peak memory	210296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364425965 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.364425965
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.925303924
Short name	T281
Test name
Test status
Simulation time	18106661 ps
CPU time	1.01 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925303924 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.925303924
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3402446429
Short name	T282
Test name
Test status
Simulation time	26669961 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402446429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.3402446429
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.1507852190
Short name	T277
Test name
Test status
Simulation time	18174311 ps
CPU time	1.24 seconds
Started	Sep 01 06:20:29 AM UTC 24
Finished	Sep 01 06:20:31 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507852190 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1507852190
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.3813996346
Short name	T303
Test name
Test status
Simulation time	1151522255 ps
CPU time	6.1 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:37 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813996346 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3813996346
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.1036455052
Short name	T176
Test name
Test status
Simulation time	74802580 ps
CPU time	1.65 seconds
Started	Sep 01 06:20:29 AM UTC 24
Finished	Sep 01 06:20:31 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036455052 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1036455052
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.2090507712
Short name	T528
Test name
Test status
Simulation time	8214333009 ps
CPU time	62.77 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:21:36 AM UTC 24
Peak memory	210800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090507712 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.2090507712
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.1140250083
Short name	T184
Test name
Test status
Simulation time	3827283806 ps
CPU time	58.06 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:21:30 AM UTC 24
Peak memory	220424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140250083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1140250083
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.3443968270
Short name	T283
Test name
Test status
Simulation time	57122368 ps
CPU time	1.4 seconds
Started	Sep 01 06:20:30 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443968270 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3443968270
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.453952373
Short name	T302
Test name
Test status
Simulation time	34865710 ps
CPU time	1.22 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:37 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453952373 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.453952373
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3975336483
Short name	T296
Test name
Test status
Simulation time	26669204 ps
CPU time	0.95 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:36 AM UTC 24
Peak memory	210068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975336483 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3975336483
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.2567499713
Short name	T292
Test name
Test status
Simulation time	15310030 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567499713 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2567499713
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.1934662380
Short name	T300
Test name
Test status
Simulation time	23297312 ps
CPU time	1.08 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:36 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934662380 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.1934662380
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.3552558000
Short name	T289
Test name
Test status
Simulation time	24983338 ps
CPU time	1.2 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:34 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552558000 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3552558000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.2574350654
Short name	T313
Test name
Test status
Simulation time	1417035249 ps
CPU time	6.74 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:40 AM UTC 24
Peak memory	210496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574350654 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2574350654
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.3865949008
Short name	T328
Test name
Test status
Simulation time	1700306446 ps
CPU time	10.22 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:44 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865949008 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.3865949008
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.3075911330
Short name	T301
Test name
Test status
Simulation time	40018839 ps
CPU time	1.6 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:37 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075911330 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.3075911330
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2855630783
Short name	T299
Test name
Test status
Simulation time	32085712 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:36 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855630783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.2855630783
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.2829696734
Short name	T298
Test name
Test status
Simulation time	15666129 ps
CPU time	1.12 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:36 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829696734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.2829696734
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.3817044352
Short name	T291
Test name
Test status
Simulation time	29718099 ps
CPU time	1.23 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817044352 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3817044352
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.1190821919
Short name	T312
Test name
Test status
Simulation time	996213571 ps
CPU time	4.35 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:40 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190821919 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1190821919
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.865030952
Short name	T290
Test name
Test status
Simulation time	66549414 ps
CPU time	1.35 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865030952 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.865030952
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.3319526316
Short name	T354
Test name
Test status
Simulation time	1486416574 ps
CPU time	13.71 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:49 AM UTC 24
Peak memory	210564 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319526316 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.3319526316
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.9868715
Short name	T496
Test name
Test status
Simulation time	7125558271 ps
CPU time	52.13 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:21:28 AM UTC 24
Peak memory	224624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9868715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.clkmgr_stress_all_with_rand_reset.9868715
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.2869462545
Short name	T294
Test name
Test status
Simulation time	32735867 ps
CPU time	1.46 seconds
Started	Sep 01 06:20:32 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869462545 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2869462545
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.705837890
Short name	T315
Test name
Test status
Simulation time	15598300 ps
CPU time	1.19 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:20:40 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705837890 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.705837890
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1914094074
Short name	T134
Test name
Test status
Simulation time	41948308 ps
CPU time	1.52 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:39 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914094074 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.1914094074
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.3981075572
Short name	T306
Test name
Test status
Simulation time	16096572 ps
CPU time	1.1 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981075572 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3981075572
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.315463964
Short name	T307
Test name
Test status
Simulation time	45584245 ps
CPU time	0.99 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315463964 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.315463964
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.819604532
Short name	T305
Test name
Test status
Simulation time	43105359 ps
CPU time	1.33 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819604532 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.819604532
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.4225709694
Short name	T359
Test name
Test status
Simulation time	1766018151 ps
CPU time	13.81 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:51 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225709694 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.4225709694
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.3065202004
Short name	T327
Test name
Test status
Simulation time	1883716289 ps
CPU time	6.55 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:44 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065202004 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.3065202004
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.329614023
Short name	T308
Test name
Test status
Simulation time	20238046 ps
CPU time	1.15 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329614023 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.329614023
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.812875049
Short name	T309
Test name
Test status
Simulation time	29653799 ps
CPU time	1.09 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812875049 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.812875049
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3885239713
Short name	T310
Test name
Test status
Simulation time	61983422 ps
CPU time	1.29 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885239713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.3885239713
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.3071048175
Short name	T304
Test name
Test status
Simulation time	18318599 ps
CPU time	1.12 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:38 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071048175 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3071048175
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.3557318205
Short name	T278
Test name
Test status
Simulation time	597350858 ps
CPU time	3.6 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	210708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557318205 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3557318205
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.774474338
Short name	T172
Test name
Test status
Simulation time	269728587 ps
CPU time	1.87 seconds
Started	Sep 01 06:20:34 AM UTC 24
Finished	Sep 01 06:20:37 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774474338 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.774474338
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.3607194531
Short name	T538
Test name
Test status
Simulation time	7295783262 ps
CPU time	59.39 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:21:39 AM UTC 24
Peak memory	227308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607194531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3607194531
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.3668360611
Short name	T311
Test name
Test status
Simulation time	78639604 ps
CPU time	1.66 seconds
Started	Sep 01 06:20:36 AM UTC 24
Finished	Sep 01 06:20:39 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668360611 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3668360611
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.965599049
Short name	T326
Test name
Test status
Simulation time	18664382 ps
CPU time	1.26 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:43 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965599049 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.965599049
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1543539131
Short name	T323
Test name
Test status
Simulation time	113235730 ps
CPU time	1.39 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:42 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543539131 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.1543539131
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.809940884
Short name	T318
Test name
Test status
Simulation time	31112393 ps
CPU time	1.21 seconds
Started	Sep 01 06:20:39 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809940884 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.809940884
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.1435238099
Short name	T321
Test name
Test status
Simulation time	15670461 ps
CPU time	0.98 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:42 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435238099 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.1435238099
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.1099607262
Short name	T286
Test name
Test status
Simulation time	86468053 ps
CPU time	1.6 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099607262 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1099607262
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.3403691311
Short name	T399
Test name
Test status
Simulation time	2234841614 ps
CPU time	20.63 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	210840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403691311 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.3403691311
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.3322586567
Short name	T358
Test name
Test status
Simulation time	1699902776 ps
CPU time	10.57 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:20:50 AM UTC 24
Peak memory	210652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322586567 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.3322586567
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.2799015166
Short name	T320
Test name
Test status
Simulation time	35018753 ps
CPU time	1.46 seconds
Started	Sep 01 06:20:39 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799015166 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.2799015166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.823740997
Short name	T325
Test name
Test status
Simulation time	83752803 ps
CPU time	1.57 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:43 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823740997 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.823740997
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3059922319
Short name	T322
Test name
Test status
Simulation time	69674656 ps
CPU time	1.53 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:42 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059922319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.3059922319
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.1062242018
Short name	T319
Test name
Test status
Simulation time	125524169 ps
CPU time	1.46 seconds
Started	Sep 01 06:20:39 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062242018 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1062242018
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.1945042991
Short name	T330
Test name
Test status
Simulation time	205245977 ps
CPU time	3.13 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:44 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945042991 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1945042991
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.2216187059
Short name	T316
Test name
Test status
Simulation time	73910031 ps
CPU time	1.49 seconds
Started	Sep 01 06:20:38 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216187059 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2216187059
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.2959396795
Short name	T340
Test name
Test status
Simulation time	678997284 ps
CPU time	4.02 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959396795 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.2959396795
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.3271847624
Short name	T539
Test name
Test status
Simulation time	2734713980 ps
CPU time	57.79 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:21:40 AM UTC 24
Peak memory	220516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271847624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3271847624
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.1749096120
Short name	T317
Test name
Test status
Simulation time	35362384 ps
CPU time	1.08 seconds
Started	Sep 01 06:20:39 AM UTC 24
Finished	Sep 01 06:20:41 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749096120 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1749096120
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.511581002
Short name	T343
Test name
Test status
Simulation time	16126404 ps
CPU time	1.2 seconds
Started	Sep 01 06:20:44 AM UTC 24
Finished	Sep 01 06:20:46 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511581002 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.511581002
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.3411136451
Short name	T337
Test name
Test status
Simulation time	65298321 ps
CPU time	1.41 seconds
Started	Sep 01 06:20:43 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411136451 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.3411136451
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.1506297377
Short name	T333
Test name
Test status
Simulation time	50323568 ps
CPU time	1.32 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	208884 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506297377 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1506297377
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.137488830
Short name	T335
Test name
Test status
Simulation time	13144084 ps
CPU time	1.01 seconds
Started	Sep 01 06:20:43 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137488830 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.137488830
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.3649259614
Short name	T331
Test name
Test status
Simulation time	19647868 ps
CPU time	1.3 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:44 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649259614 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3649259614
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.3030710005
Short name	T370
Test name
Test status
Simulation time	1729623245 ps
CPU time	9.88 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:53 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030710005 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3030710005
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.1177493477
Short name	T406
Test name
Test status
Simulation time	2060315404 ps
CPU time	18.65 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:21:02 AM UTC 24
Peak memory	210704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177493477 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.1177493477
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.965756171
Short name	T338
Test name
Test status
Simulation time	37556611 ps
CPU time	1.68 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965756171 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.965756171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.3672742970
Short name	T334
Test name
Test status
Simulation time	12783816 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:43 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672742970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.3672742970
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.932481441
Short name	T341
Test name
Test status
Simulation time	121719602 ps
CPU time	1.91 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932481441 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.932481441
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.736816448
Short name	T332
Test name
Test status
Simulation time	32072305 ps
CPU time	1.25 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210048 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736816448 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.736816448
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.1924941458
Short name	T180
Test name
Test status
Simulation time	404910720 ps
CPU time	3.75 seconds
Started	Sep 01 06:20:43 AM UTC 24
Finished	Sep 01 06:20:47 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924941458 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1924941458
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.4144943778
Short name	T324
Test name
Test status
Simulation time	62078207 ps
CPU time	1.15 seconds
Started	Sep 01 06:20:40 AM UTC 24
Finished	Sep 01 06:20:43 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144943778 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.4144943778
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.3832713551
Short name	T177
Test name
Test status
Simulation time	6917394993 ps
CPU time	34.07 seconds
Started	Sep 01 06:20:44 AM UTC 24
Finished	Sep 01 06:21:19 AM UTC 24
Peak memory	211024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832713551 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.3832713551
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.3987536162
Short name	T98
Test name
Test status
Simulation time	1412650506 ps
CPU time	21.94 seconds
Started	Sep 01 06:20:44 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	222408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987536162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.3987536162
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.4281660840
Short name	T336
Test name
Test status
Simulation time	37321432 ps
CPU time	1.64 seconds
Started	Sep 01 06:20:42 AM UTC 24
Finished	Sep 01 06:20:45 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281660840 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.4281660840
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.2435845475
Short name	T355
Test name
Test status
Simulation time	33395432 ps
CPU time	1.23 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:49 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435845475 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.2435845475
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.963014833
Short name	T349
Test name
Test status
Simulation time	47675118 ps
CPU time	1.19 seconds
Started	Sep 01 06:20:46 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963014833 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.963014833
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.3926562831
Short name	T345
Test name
Test status
Simulation time	38871645 ps
CPU time	0.99 seconds
Started	Sep 01 06:20:45 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	209124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926562831 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3926562831
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.3731114815
Short name	T351
Test name
Test status
Simulation time	95827937 ps
CPU time	1.64 seconds
Started	Sep 01 06:20:46 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731114815 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.3731114815
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.2414049719
Short name	T344
Test name
Test status
Simulation time	23435960 ps
CPU time	1.02 seconds
Started	Sep 01 06:20:44 AM UTC 24
Finished	Sep 01 06:20:46 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414049719 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2414049719
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.420029982
Short name	T391
Test name
Test status
Simulation time	1885545883 ps
CPU time	12.56 seconds
Started	Sep 01 06:20:44 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420029982 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.420029982
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.752879355
Short name	T353
Test name
Test status
Simulation time	134156908 ps
CPU time	2.5 seconds
Started	Sep 01 06:20:45 AM UTC 24
Finished	Sep 01 06:20:49 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752879355 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.752879355
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.412060186
Short name	T350
Test name
Test status
Simulation time	93643406 ps
CPU time	1.78 seconds
Started	Sep 01 06:20:45 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412060186 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.412060186
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3285321076
Short name	T347
Test name
Test status
Simulation time	26007299 ps
CPU time	1.22 seconds
Started	Sep 01 06:20:46 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285321076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.3285321076
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.4047794857
Short name	T348
Test name
Test status
Simulation time	59541374 ps
CPU time	1.35 seconds
Started	Sep 01 06:20:45 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047794857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.4047794857
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.2858337836
Short name	T346
Test name
Test status
Simulation time	28529832 ps
CPU time	1.21 seconds
Started	Sep 01 06:20:45 AM UTC 24
Finished	Sep 01 06:20:48 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858337836 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2858337836
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.2621414555
Short name	T360
Test name
Test status
Simulation time	660670378 ps
CPU time	3.83 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621414555 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2621414555
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.3916319935
Short name	T173
Test name
Test status
Simulation time	23396788 ps
CPU time	1.34 seconds
Started	Sep 01 06:20:44 AM UTC 24
Finished	Sep 01 06:20:46 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916319935 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3916319935
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.844028132
Short name	T77
Test name
Test status
Simulation time	7396670661 ps
CPU time	64.14 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844028132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.844028132
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.3625316513
Short name	T628
Test name
Test status
Simulation time	8986799846 ps
CPU time	82.22 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:22:11 AM UTC 24
Peak memory	227536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625316513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3625316513
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.3120621115
Short name	T352
Test name
Test status
Simulation time	147432484 ps
CPU time	2.14 seconds
Started	Sep 01 06:20:45 AM UTC 24
Finished	Sep 01 06:20:49 AM UTC 24
Peak memory	210540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120621115 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3120621115
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.2674367016
Short name	T372
Test name
Test status
Simulation time	17917639 ps
CPU time	1.25 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:20:54 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674367016 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.2674367016
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.957685845
Short name	T368
Test name
Test status
Simulation time	96117444 ps
CPU time	1.49 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:53 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957685845 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.957685845
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.2288162178
Short name	T362
Test name
Test status
Simulation time	50649814 ps
CPU time	1.32 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288162178 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.2288162178
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.477337119
Short name	T364
Test name
Test status
Simulation time	34119100 ps
CPU time	0.97 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477337119 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.477337119
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.2274402310
Short name	T357
Test name
Test status
Simulation time	74848465 ps
CPU time	1.62 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:50 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274402310 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2274402310
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.303740043
Short name	T369
Test name
Test status
Simulation time	568628290 ps
CPU time	4.65 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:53 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303740043 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.303740043
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.4112450937
Short name	T363
Test name
Test status
Simulation time	756664493 ps
CPU time	3.68 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112450937 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.4112450937
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.2136024147
Short name	T367
Test name
Test status
Simulation time	88509397 ps
CPU time	1.79 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136024147 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.2136024147
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.1022326566
Short name	T366
Test name
Test status
Simulation time	23735977 ps
CPU time	1.25 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022326566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.1022326566
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2391787841
Short name	T365
Test name
Test status
Simulation time	29728906 ps
CPU time	1.33 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391787841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.2391787841
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.3817087774
Short name	T356
Test name
Test status
Simulation time	33500619 ps
CPU time	1.25 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:50 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817087774 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3817087774
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.4177658279
Short name	T181
Test name
Test status
Simulation time	531348662 ps
CPU time	3.13 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177658279 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.4177658279
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.1359556009
Short name	T174
Test name
Test status
Simulation time	37611940 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:47 AM UTC 24
Finished	Sep 01 06:20:49 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359556009 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1359556009
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.2774159256
Short name	T552
Test name
Test status
Simulation time	9519848747 ps
CPU time	49.56 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774159256 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.2774159256
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.4049750673
Short name	T532
Test name
Test status
Simulation time	3382460806 ps
CPU time	44.79 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:21:38 AM UTC 24
Peak memory	220332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049750673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.4049750673
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.824918388
Short name	T361
Test name
Test status
Simulation time	40927179 ps
CPU time	1.26 seconds
Started	Sep 01 06:20:49 AM UTC 24
Finished	Sep 01 06:20:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824918388 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.824918388
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.2196009887
Short name	T23
Test name
Test status
Simulation time	43454337 ps
CPU time	1.27 seconds
Started	Sep 01 06:19:45 AM UTC 24
Finished	Sep 01 06:19:47 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196009887 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.2196009887
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3493953004
Short name	T64
Test name
Test status
Simulation time	20695250 ps
CPU time	1.27 seconds
Started	Sep 01 06:19:42 AM UTC 24
Finished	Sep 01 06:19:44 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493953004 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.3493953004
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.2372557891
Short name	T70
Test name
Test status
Simulation time	40723368 ps
CPU time	1.24 seconds
Started	Sep 01 06:19:41 AM UTC 24
Finished	Sep 01 06:19:43 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372557891 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2372557891
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.2298611031
Short name	T65
Test name
Test status
Simulation time	18658168 ps
CPU time	1.3 seconds
Started	Sep 01 06:19:42 AM UTC 24
Finished	Sep 01 06:19:44 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298611031 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.2298611031
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.1262525718
Short name	T86
Test name
Test status
Simulation time	76917795 ps
CPU time	1.59 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:41 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262525718 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1262525718
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.362542663
Short name	T2
Test name
Test status
Simulation time	201754761 ps
CPU time	3.98 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:43 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362542663 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.362542663
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.2827451682
Short name	T21
Test name
Test status
Simulation time	1245026752 ps
CPU time	6.98 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:46 AM UTC 24
Peak memory	210400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827451682 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.2827451682
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.785727579
Short name	T66
Test name
Test status
Simulation time	85860161 ps
CPU time	1.73 seconds
Started	Sep 01 06:19:42 AM UTC 24
Finished	Sep 01 06:19:45 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785727579 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.785727579
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3002276445
Short name	T62
Test name
Test status
Simulation time	15952622 ps
CPU time	1.21 seconds
Started	Sep 01 06:19:42 AM UTC 24
Finished	Sep 01 06:19:44 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002276445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.3002276445
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3263000378
Short name	T63
Test name
Test status
Simulation time	21835511 ps
CPU time	1.29 seconds
Started	Sep 01 06:19:42 AM UTC 24
Finished	Sep 01 06:19:44 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263000378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.3263000378
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.284976844
Short name	T85
Test name
Test status
Simulation time	30980040 ps
CPU time	1.19 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:41 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284976844 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.284976844
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.3719798169
Short name	T71
Test name
Test status
Simulation time	839175089 ps
CPU time	5.34 seconds
Started	Sep 01 06:19:45 AM UTC 24
Finished	Sep 01 06:19:51 AM UTC 24
Peak memory	242728 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719798169 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.3719798169
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.3979884162
Short name	T72
Test name
Test status
Simulation time	65494508 ps
CPU time	1.56 seconds
Started	Sep 01 06:19:38 AM UTC 24
Finished	Sep 01 06:19:41 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979884162 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3979884162
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.1449138054
Short name	T40
Test name
Test status
Simulation time	1164137894 ps
CPU time	7.76 seconds
Started	Sep 01 06:19:45 AM UTC 24
Finished	Sep 01 06:19:54 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449138054 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.1449138054
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.346318454
Short name	T16
Test name
Test status
Simulation time	2313358069 ps
CPU time	35.06 seconds
Started	Sep 01 06:19:45 AM UTC 24
Finished	Sep 01 06:20:21 AM UTC 24
Peak memory	227544 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346318454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.346318454
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.1713484934
Short name	T61
Test name
Test status
Simulation time	113247052 ps
CPU time	1.98 seconds
Started	Sep 01 06:19:41 AM UTC 24
Finished	Sep 01 06:19:44 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713484934 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1713484934
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.98630963
Short name	T381
Test name
Test status
Simulation time	28487390 ps
CPU time	1.28 seconds
Started	Sep 01 06:20:54 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98630963 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.98630963
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3221424327
Short name	T135
Test name
Test status
Simulation time	17905574 ps
CPU time	0.94 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221424327 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3221424327
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.3644972740
Short name	T375
Test name
Test status
Simulation time	29664475 ps
CPU time	1.19 seconds
Started	Sep 01 06:20:52 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644972740 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.3644972740
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.2202607757
Short name	T378
Test name
Test status
Simulation time	22721413 ps
CPU time	1.32 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202607757 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.2202607757
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.973732955
Short name	T374
Test name
Test status
Simulation time	22996101 ps
CPU time	1.25 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:20:54 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973732955 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.973732955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.3701878589
Short name	T427
Test name
Test status
Simulation time	1636984552 ps
CPU time	15.02 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3701878589 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.3701878589
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.1842290566
Short name	T424
Test name
Test status
Simulation time	1454974490 ps
CPU time	14.65 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842290566 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.1842290566
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.4263755450
Short name	T379
Test name
Test status
Simulation time	70306674 ps
CPU time	1.5 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263755450 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.4263755450
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3864364723
Short name	T376
Test name
Test status
Simulation time	52066025 ps
CPU time	1.32 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864364723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.3864364723
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2985821249
Short name	T377
Test name
Test status
Simulation time	47478839 ps
CPU time	1.27 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:20:55 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985821249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.2985821249
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.4253690892
Short name	T373
Test name
Test status
Simulation time	50309822 ps
CPU time	1.15 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:20:54 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253690892 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.4253690892
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.1071200214
Short name	T182
Test name
Test status
Simulation time	449016822 ps
CPU time	4.18 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1071200214 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1071200214
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.3263156959
Short name	T175
Test name
Test status
Simulation time	95526641 ps
CPU time	1.27 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:20:54 AM UTC 24
Peak memory	209948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263156959 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3263156959
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.2662587028
Short name	T581
Test name
Test status
Simulation time	7160168035 ps
CPU time	58.51 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662587028 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.2662587028
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.3746025352
Short name	T536
Test name
Test status
Simulation time	2290278596 ps
CPU time	43.8 seconds
Started	Sep 01 06:20:53 AM UTC 24
Finished	Sep 01 06:21:38 AM UTC 24
Peak memory	220264 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746025352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3746025352
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.874172955
Short name	T371
Test name
Test status
Simulation time	57563236 ps
CPU time	0.96 seconds
Started	Sep 01 06:20:51 AM UTC 24
Finished	Sep 01 06:20:53 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874172955 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.874172955
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.746846688
Short name	T393
Test name
Test status
Simulation time	15626731 ps
CPU time	1.18 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746846688 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.746846688
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3498514918
Short name	T392
Test name
Test status
Simulation time	39110628 ps
CPU time	1.33 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498514918 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.3498514918
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.3945500603
Short name	T382
Test name
Test status
Simulation time	39533511 ps
CPU time	1.15 seconds
Started	Sep 01 06:20:55 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945500603 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.3945500603
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.2248730566
Short name	T388
Test name
Test status
Simulation time	27498555 ps
CPU time	1.04 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248730566 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.2248730566
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.1903167108
Short name	T384
Test name
Test status
Simulation time	37201794 ps
CPU time	1.43 seconds
Started	Sep 01 06:20:54 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903167108 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1903167108
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.1320401492
Short name	T394
Test name
Test status
Simulation time	575986417 ps
CPU time	4.28 seconds
Started	Sep 01 06:20:54 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320401492 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.1320401492
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.3340512448
Short name	T461
Test name
Test status
Simulation time	2296689874 ps
CPU time	21.58 seconds
Started	Sep 01 06:20:54 AM UTC 24
Finished	Sep 01 06:21:17 AM UTC 24
Peak memory	210836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340512448 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.3340512448
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.2290838151
Short name	T386
Test name
Test status
Simulation time	53943044 ps
CPU time	1.41 seconds
Started	Sep 01 06:20:55 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290838151 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.2290838151
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1886055408
Short name	T390
Test name
Test status
Simulation time	216765926 ps
CPU time	2.39 seconds
Started	Sep 01 06:20:55 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	210304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886055408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.1886055408
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3227607091
Short name	T387
Test name
Test status
Simulation time	26778113 ps
CPU time	1.41 seconds
Started	Sep 01 06:20:55 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227607091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.3227607091
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.4292977945
Short name	T385
Test name
Test status
Simulation time	179780934 ps
CPU time	1.4 seconds
Started	Sep 01 06:20:55 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292977945 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.4292977945
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.2231330166
Short name	T409
Test name
Test status
Simulation time	1300492148 ps
CPU time	5.76 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231330166 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2231330166
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.3198449139
Short name	T380
Test name
Test status
Simulation time	28697408 ps
CPU time	1.34 seconds
Started	Sep 01 06:20:54 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198449139 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.3198449139
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.1759248355
Short name	T509
Test name
Test status
Simulation time	8002500025 ps
CPU time	33.13 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:21:31 AM UTC 24
Peak memory	210832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759248355 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.1759248355
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.1232705033
Short name	T183
Test name
Test status
Simulation time	2115196317 ps
CPU time	32.03 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:21:30 AM UTC 24
Peak memory	220360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232705033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1232705033
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.4288739406
Short name	T383
Test name
Test status
Simulation time	30142250 ps
CPU time	1.3 seconds
Started	Sep 01 06:20:55 AM UTC 24
Finished	Sep 01 06:20:57 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288739406 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.4288739406
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.2757988280
Short name	T405
Test name
Test status
Simulation time	46249791 ps
CPU time	1.36 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:02 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757988280 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.2757988280
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.4146818556
Short name	T403
Test name
Test status
Simulation time	37272107 ps
CPU time	1.35 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:02 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146818556 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.4146818556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.1401151349
Short name	T398
Test name
Test status
Simulation time	15881838 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:58 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401151349 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1401151349
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.3106647463
Short name	T404
Test name
Test status
Simulation time	25433379 ps
CPU time	1.35 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:02 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106647463 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.3106647463
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2812139382
Short name	T395
Test name
Test status
Simulation time	16365380 ps
CPU time	1.21 seconds
Started	Sep 01 06:20:57 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812139382 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2812139382
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.852016744
Short name	T450
Test name
Test status
Simulation time	1397956676 ps
CPU time	15.54 seconds
Started	Sep 01 06:20:58 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852016744 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.852016744
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.658800023
Short name	T401
Test name
Test status
Simulation time	157025922 ps
CPU time	2.05 seconds
Started	Sep 01 06:20:58 AM UTC 24
Finished	Sep 01 06:21:01 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658800023 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.658800023
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.3566744724
Short name	T396
Test name
Test status
Simulation time	25908955 ps
CPU time	1.07 seconds
Started	Sep 01 06:20:58 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566744724 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3566744724
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2998530155
Short name	T402
Test name
Test status
Simulation time	23743053 ps
CPU time	1.36 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:01 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998530155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.2998530155
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1867784316
Short name	T408
Test name
Test status
Simulation time	174964467 ps
CPU time	2.37 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867784316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.1867784316
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.3658755007
Short name	T397
Test name
Test status
Simulation time	17336461 ps
CPU time	1.21 seconds
Started	Sep 01 06:20:58 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658755007 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3658755007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.3835927081
Short name	T425
Test name
Test status
Simulation time	1291778042 ps
CPU time	6.99 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835927081 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.3835927081
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.1418563823
Short name	T342
Test name
Test status
Simulation time	134881521 ps
CPU time	1.91 seconds
Started	Sep 01 06:20:56 AM UTC 24
Finished	Sep 01 06:20:59 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418563823 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1418563823
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.2176435565
Short name	T698
Test name
Test status
Simulation time	11765089778 ps
CPU time	84.97 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:22:26 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176435565 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2176435565
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.1713908941
Short name	T587
Test name
Test status
Simulation time	2839605556 ps
CPU time	55.23 seconds
Started	Sep 01 06:20:59 AM UTC 24
Finished	Sep 01 06:21:56 AM UTC 24
Peak memory	220292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713908941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1713908941
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.2287409115
Short name	T400
Test name
Test status
Simulation time	24839660 ps
CPU time	1.37 seconds
Started	Sep 01 06:20:58 AM UTC 24
Finished	Sep 01 06:21:00 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287409115 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.2287409115
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.2950794189
Short name	T420
Test name
Test status
Simulation time	47926302 ps
CPU time	1.35 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950794189 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.2950794189
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.120117204
Short name	T419
Test name
Test status
Simulation time	141450407 ps
CPU time	1.8 seconds
Started	Sep 01 06:21:02 AM UTC 24
Finished	Sep 01 06:21:05 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120117204 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.120117204
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.2402133424
Short name	T414
Test name
Test status
Simulation time	24496227 ps
CPU time	1.19 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402133424 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2402133424
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.3955465808
Short name	T417
Test name
Test status
Simulation time	14567049 ps
CPU time	1.14 seconds
Started	Sep 01 06:21:02 AM UTC 24
Finished	Sep 01 06:21:05 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955465808 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.3955465808
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.50142914
Short name	T410
Test name
Test status
Simulation time	110702398 ps
CPU time	1.27 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50142914 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.50142914
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.1865099858
Short name	T449
Test name
Test status
Simulation time	1424224423 ps
CPU time	12.01 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865099858 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1865099858
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.2018439906
Short name	T432
Test name
Test status
Simulation time	1155751620 ps
CPU time	7.77 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:10 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018439906 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.2018439906
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.1894197973
Short name	T415
Test name
Test status
Simulation time	63103787 ps
CPU time	1.58 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:04 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894197973 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.1894197973
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.312114436
Short name	T416
Test name
Test status
Simulation time	19426757 ps
CPU time	1.3 seconds
Started	Sep 01 06:21:02 AM UTC 24
Finished	Sep 01 06:21:05 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312114436 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.312114436
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3067938913
Short name	T418
Test name
Test status
Simulation time	31570656 ps
CPU time	1.44 seconds
Started	Sep 01 06:21:02 AM UTC 24
Finished	Sep 01 06:21:05 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067938913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.3067938913
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.1344534498
Short name	T411
Test name
Test status
Simulation time	23168370 ps
CPU time	1.14 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344534498 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1344534498
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.3643643053
Short name	T455
Test name
Test status
Simulation time	953316067 ps
CPU time	10.92 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:16 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643643053 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3643643053
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.4120305258
Short name	T412
Test name
Test status
Simulation time	38119656 ps
CPU time	1.36 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	210204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120305258 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.4120305258
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.2682987607
Short name	T76
Test name
Test status
Simulation time	5957979739 ps
CPU time	34.31 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:40 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682987607 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.2682987607
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.3150464700
Short name	T413
Test name
Test status
Simulation time	17128133 ps
CPU time	1.24 seconds
Started	Sep 01 06:21:01 AM UTC 24
Finished	Sep 01 06:21:03 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3150464700 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3150464700
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.1862128773
Short name	T438
Test name
Test status
Simulation time	83413216 ps
CPU time	1.58 seconds
Started	Sep 01 06:21:08 AM UTC 24
Finished	Sep 01 06:21:11 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862128773 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.1862128773
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.985524731
Short name	T430
Test name
Test status
Simulation time	83583123 ps
CPU time	1.76 seconds
Started	Sep 01 06:21:06 AM UTC 24
Finished	Sep 01 06:21:09 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985524731 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.985524731
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.2200326415
Short name	T428
Test name
Test status
Simulation time	17188595 ps
CPU time	1.2 seconds
Started	Sep 01 06:21:06 AM UTC 24
Finished	Sep 01 06:21:08 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200326415 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2200326415
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.2342738669
Short name	T434
Test name
Test status
Simulation time	74316305 ps
CPU time	1.54 seconds
Started	Sep 01 06:21:07 AM UTC 24
Finished	Sep 01 06:21:10 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342738669 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.2342738669
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.189035499
Short name	T423
Test name
Test status
Simulation time	90386725 ps
CPU time	1.67 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189035499 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.189035499
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.2100845526
Short name	T448
Test name
Test status
Simulation time	563209773 ps
CPU time	8.08 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100845526 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2100845526
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.2206828072
Short name	T436
Test name
Test status
Simulation time	1065520413 ps
CPU time	5.58 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:11 AM UTC 24
Peak memory	210292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206828072 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.2206828072
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.2917715403
Short name	T429
Test name
Test status
Simulation time	61170870 ps
CPU time	1.51 seconds
Started	Sep 01 06:21:06 AM UTC 24
Finished	Sep 01 06:21:09 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917715403 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.2917715403
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2935646543
Short name	T431
Test name
Test status
Simulation time	109042988 ps
CPU time	1.84 seconds
Started	Sep 01 06:21:06 AM UTC 24
Finished	Sep 01 06:21:09 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935646543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.2935646543
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3432325214
Short name	T433
Test name
Test status
Simulation time	167616274 ps
CPU time	2.35 seconds
Started	Sep 01 06:21:06 AM UTC 24
Finished	Sep 01 06:21:10 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432325214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.3432325214
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.94495839
Short name	T422
Test name
Test status
Simulation time	16832122 ps
CPU time	1.21 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94495839 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3 1/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.94495839
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.3579913973
Short name	T447
Test name
Test status
Simulation time	680281457 ps
CPU time	5.51 seconds
Started	Sep 01 06:21:07 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	210868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3579913973 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3579913973
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.1866807556
Short name	T421
Test name
Test status
Simulation time	22695271 ps
CPU time	1.31 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866807556 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1866807556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.1045171315
Short name	T716
Test name
Test status
Simulation time	11007930621 ps
CPU time	80.92 seconds
Started	Sep 01 06:21:08 AM UTC 24
Finished	Sep 01 06:22:31 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045171315 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1045171315
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.3014363616
Short name	T100
Test name
Test status
Simulation time	901990565 ps
CPU time	16.91 seconds
Started	Sep 01 06:21:07 AM UTC 24
Finished	Sep 01 06:21:25 AM UTC 24
Peak memory	220196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014363616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.3014363616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.2624988234
Short name	T426
Test name
Test status
Simulation time	145964319 ps
CPU time	1.81 seconds
Started	Sep 01 06:21:04 AM UTC 24
Finished	Sep 01 06:21:07 AM UTC 24
Peak memory	208824 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624988234 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2624988234
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.3076952131
Short name	T451
Test name
Test status
Simulation time	33250853 ps
CPU time	1.24 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:15 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076952131 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.3076952131
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.3335590467
Short name	T446
Test name
Test status
Simulation time	23885827 ps
CPU time	1.34 seconds
Started	Sep 01 06:21:11 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335590467 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.3335590467
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.3615095349
Short name	T440
Test name
Test status
Simulation time	23912882 ps
CPU time	1.15 seconds
Started	Sep 01 06:21:10 AM UTC 24
Finished	Sep 01 06:21:12 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615095349 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3615095349
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.3389025266
Short name	T445
Test name
Test status
Simulation time	18156660 ps
CPU time	1.24 seconds
Started	Sep 01 06:21:12 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389025266 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.3389025266
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.4022167739
Short name	T437
Test name
Test status
Simulation time	52475883 ps
CPU time	1.38 seconds
Started	Sep 01 06:21:09 AM UTC 24
Finished	Sep 01 06:21:11 AM UTC 24
Peak memory	210128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022167739 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.4022167739
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.1323459428
Short name	T469
Test name
Test status
Simulation time	1528799836 ps
CPU time	9.62 seconds
Started	Sep 01 06:21:09 AM UTC 24
Finished	Sep 01 06:21:20 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323459428 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.1323459428
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.1047912207
Short name	T497
Test name
Test status
Simulation time	2302385940 ps
CPU time	17.87 seconds
Started	Sep 01 06:21:09 AM UTC 24
Finished	Sep 01 06:21:28 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047912207 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.1047912207
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.1545117079
Short name	T443
Test name
Test status
Simulation time	153672045 ps
CPU time	2.19 seconds
Started	Sep 01 06:21:10 AM UTC 24
Finished	Sep 01 06:21:13 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545117079 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1545117079
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1369073533
Short name	T444
Test name
Test status
Simulation time	20527912 ps
CPU time	1.29 seconds
Started	Sep 01 06:21:11 AM UTC 24
Finished	Sep 01 06:21:14 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369073533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.1369073533
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3856033639
Short name	T441
Test name
Test status
Simulation time	55131348 ps
CPU time	1.19 seconds
Started	Sep 01 06:21:10 AM UTC 24
Finished	Sep 01 06:21:12 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856033639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.3856033639
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.201425472
Short name	T439
Test name
Test status
Simulation time	27652216 ps
CPU time	1.16 seconds
Started	Sep 01 06:21:09 AM UTC 24
Finished	Sep 01 06:21:11 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201425472 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.201425472
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.3672921896
Short name	T466
Test name
Test status
Simulation time	878004547 ps
CPU time	5.75 seconds
Started	Sep 01 06:21:12 AM UTC 24
Finished	Sep 01 06:21:18 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672921896 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3672921896
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.2678306919
Short name	T435
Test name
Test status
Simulation time	18359443 ps
CPU time	1.29 seconds
Started	Sep 01 06:21:09 AM UTC 24
Finished	Sep 01 06:21:11 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678306919 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2678306919
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.1582806781
Short name	T540
Test name
Test status
Simulation time	2657161942 ps
CPU time	25.77 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:40 AM UTC 24
Peak memory	210808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582806781 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.1582806781
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.1629217673
Short name	T185
Test name
Test status
Simulation time	1205445381 ps
CPU time	17.02 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:31 AM UTC 24
Peak memory	220204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629217673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.1629217673
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.3723597493
Short name	T442
Test name
Test status
Simulation time	58527103 ps
CPU time	1.44 seconds
Started	Sep 01 06:21:10 AM UTC 24
Finished	Sep 01 06:21:12 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723597493 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.3723597493
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.4225436462
Short name	T467
Test name
Test status
Simulation time	20066430 ps
CPU time	1.09 seconds
Started	Sep 01 06:21:16 AM UTC 24
Finished	Sep 01 06:21:18 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225436462 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.4225436462
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3678866742
Short name	T136
Test name
Test status
Simulation time	30164669 ps
CPU time	1.53 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:17 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678866742 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.3678866742
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.1369271637
Short name	T458
Test name
Test status
Simulation time	24439257 ps
CPU time	1.23 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:17 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369271637 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1369271637
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.832048615
Short name	T462
Test name
Test status
Simulation time	62820259 ps
CPU time	1.55 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:18 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832048615 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.832048615
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.1703414174
Short name	T453
Test name
Test status
Simulation time	25018078 ps
CPU time	1.22 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:15 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703414174 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1703414174
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.4012094209
Short name	T525
Test name
Test status
Simulation time	1756571482 ps
CPU time	19.06 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:34 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012094209 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.4012094209
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.1410863911
Short name	T490
Test name
Test status
Simulation time	1585999232 ps
CPU time	11.36 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:26 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410863911 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.1410863911
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.4057592864
Short name	T463
Test name
Test status
Simulation time	107464405 ps
CPU time	1.85 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:18 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057592864 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.4057592864
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3106556127
Short name	T459
Test name
Test status
Simulation time	21124242 ps
CPU time	1.37 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:17 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106556127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.3106556127
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.801309400
Short name	T460
Test name
Test status
Simulation time	51522166 ps
CPU time	1.42 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:17 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801309400 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.801309400
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.1464011111
Short name	T456
Test name
Test status
Simulation time	52739339 ps
CPU time	1.43 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:16 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464011111 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1464011111
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.3966009058
Short name	T465
Test name
Test status
Simulation time	112754596 ps
CPU time	2.16 seconds
Started	Sep 01 06:21:15 AM UTC 24
Finished	Sep 01 06:21:18 AM UTC 24
Peak memory	210488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966009058 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3966009058
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.2524869499
Short name	T454
Test name
Test status
Simulation time	42246098 ps
CPU time	1.45 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:16 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524869499 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2524869499
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.4263995371
Short name	T507
Test name
Test status
Simulation time	1584732677 ps
CPU time	13.16 seconds
Started	Sep 01 06:21:16 AM UTC 24
Finished	Sep 01 06:21:30 AM UTC 24
Peak memory	210592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263995371 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.4263995371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.645647795
Short name	T741
Test name
Test status
Simulation time	6560340100 ps
CPU time	78.49 seconds
Started	Sep 01 06:21:16 AM UTC 24
Finished	Sep 01 06:22:36 AM UTC 24
Peak memory	224620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645647795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.645647795
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.1093671168
Short name	T457
Test name
Test status
Simulation time	179245656 ps
CPU time	2.47 seconds
Started	Sep 01 06:21:13 AM UTC 24
Finished	Sep 01 06:21:17 AM UTC 24
Peak memory	210428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093671168 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1093671168
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.2815816047
Short name	T478
Test name
Test status
Simulation time	31672095 ps
CPU time	1.22 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:22 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815816047 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.2815816047
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.2718729286
Short name	T474
Test name
Test status
Simulation time	16170828 ps
CPU time	1.21 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:21 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718729286 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.2718729286
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.3604137520
Short name	T471
Test name
Test status
Simulation time	13588634 ps
CPU time	1 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:21 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3604137520 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3604137520
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.3589020207
Short name	T475
Test name
Test status
Simulation time	28647544 ps
CPU time	1.18 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:21 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589020207 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.3589020207
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.2103961228
Short name	T468
Test name
Test status
Simulation time	19942120 ps
CPU time	1.24 seconds
Started	Sep 01 06:21:16 AM UTC 24
Finished	Sep 01 06:21:19 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103961228 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2103961228
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.965105044
Short name	T529
Test name
Test status
Simulation time	2357350462 ps
CPU time	18.99 seconds
Started	Sep 01 06:21:16 AM UTC 24
Finished	Sep 01 06:21:37 AM UTC 24
Peak memory	210808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965105044 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.965105044
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.2664683031
Short name	T499
Test name
Test status
Simulation time	860026245 ps
CPU time	9.91 seconds
Started	Sep 01 06:21:18 AM UTC 24
Finished	Sep 01 06:21:28 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664683031 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.2664683031
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.1204005999
Short name	T476
Test name
Test status
Simulation time	46546802 ps
CPU time	1.53 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:21 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204005999 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.1204005999
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.4082532232
Short name	T473
Test name
Test status
Simulation time	25148721 ps
CPU time	1.15 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:21 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082532232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.4082532232
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.4178887471
Short name	T477
Test name
Test status
Simulation time	48611583 ps
CPU time	1.49 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:22 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178887471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.4178887471
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.3825565473
Short name	T470
Test name
Test status
Simulation time	80064578 ps
CPU time	1.57 seconds
Started	Sep 01 06:21:18 AM UTC 24
Finished	Sep 01 06:21:20 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825565473 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3825565473
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.644780454
Short name	T489
Test name
Test status
Simulation time	584943237 ps
CPU time	5.28 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:26 AM UTC 24
Peak memory	210520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644780454 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.644780454
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.3739405149
Short name	T407
Test name
Test status
Simulation time	22953123 ps
CPU time	1.34 seconds
Started	Sep 01 06:21:16 AM UTC 24
Finished	Sep 01 06:21:19 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739405149 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3739405149
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.2745985508
Short name	T558
Test name
Test status
Simulation time	3437612680 ps
CPU time	26.62 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:47 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745985508 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.2745985508
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.3189156830
Short name	T186
Test name
Test status
Simulation time	5987688923 ps
CPU time	29.89 seconds
Started	Sep 01 06:21:19 AM UTC 24
Finished	Sep 01 06:21:51 AM UTC 24
Peak memory	224616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189156830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.3189156830
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.3545948909
Short name	T472
Test name
Test status
Simulation time	305995672 ps
CPU time	2.27 seconds
Started	Sep 01 06:21:18 AM UTC 24
Finished	Sep 01 06:21:21 AM UTC 24
Peak memory	210288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545948909 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3545948909
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.3911362988
Short name	T492
Test name
Test status
Simulation time	52533024 ps
CPU time	1.44 seconds
Started	Sep 01 06:21:25 AM UTC 24
Finished	Sep 01 06:21:27 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911362988 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.3911362988
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.606189862
Short name	T485
Test name
Test status
Simulation time	19747898 ps
CPU time	1.27 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:25 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606189862 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.606189862
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.1981828225
Short name	T481
Test name
Test status
Simulation time	16624369 ps
CPU time	1.08 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:23 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981828225 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1981828225
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.2782074446
Short name	T486
Test name
Test status
Simulation time	14379410 ps
CPU time	1.24 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:25 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782074446 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.2782074446
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.793938028
Short name	T483
Test name
Test status
Simulation time	281436945 ps
CPU time	2.3 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:24 AM UTC 24
Peak memory	210236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793938028 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.793938028
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.203385031
Short name	T516
Test name
Test status
Simulation time	1414354359 ps
CPU time	10.5 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203385031 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.203385031
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.143210690
Short name	T495
Test name
Test status
Simulation time	988062017 ps
CPU time	4.88 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:27 AM UTC 24
Peak memory	210652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143210690 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.143210690
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.2668746485
Short name	T487
Test name
Test status
Simulation time	206138252 ps
CPU time	1.69 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:25 AM UTC 24
Peak memory	208848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668746485 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.2668746485
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2679832664
Short name	T488
Test name
Test status
Simulation time	73346096 ps
CPU time	1.67 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:25 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679832664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.2679832664
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2941835994
Short name	T484
Test name
Test status
Simulation time	30755585 ps
CPU time	1.36 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:25 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941835994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.2941835994
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.3425576804
Short name	T482
Test name
Test status
Simulation time	27991926 ps
CPU time	1.26 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:24 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425576804 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3425576804
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.3581253908
Short name	T494
Test name
Test status
Simulation time	194604064 ps
CPU time	3.11 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:27 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581253908 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.3581253908
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.3412280550
Short name	T480
Test name
Test status
Simulation time	21722841 ps
CPU time	1.32 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:23 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412280550 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3412280550
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.4117999074
Short name	T586
Test name
Test status
Simulation time	7121991239 ps
CPU time	31.26 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:55 AM UTC 24
Peak memory	210768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117999074 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.4117999074
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.3449057400
Short name	T568
Test name
Test status
Simulation time	1863007990 ps
CPU time	27.19 seconds
Started	Sep 01 06:21:23 AM UTC 24
Finished	Sep 01 06:21:51 AM UTC 24
Peak memory	227152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449057400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3449057400
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.2906871894
Short name	T479
Test name
Test status
Simulation time	19468622 ps
CPU time	1.03 seconds
Started	Sep 01 06:21:21 AM UTC 24
Finished	Sep 01 06:21:23 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906871894 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2906871894
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.1706799195
Short name	T510
Test name
Test status
Simulation time	53199896 ps
CPU time	1.29 seconds
Started	Sep 01 06:21:28 AM UTC 24
Finished	Sep 01 06:21:31 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706799195 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.1706799195
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2174533371
Short name	T506
Test name
Test status
Simulation time	148234063 ps
CPU time	1.48 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:29 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174533371 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.2174533371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.1204755819
Short name	T500
Test name
Test status
Simulation time	51000974 ps
CPU time	1.31 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:28 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204755819 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.1204755819
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.2119534232
Short name	T505
Test name
Test status
Simulation time	35394816 ps
CPU time	1.44 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:29 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119534232 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.2119534232
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.1692122371
Short name	T491
Test name
Test status
Simulation time	12703205 ps
CPU time	1.17 seconds
Started	Sep 01 06:21:25 AM UTC 24
Finished	Sep 01 06:21:27 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692122371 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1692122371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.2709886197
Short name	T520
Test name
Test status
Simulation time	803239504 ps
CPU time	7.37 seconds
Started	Sep 01 06:21:25 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709886197 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2709886197
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.601204369
Short name	T527
Test name
Test status
Simulation time	2025329219 ps
CPU time	10.09 seconds
Started	Sep 01 06:21:25 AM UTC 24
Finished	Sep 01 06:21:36 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601204369 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.601204369
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.1073534799
Short name	T501
Test name
Test status
Simulation time	54182385 ps
CPU time	1.37 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:29 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073534799 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.1073534799
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.880891212
Short name	T503
Test name
Test status
Simulation time	23593519 ps
CPU time	1.39 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:29 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880891212 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.880891212
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1383666171
Short name	T504
Test name
Test status
Simulation time	54325217 ps
CPU time	1.53 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:29 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383666171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.1383666171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.3948043425
Short name	T498
Test name
Test status
Simulation time	35052722 ps
CPU time	1.17 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:28 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948043425 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3948043425
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.738556919
Short name	T512
Test name
Test status
Simulation time	218399689 ps
CPU time	2.3 seconds
Started	Sep 01 06:21:28 AM UTC 24
Finished	Sep 01 06:21:32 AM UTC 24
Peak memory	210304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738556919 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.738556919
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.3547992221
Short name	T493
Test name
Test status
Simulation time	60889069 ps
CPU time	1.42 seconds
Started	Sep 01 06:21:25 AM UTC 24
Finished	Sep 01 06:21:27 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547992221 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3547992221
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.2650552362
Short name	T556
Test name
Test status
Simulation time	2227254222 ps
CPU time	14.35 seconds
Started	Sep 01 06:21:28 AM UTC 24
Finished	Sep 01 06:21:44 AM UTC 24
Peak memory	210968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650552362 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.2650552362
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.3162151103
Short name	T187
Test name
Test status
Simulation time	2349984801 ps
CPU time	33.54 seconds
Started	Sep 01 06:21:28 AM UTC 24
Finished	Sep 01 06:22:03 AM UTC 24
Peak memory	220232 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162151103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.3162151103
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.582225273
Short name	T502
Test name
Test status
Simulation time	131859657 ps
CPU time	1.65 seconds
Started	Sep 01 06:21:26 AM UTC 24
Finished	Sep 01 06:21:29 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582225273 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.582225273
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.2275533361
Short name	T214
Test name
Test status
Simulation time	26530887 ps
CPU time	1.24 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:19:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275533361 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.2275533361
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.249817408
Short name	T204
Test name
Test status
Simulation time	350756172 ps
CPU time	2.2 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:51 AM UTC 24
Peak memory	210256 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249817408 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.249817408
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.2547056024
Short name	T26
Test name
Test status
Simulation time	28734308 ps
CPU time	1.17 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547056024 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2547056024
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.1164621557
Short name	T206
Test name
Test status
Simulation time	32121500 ps
CPU time	1.26 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:19:53 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164621557 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.1164621557
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.1088691974
Short name	T24
Test name
Test status
Simulation time	39008009 ps
CPU time	1.25 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088691974 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1088691974
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.354494616
Short name	T13
Test name
Test status
Simulation time	438241176 ps
CPU time	7.37 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	210556 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354494616 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.354494616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.3407660120
Short name	T113
Test name
Test status
Simulation time	2182260094 ps
CPU time	15.42 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:20:05 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407660120 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.3407660120
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.2440970684
Short name	T28
Test name
Test status
Simulation time	16186064 ps
CPU time	1.14 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440970684 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.2440970684
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.167489749
Short name	T203
Test name
Test status
Simulation time	24411381 ps
CPU time	1.32 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167489749 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.167489749
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1379984829
Short name	T27
Test name
Test status
Simulation time	15454581 ps
CPU time	1.14 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379984829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.1379984829
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.4068200082
Short name	T25
Test name
Test status
Simulation time	18018100 ps
CPU time	1.24 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068200082 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.4068200082
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.2219560145
Short name	T68
Test name
Test status
Simulation time	369736609 ps
CPU time	2.79 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:19:55 AM UTC 24
Peak memory	210620 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219560145 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2219560145
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.1404881869
Short name	T80
Test name
Test status
Simulation time	470012206 ps
CPU time	3.79 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	242604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404881869 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.1404881869
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.2327392417
Short name	T22
Test name
Test status
Simulation time	27139180 ps
CPU time	1.19 seconds
Started	Sep 01 06:19:45 AM UTC 24
Finished	Sep 01 06:19:47 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327392417 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2327392417
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.89117984
Short name	T569
Test name
Test status
Simulation time	14113549225 ps
CPU time	118.38 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89117984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.89117984
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.1271694465
Short name	T99
Test name
Test status
Simulation time	11880091233 ps
CPU time	87.32 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:21:20 AM UTC 24
Peak memory	224560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271694465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1271694465
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.1725883439
Short name	T155
Test name
Test status
Simulation time	26454004 ps
CPU time	1.35 seconds
Started	Sep 01 06:19:48 AM UTC 24
Finished	Sep 01 06:19:50 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725883439 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1725883439
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.1620123532
Short name	T517
Test name
Test status
Simulation time	12431969 ps
CPU time	0.88 seconds
Started	Sep 01 06:21:31 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620123532 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.1620123532
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1171998399
Short name	T518
Test name
Test status
Simulation time	28441351 ps
CPU time	1.2 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171998399 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1171998399
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.1118273272
Short name	T513
Test name
Test status
Simulation time	15070435 ps
CPU time	1.09 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:32 AM UTC 24
Peak memory	208852 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118273272 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1118273272
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.3983573553
Short name	T524
Test name
Test status
Simulation time	75537347 ps
CPU time	1.53 seconds
Started	Sep 01 06:21:31 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983573553 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.3983573553
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.2135285010
Short name	T511
Test name
Test status
Simulation time	20969903 ps
CPU time	1.28 seconds
Started	Sep 01 06:21:29 AM UTC 24
Finished	Sep 01 06:21:31 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135285010 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2135285010
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.3748545763
Short name	T541
Test name
Test status
Simulation time	1638153997 ps
CPU time	11.19 seconds
Started	Sep 01 06:21:29 AM UTC 24
Finished	Sep 01 06:21:41 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748545763 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3748545763
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.4209226289
Short name	T554
Test name
Test status
Simulation time	2303853912 ps
CPU time	12.83 seconds
Started	Sep 01 06:21:29 AM UTC 24
Finished	Sep 01 06:21:43 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209226289 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.4209226289
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.3259097615
Short name	T523
Test name
Test status
Simulation time	104868712 ps
CPU time	1.73 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259097615 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.3259097615
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.3564181804
Short name	T521
Test name
Test status
Simulation time	79257399 ps
CPU time	1.63 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564181804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.3564181804
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.664984223
Short name	T522
Test name
Test status
Simulation time	114779431 ps
CPU time	1.61 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664984223 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.664984223
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.2276986322
Short name	T514
Test name
Test status
Simulation time	14833519 ps
CPU time	1.22 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:32 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276986322 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2276986322
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.1090685624
Short name	T537
Test name
Test status
Simulation time	1308690694 ps
CPU time	6.69 seconds
Started	Sep 01 06:21:31 AM UTC 24
Finished	Sep 01 06:21:39 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090685624 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.1090685624
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.4069044496
Short name	T508
Test name
Test status
Simulation time	17239898 ps
CPU time	1.09 seconds
Started	Sep 01 06:21:28 AM UTC 24
Finished	Sep 01 06:21:31 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069044496 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.4069044496
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.2149333491
Short name	T593
Test name
Test status
Simulation time	3533964780 ps
CPU time	26.05 seconds
Started	Sep 01 06:21:31 AM UTC 24
Finished	Sep 01 06:21:58 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149333491 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.2149333491
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.3720144657
Short name	T671
Test name
Test status
Simulation time	4771918126 ps
CPU time	49.51 seconds
Started	Sep 01 06:21:31 AM UTC 24
Finished	Sep 01 06:22:22 AM UTC 24
Peak memory	227276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720144657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.3720144657
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.4099605887
Short name	T515
Test name
Test status
Simulation time	79221748 ps
CPU time	1.4 seconds
Started	Sep 01 06:21:30 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4099605887 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.4099605887
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1987680262
Short name	T562
Test name
Test status
Simulation time	25939447 ps
CPU time	0.92 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:21:47 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987680262 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.1987680262
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.2052610292
Short name	T526
Test name
Test status
Simulation time	16363024 ps
CPU time	1.06 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:34 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052610292 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2052610292
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.3350904655
Short name	T563
Test name
Test status
Simulation time	15582739 ps
CPU time	0.89 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:21:48 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350904655 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.3350904655
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.2985540345
Short name	T559
Test name
Test status
Simulation time	12134586 ps
CPU time	0.83 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:47 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985540345 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2985540345
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.2948222556
Short name	T557
Test name
Test status
Simulation time	2120638671 ps
CPU time	12.6 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:46 AM UTC 24
Peak memory	210680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948222556 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.2948222556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.3377946744
Short name	T535
Test name
Test status
Simulation time	499704692 ps
CPU time	4.44 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:38 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377946744 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.3377946744
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.2664399388
Short name	T543
Test name
Test status
Simulation time	77083466 ps
CPU time	1.08 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:41 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664399388 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.2664399388
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.662020279
Short name	T564
Test name
Test status
Simulation time	65802926 ps
CPU time	1.13 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:21:48 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662020279 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.662020279
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.135711165
Short name	T534
Test name
Test status
Simulation time	22986174 ps
CPU time	1.12 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:21:38 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135711165 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.135711165
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.3195419132
Short name	T560
Test name
Test status
Simulation time	22582615 ps
CPU time	0.87 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:47 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195419132 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.3195419132
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.1156727740
Short name	T565
Test name
Test status
Simulation time	421126802 ps
CPU time	2.8 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:21:50 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156727740 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.1156727740
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.2026799201
Short name	T519
Test name
Test status
Simulation time	17145428 ps
CPU time	1.08 seconds
Started	Sep 01 06:21:31 AM UTC 24
Finished	Sep 01 06:21:33 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026799201 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2026799201
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.232493385
Short name	T717
Test name
Test status
Simulation time	10815193593 ps
CPU time	44.49 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232493385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.232493385
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.1558805771
Short name	T843
Test name
Test status
Simulation time	20508526555 ps
CPU time	114.47 seconds
Started	Sep 01 06:21:34 AM UTC 24
Finished	Sep 01 06:23:42 AM UTC 24
Peak memory	220484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558805771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.1558805771
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.161328435
Short name	T542
Test name
Test status
Simulation time	16745122 ps
CPU time	0.87 seconds
Started	Sep 01 06:21:32 AM UTC 24
Finished	Sep 01 06:21:41 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161328435 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.161328435
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.3607209881
Short name	T664
Test name
Test status
Simulation time	44541490 ps
CPU time	0.85 seconds
Started	Sep 01 06:21:39 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607209881 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.3607209881
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.873928556
Short name	T550
Test name
Test status
Simulation time	14995875 ps
CPU time	0.87 seconds
Started	Sep 01 06:21:37 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873928556 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.873928556
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.777082807
Short name	T533
Test name
Test status
Simulation time	39643059 ps
CPU time	1.24 seconds
Started	Sep 01 06:21:35 AM UTC 24
Finished	Sep 01 06:21:38 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777082807 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.777082807
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.1085794298
Short name	T553
Test name
Test status
Simulation time	12782106 ps
CPU time	1 seconds
Started	Sep 01 06:21:37 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085794298 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.1085794298
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.250325377
Short name	T626
Test name
Test status
Simulation time	295229866 ps
CPU time	1.87 seconds
Started	Sep 01 06:21:35 AM UTC 24
Finished	Sep 01 06:22:09 AM UTC 24
Peak memory	209740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250325377 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.250325377
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.3045327007
Short name	T597
Test name
Test status
Simulation time	120023354 ps
CPU time	1.35 seconds
Started	Sep 01 06:21:36 AM UTC 24
Finished	Sep 01 06:22:02 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045327007 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.3045327007
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2678705099
Short name	T548
Test name
Test status
Simulation time	22589289 ps
CPU time	0.89 seconds
Started	Sep 01 06:21:37 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678705099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.2678705099
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.3601644580
Short name	T551
Test name
Test status
Simulation time	57025363 ps
CPU time	1.01 seconds
Started	Sep 01 06:21:37 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601644580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.3601644580
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.1926189515
Short name	T531
Test name
Test status
Simulation time	13207377 ps
CPU time	1.14 seconds
Started	Sep 01 06:21:35 AM UTC 24
Finished	Sep 01 06:21:37 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926189515 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1926189515
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.3559335275
Short name	T567
Test name
Test status
Simulation time	1042005013 ps
CPU time	3.7 seconds
Started	Sep 01 06:21:38 AM UTC 24
Finished	Sep 01 06:21:50 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559335275 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3559335275
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.1262968489
Short name	T817
Test name
Test status
Simulation time	9501517361 ps
CPU time	65.66 seconds
Started	Sep 01 06:21:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262968489 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.1262968489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.2217590610
Short name	T846
Test name
Test status
Simulation time	27369073235 ps
CPU time	122.53 seconds
Started	Sep 01 06:21:38 AM UTC 24
Finished	Sep 01 06:24:21 AM UTC 24
Peak memory	220492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217590610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.2217590610
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.1674628909
Short name	T530
Test name
Test status
Simulation time	28899013 ps
CPU time	1.07 seconds
Started	Sep 01 06:21:35 AM UTC 24
Finished	Sep 01 06:21:37 AM UTC 24
Peak memory	209968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674628909 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1674628909
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.1232604360
Short name	T596
Test name
Test status
Simulation time	53167688 ps
CPU time	0.81 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:22:01 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232604360 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.1232604360
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2517633433
Short name	T588
Test name
Test status
Simulation time	23580360 ps
CPU time	0.85 seconds
Started	Sep 01 06:21:42 AM UTC 24
Finished	Sep 01 06:21:57 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517633433 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.2517633433
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.3520172378
Short name	T547
Test name
Test status
Simulation time	18259763 ps
CPU time	0.78 seconds
Started	Sep 01 06:21:40 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520172378 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3520172378
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.1705473440
Short name	T589
Test name
Test status
Simulation time	70715406 ps
CPU time	0.92 seconds
Started	Sep 01 06:21:42 AM UTC 24
Finished	Sep 01 06:21:57 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705473440 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.1705473440
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.287482640
Short name	T659
Test name
Test status
Simulation time	27516596 ps
CPU time	0.74 seconds
Started	Sep 01 06:21:39 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210568 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287482640 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.287482640
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.3932790869
Short name	T555
Test name
Test status
Simulation time	201101593 ps
CPU time	1.69 seconds
Started	Sep 01 06:21:40 AM UTC 24
Finished	Sep 01 06:21:43 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932790869 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3932790869
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.3384399345
Short name	T566
Test name
Test status
Simulation time	1219392229 ps
CPU time	8.78 seconds
Started	Sep 01 06:21:40 AM UTC 24
Finished	Sep 01 06:21:50 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384399345 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.3384399345
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.1985645491
Short name	T544
Test name
Test status
Simulation time	12634689 ps
CPU time	0.65 seconds
Started	Sep 01 06:21:40 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985645491 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.1985645491
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.191827543
Short name	T584
Test name
Test status
Simulation time	23183745 ps
CPU time	0.87 seconds
Started	Sep 01 06:21:42 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191827543 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.191827543
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1052763073
Short name	T585
Test name
Test status
Simulation time	59858520 ps
CPU time	0.86 seconds
Started	Sep 01 06:21:42 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052763073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.1052763073
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.142436466
Short name	T546
Test name
Test status
Simulation time	20894376 ps
CPU time	0.77 seconds
Started	Sep 01 06:21:40 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	209756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142436466 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.142436466
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.1192228895
Short name	T604
Test name
Test status
Simulation time	664926811 ps
CPU time	3.13 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:22:04 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192228895 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1192228895
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.3571380883
Short name	T663
Test name
Test status
Simulation time	23551576 ps
CPU time	0.77 seconds
Started	Sep 01 06:21:39 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571380883 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.3571380883
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.1291962968
Short name	T801
Test name
Test status
Simulation time	12824397532 ps
CPU time	49.85 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:22:51 AM UTC 24
Peak memory	210840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291962968 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.1291962968
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.925722235
Short name	T832
Test name
Test status
Simulation time	11905963707 ps
CPU time	68.37 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:23:09 AM UTC 24
Peak memory	220328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925722235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.925722235
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.3982669401
Short name	T549
Test name
Test status
Simulation time	15756754 ps
CPU time	1.02 seconds
Started	Sep 01 06:21:40 AM UTC 24
Finished	Sep 01 06:21:42 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982669401 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3982669401
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.778052912
Short name	T570
Test name
Test status
Simulation time	14887279 ps
CPU time	0.71 seconds
Started	Sep 01 06:21:49 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778052912 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.778052912
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3717145024
Short name	T776
Test name
Test status
Simulation time	116704213 ps
CPU time	1.08 seconds
Started	Sep 01 06:21:47 AM UTC 24
Finished	Sep 01 06:22:43 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717145024 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.3717145024
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.2504787684
Short name	T577
Test name
Test status
Simulation time	29723187 ps
CPU time	0.71 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504787684 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.2504787684
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.1337771193
Short name	T580
Test name
Test status
Simulation time	56225914 ps
CPU time	0.95 seconds
Started	Sep 01 06:21:48 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337771193 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.1337771193
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.1556907437
Short name	T574
Test name
Test status
Simulation time	59785436 ps
CPU time	0.84 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556907437 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1556907437
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.2114705776
Short name	T608
Test name
Test status
Simulation time	1641134694 ps
CPU time	12.81 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:22:05 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114705776 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2114705776
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.2003045596
Short name	T602
Test name
Test status
Simulation time	1697231209 ps
CPU time	11.3 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:22:03 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003045596 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.2003045596
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.1104779276
Short name	T575
Test name
Test status
Simulation time	22942809 ps
CPU time	0.69 seconds
Started	Sep 01 06:21:44 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104779276 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.1104779276
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.280375325
Short name	T666
Test name
Test status
Simulation time	28478866 ps
CPU time	0.88 seconds
Started	Sep 01 06:21:45 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	209700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280375325 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.280375325
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.570762095
Short name	T578
Test name
Test status
Simulation time	55063197 ps
CPU time	0.84 seconds
Started	Sep 01 06:21:44 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570762095 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.570762095
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.3468312549
Short name	T576
Test name
Test status
Simulation time	33844857 ps
CPU time	0.75 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468312549 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.3468312549
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.1124301641
Short name	T591
Test name
Test status
Simulation time	1315010047 ps
CPU time	5.62 seconds
Started	Sep 01 06:21:48 AM UTC 24
Finished	Sep 01 06:21:58 AM UTC 24
Peak memory	210936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124301641 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1124301641
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.811355949
Short name	T573
Test name
Test status
Simulation time	24949238 ps
CPU time	0.81 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811355949 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.811355949
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.898035756
Short name	T594
Test name
Test status
Simulation time	1505659198 ps
CPU time	9.23 seconds
Started	Sep 01 06:21:48 AM UTC 24
Finished	Sep 01 06:22:01 AM UTC 24
Peak memory	210676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898035756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.898035756
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.2866496465
Short name	T188
Test name
Test status
Simulation time	1989301256 ps
CPU time	13.4 seconds
Started	Sep 01 06:21:48 AM UTC 24
Finished	Sep 01 06:22:05 AM UTC 24
Peak memory	220140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866496465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.2866496465
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.3733839321
Short name	T579
Test name
Test status
Simulation time	61683798 ps
CPU time	1.08 seconds
Started	Sep 01 06:21:43 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733839321 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3733839321
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.3997381878
Short name	T590
Test name
Test status
Simulation time	49772647 ps
CPU time	0.81 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:21:57 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997381878 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.3997381878
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.91835558
Short name	T625
Test name
Test status
Simulation time	24618494 ps
CPU time	0.88 seconds
Started	Sep 01 06:21:53 AM UTC 24
Finished	Sep 01 06:22:08 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91835558 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.91835558
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.4012265371
Short name	T619
Test name
Test status
Simulation time	15934557 ps
CPU time	0.8 seconds
Started	Sep 01 06:21:53 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012265371 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.4012265371
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.3387415998
Short name	T623
Test name
Test status
Simulation time	16701092 ps
CPU time	0.79 seconds
Started	Sep 01 06:21:53 AM UTC 24
Finished	Sep 01 06:22:08 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387415998 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3387415998
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.3686680431
Short name	T571
Test name
Test status
Simulation time	37078851 ps
CPU time	0.79 seconds
Started	Sep 01 06:21:50 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686680431 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3686680431
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.2635369626
Short name	T603
Test name
Test status
Simulation time	1400096398 ps
CPU time	10.97 seconds
Started	Sep 01 06:21:51 AM UTC 24
Finished	Sep 01 06:22:03 AM UTC 24
Peak memory	210504 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635369626 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2635369626
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.2191048365
Short name	T599
Test name
Test status
Simulation time	2389414585 ps
CPU time	9.86 seconds
Started	Sep 01 06:21:51 AM UTC 24
Finished	Sep 01 06:22:02 AM UTC 24
Peak memory	210736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191048365 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.2191048365
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.2855137068
Short name	T622
Test name
Test status
Simulation time	22939552 ps
CPU time	0.98 seconds
Started	Sep 01 06:21:53 AM UTC 24
Finished	Sep 01 06:22:08 AM UTC 24
Peak memory	210072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855137068 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.2855137068
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3922650783
Short name	T624
Test name
Test status
Simulation time	29853034 ps
CPU time	0.93 seconds
Started	Sep 01 06:21:53 AM UTC 24
Finished	Sep 01 06:22:08 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922650783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.3922650783
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.551947233
Short name	T621
Test name
Test status
Simulation time	34983916 ps
CPU time	0.9 seconds
Started	Sep 01 06:21:53 AM UTC 24
Finished	Sep 01 06:22:08 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551947233 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.551947233
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.4030727611
Short name	T583
Test name
Test status
Simulation time	27545191 ps
CPU time	0.82 seconds
Started	Sep 01 06:21:51 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030727611 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.4030727611
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.253236810
Short name	T595
Test name
Test status
Simulation time	1546873759 ps
CPU time	5.3 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:01 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253236810 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.253236810
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.2677572981
Short name	T572
Test name
Test status
Simulation time	62113511 ps
CPU time	0.94 seconds
Started	Sep 01 06:21:49 AM UTC 24
Finished	Sep 01 06:21:52 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677572981 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2677572981
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.1638254314
Short name	T798
Test name
Test status
Simulation time	6970543378 ps
CPU time	53.72 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:50 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638254314 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.1638254314
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.242298203
Short name	T210
Test name
Test status
Simulation time	1876644927 ps
CPU time	26.45 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:30 AM UTC 24
Peak memory	220196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242298203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.242298203
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.556815704
Short name	T582
Test name
Test status
Simulation time	32242962 ps
CPU time	0.76 seconds
Started	Sep 01 06:21:51 AM UTC 24
Finished	Sep 01 06:21:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556815704 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.556815704
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.2219182619
Short name	T601
Test name
Test status
Simulation time	16492542 ps
CPU time	0.75 seconds
Started	Sep 01 06:21:58 AM UTC 24
Finished	Sep 01 06:22:03 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219182619 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.2219182619
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3254015948
Short name	T770
Test name
Test status
Simulation time	30524578 ps
CPU time	0.96 seconds
Started	Sep 01 06:21:57 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	209652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254015948 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.3254015948
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.1353723435
Short name	T613
Test name
Test status
Simulation time	46017135 ps
CPU time	0.77 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353723435 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1353723435
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.1403725112
Short name	T769
Test name
Test status
Simulation time	17532867 ps
CPU time	0.73 seconds
Started	Sep 01 06:21:57 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	209660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403725112 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.1403725112
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.1245388343
Short name	T561
Test name
Test status
Simulation time	99427075 ps
CPU time	1.12 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245388343 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1245388343
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.2761197157
Short name	T657
Test name
Test status
Simulation time	1401514096 ps
CPU time	10.94 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	210372 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761197157 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2761197157
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.75584590
Short name	T631
Test name
Test status
Simulation time	1525262153 ps
CPU time	5.85 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75584590 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.75584590
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.4156793924
Short name	T545
Test name
Test status
Simulation time	22786262 ps
CPU time	0.81 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156793924 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.4156793924
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3165818938
Short name	T614
Test name
Test status
Simulation time	31032997 ps
CPU time	0.77 seconds
Started	Sep 01 06:21:55 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165818938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.3165818938
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3163638068
Short name	T617
Test name
Test status
Simulation time	84431120 ps
CPU time	0.94 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163638068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.3163638068
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.3065033787
Short name	T612
Test name
Test status
Simulation time	21875011 ps
CPU time	0.7 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065033787 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3065033787
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.2381917229
Short name	T610
Test name
Test status
Simulation time	1115101064 ps
CPU time	4.74 seconds
Started	Sep 01 06:21:58 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381917229 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2381917229
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.2188343999
Short name	T606
Test name
Test status
Simulation time	67445916 ps
CPU time	0.98 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:22:04 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188343999 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.2188343999
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.293636299
Short name	T829
Test name
Test status
Simulation time	8691104283 ps
CPU time	65.58 seconds
Started	Sep 01 06:21:58 AM UTC 24
Finished	Sep 01 06:23:08 AM UTC 24
Peak memory	210992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293636299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.293636299
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.2262441177
Short name	T749
Test name
Test status
Simulation time	2405987363 ps
CPU time	34.92 seconds
Started	Sep 01 06:21:58 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	220460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262441177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2262441177
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.1404445268
Short name	T592
Test name
Test status
Simulation time	349975813 ps
CPU time	1.68 seconds
Started	Sep 01 06:21:54 AM UTC 24
Finished	Sep 01 06:21:58 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404445268 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1404445268
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.2066009291
Short name	T662
Test name
Test status
Simulation time	37031492 ps
CPU time	0.79 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066009291 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.2066009291
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.449609557
Short name	T632
Test name
Test status
Simulation time	34107684 ps
CPU time	0.73 seconds
Started	Sep 01 06:22:03 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449609557 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.449609557
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.4075066516
Short name	T616
Test name
Test status
Simulation time	33607838 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:02 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075066516 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.4075066516
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.3625357892
Short name	T620
Test name
Test status
Simulation time	19258746 ps
CPU time	0.72 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:08 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625357892 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.3625357892
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.1420854790
Short name	T600
Test name
Test status
Simulation time	287295702 ps
CPU time	1.47 seconds
Started	Sep 01 06:21:59 AM UTC 24
Finished	Sep 01 06:22:02 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420854790 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1420854790
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.4212305102
Short name	T611
Test name
Test status
Simulation time	1225333048 ps
CPU time	5.91 seconds
Started	Sep 01 06:21:59 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212305102 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.4212305102
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.1611710506
Short name	T645
Test name
Test status
Simulation time	2184642090 ps
CPU time	11.86 seconds
Started	Sep 01 06:22:02 AM UTC 24
Finished	Sep 01 06:22:15 AM UTC 24
Peak memory	210736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611710506 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.1611710506
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.135179071
Short name	T638
Test name
Test status
Simulation time	102423570 ps
CPU time	1.12 seconds
Started	Sep 01 06:22:03 AM UTC 24
Finished	Sep 01 06:22:13 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135179071 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.135179071
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3748248147
Short name	T634
Test name
Test status
Simulation time	22418120 ps
CPU time	0.79 seconds
Started	Sep 01 06:22:03 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	209492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748248147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.3748248147
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1142326738
Short name	T633
Test name
Test status
Simulation time	52901655 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:03 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	209808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142326738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.1142326738
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.1316014967
Short name	T605
Test name
Test status
Simulation time	42938068 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:02 AM UTC 24
Finished	Sep 01 06:22:04 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316014967 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1316014967
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.2050037563
Short name	T627
Test name
Test status
Simulation time	863062507 ps
CPU time	3.2 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:10 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050037563 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.2050037563
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.559906273
Short name	T598
Test name
Test status
Simulation time	22636162 ps
CPU time	0.83 seconds
Started	Sep 01 06:21:59 AM UTC 24
Finished	Sep 01 06:22:02 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559906273 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.559906273
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.4262174042
Short name	T684
Test name
Test status
Simulation time	2317952035 ps
CPU time	16.37 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262174042 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.4262174042
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.241506748
Short name	T836
Test name
Test status
Simulation time	13287478519 ps
CPU time	73.41 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:23:21 AM UTC 24
Peak memory	226344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241506748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.241506748
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.1540840317
Short name	T607
Test name
Test status
Simulation time	38722564 ps
CPU time	0.99 seconds
Started	Sep 01 06:22:02 AM UTC 24
Finished	Sep 01 06:22:04 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540840317 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1540840317
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.1451303995
Short name	T629
Test name
Test status
Simulation time	13788942 ps
CPU time	0.72 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:11 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451303995 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.1451303995
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1589331119
Short name	T642
Test name
Test status
Simulation time	78718921 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:13 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589331119 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.1589331119
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.1408216515
Short name	T630
Test name
Test status
Simulation time	14410421 ps
CPU time	0.68 seconds
Started	Sep 01 06:22:07 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408216515 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1408216515
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.2760677396
Short name	T649
Test name
Test status
Simulation time	21532010 ps
CPU time	0.75 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:16 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760677396 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.2760677396
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.746611978
Short name	T609
Test name
Test status
Simulation time	22240891 ps
CPU time	0.74 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:07 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746611978 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.746611978
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.1741749819
Short name	T644
Test name
Test status
Simulation time	1038854015 ps
CPU time	8.13 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:14 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741749819 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1741749819
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.258800303
Short name	T777
Test name
Test status
Simulation time	855841979 ps
CPU time	6.62 seconds
Started	Sep 01 06:22:06 AM UTC 24
Finished	Sep 01 06:22:44 AM UTC 24
Peak memory	210288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258800303 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.258800303
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.879359196
Short name	T643
Test name
Test status
Simulation time	89161716 ps
CPU time	1.1 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:14 AM UTC 24
Peak memory	210004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879359196 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.879359196
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.4266610541
Short name	T640
Test name
Test status
Simulation time	28371878 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266610541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.4266610541
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3129076869
Short name	T641
Test name
Test status
Simulation time	20210053 ps
CPU time	0.96 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:13 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129076869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.3129076869
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.1102983021
Short name	T755
Test name
Test status
Simulation time	23717124 ps
CPU time	0.81 seconds
Started	Sep 01 06:22:06 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	209768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102983021 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1102983021
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.786468596
Short name	T646
Test name
Test status
Simulation time	591356905 ps
CPU time	3.01 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:16 AM UTC 24
Peak memory	210304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786468596 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.786468596
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.2149839448
Short name	T667
Test name
Test status
Simulation time	45871324 ps
CPU time	0.9 seconds
Started	Sep 01 06:22:05 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	209960 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149839448 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2149839448
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.1655766475
Short name	T647
Test name
Test status
Simulation time	591193930 ps
CPU time	3.13 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:16 AM UTC 24
Peak memory	210060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655766475 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1655766475
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.1497081780
Short name	T709
Test name
Test status
Simulation time	1820124606 ps
CPU time	15.74 seconds
Started	Sep 01 06:22:08 AM UTC 24
Finished	Sep 01 06:22:29 AM UTC 24
Peak memory	227176 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497081780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.1497081780
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.215228249
Short name	T636
Test name
Test status
Simulation time	101693998 ps
CPU time	1.11 seconds
Started	Sep 01 06:22:07 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	210064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215228249 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.215228249
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.3800065990
Short name	T648
Test name
Test status
Simulation time	37821169 ps
CPU time	0.83 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:16 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800065990 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.3800065990
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.2244991042
Short name	T761
Test name
Test status
Simulation time	30164914 ps
CPU time	0.97 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:39 AM UTC 24
Peak memory	210060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244991042 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.2244991042
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.1552378000
Short name	T637
Test name
Test status
Simulation time	15252322 ps
CPU time	0.66 seconds
Started	Sep 01 06:22:10 AM UTC 24
Finished	Sep 01 06:22:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552378000 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1552378000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.903598051
Short name	T759
Test name
Test status
Simulation time	24407681 ps
CPU time	0.88 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:39 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=903598051 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.903598051
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.1891312723
Short name	T651
Test name
Test status
Simulation time	36605987 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891312723 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1891312723
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.1040314631
Short name	T665
Test name
Test status
Simulation time	196938104 ps
CPU time	2.06 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040314631 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1040314631
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.42106479
Short name	T670
Test name
Test status
Simulation time	880905075 ps
CPU time	3.97 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:20 AM UTC 24
Peak memory	210400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42106479 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.42106479
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.3392697021
Short name	T639
Test name
Test status
Simulation time	117441421 ps
CPU time	1.15 seconds
Started	Sep 01 06:22:11 AM UTC 24
Finished	Sep 01 06:22:13 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392697021 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.3392697021
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.3573360181
Short name	T655
Test name
Test status
Simulation time	40302348 ps
CPU time	0.76 seconds
Started	Sep 01 06:22:12 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573360181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.3573360181
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.79860591
Short name	T656
Test name
Test status
Simulation time	36978395 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:12 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79860591 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.79860591
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.1838629817
Short name	T653
Test name
Test status
Simulation time	46346961 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838629817 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1838629817
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.30219033
Short name	T710
Test name
Test status
Simulation time	129357280 ps
CPU time	1.11 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:29 AM UTC 24
Peak memory	209912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30219033 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.30219033
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.3675751918
Short name	T652
Test name
Test status
Simulation time	26163122 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675751918 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3675751918
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.3491636412
Short name	T783
Test name
Test status
Simulation time	4885339318 ps
CPU time	25.25 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:47 AM UTC 24
Peak memory	211092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491636412 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.3491636412
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.1626752241
Short name	T764
Test name
Test status
Simulation time	2259073131 ps
CPU time	19.03 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:40 AM UTC 24
Peak memory	227456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626752241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.1626752241
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.1010494500
Short name	T635
Test name
Test status
Simulation time	308986285 ps
CPU time	1.52 seconds
Started	Sep 01 06:22:09 AM UTC 24
Finished	Sep 01 06:22:12 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010494500 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1010494500
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.4089346795
Short name	T213
Test name
Test status
Simulation time	25041988 ps
CPU time	1.25 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	209980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089346795 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.4089346795
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.762532766
Short name	T198
Test name
Test status
Simulation time	17481038 ps
CPU time	1.15 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762532766 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.762532766
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.825782193
Short name	T219
Test name
Test status
Simulation time	14379850 ps
CPU time	0.98 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825782193 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.825782193
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.562918601
Short name	T207
Test name
Test status
Simulation time	18479715 ps
CPU time	1.32 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:19:53 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562918601 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.562918601
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.2730779443
Short name	T36
Test name
Test status
Simulation time	482063545 ps
CPU time	3.88 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:59 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730779443 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2730779443
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.1555956164
Short name	T75
Test name
Test status
Simulation time	993347744 ps
CPU time	8.75 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	210528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555956164 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.1555956164
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3416669873
Short name	T217
Test name
Test status
Simulation time	32099040 ps
CPU time	1.08 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416669873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.3416669873
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1814857756
Short name	T218
Test name
Test status
Simulation time	45927518 ps
CPU time	1.33 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814857756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.1814857756
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.3601358717
Short name	T216
Test name
Test status
Simulation time	27097056 ps
CPU time	1.22 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601358717 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3601358717
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.2840407661
Short name	T111
Test name
Test status
Simulation time	644066018 ps
CPU time	4.27 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:03 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840407661 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2840407661
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.4206135864
Short name	T81
Test name
Test status
Simulation time	680698247 ps
CPU time	4.92 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	241624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206135864 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.4206135864
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.393225071
Short name	T156
Test name
Test status
Simulation time	28906222 ps
CPU time	1.29 seconds
Started	Sep 01 06:19:51 AM UTC 24
Finished	Sep 01 06:19:53 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393225071 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.393225071
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.2116858782
Short name	T263
Test name
Test status
Simulation time	2961974545 ps
CPU time	26.34 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:25 AM UTC 24
Peak memory	210924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116858782 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.2116858782
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.3163685018
Short name	T79
Test name
Test status
Simulation time	1283218745 ps
CPU time	25.93 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:25 AM UTC 24
Peak memory	226380 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163685018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.3163685018
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.3351736497
Short name	T215
Test name
Test status
Simulation time	20592436 ps
CPU time	1.08 seconds
Started	Sep 01 06:19:54 AM UTC 24
Finished	Sep 01 06:19:56 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351736497 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3351736497
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.4068798778
Short name	T687
Test name
Test status
Simulation time	30876033 ps
CPU time	1.06 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	209912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068798778 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.4068798778
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1173976517
Short name	T669
Test name
Test status
Simulation time	43025431 ps
CPU time	0.92 seconds
Started	Sep 01 06:22:16 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173976517 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.1173976517
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.2750648487
Short name	T660
Test name
Test status
Simulation time	40442402 ps
CPU time	0.81 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750648487 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.2750648487
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.3437569255
Short name	T756
Test name
Test status
Simulation time	48742144 ps
CPU time	0.93 seconds
Started	Sep 01 06:22:16 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	209904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437569255 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.3437569255
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.1870002752
Short name	T680
Test name
Test status
Simulation time	39662034 ps
CPU time	1.01 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870002752 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1870002752
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.3204394797
Short name	T708
Test name
Test status
Simulation time	1284099189 ps
CPU time	7.48 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:28 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204394797 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.3204394797
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.3696733085
Short name	T697
Test name
Test status
Simulation time	1924700012 ps
CPU time	8.01 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:25 AM UTC 24
Peak memory	210356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696733085 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.3696733085
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.2454581502
Short name	T654
Test name
Test status
Simulation time	28640161 ps
CPU time	0.99 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454581502 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.2454581502
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.618310987
Short name	T650
Test name
Test status
Simulation time	23118127 ps
CPU time	0.73 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:17 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618310987 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.618310987
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3915551460
Short name	T661
Test name
Test status
Simulation time	18404049 ps
CPU time	0.75 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915551460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.3915551460
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.1123659937
Short name	T668
Test name
Test status
Simulation time	71205950 ps
CPU time	0.98 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	209968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123659937 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.1123659937
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.3851980558
Short name	T696
Test name
Test status
Simulation time	422325949 ps
CPU time	2.78 seconds
Started	Sep 01 06:22:17 AM UTC 24
Finished	Sep 01 06:22:25 AM UTC 24
Peak memory	210492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851980558 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3851980558
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.2142048304
Short name	T676
Test name
Test status
Simulation time	49006341 ps
CPU time	0.84 seconds
Started	Sep 01 06:22:13 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142048304 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2142048304
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.3833831724
Short name	T688
Test name
Test status
Simulation time	45673485 ps
CPU time	1.34 seconds
Started	Sep 01 06:22:17 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	209980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833831724 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.3833831724
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.3733305705
Short name	T826
Test name
Test status
Simulation time	4674055094 ps
CPU time	37.88 seconds
Started	Sep 01 06:22:17 AM UTC 24
Finished	Sep 01 06:23:00 AM UTC 24
Peak memory	227312 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733305705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3733305705
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.3725530024
Short name	T658
Test name
Test status
Simulation time	35729326 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:15 AM UTC 24
Finished	Sep 01 06:22:18 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725530024 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3725530024
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.1620864841
Short name	T672
Test name
Test status
Simulation time	19881177 ps
CPU time	0.75 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:22 AM UTC 24
Peak memory	210136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620864841 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.1620864841
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.56429151
Short name	T618
Test name
Test status
Simulation time	19846117 ps
CPU time	0.91 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56429151 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.56429151
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.879210645
Short name	T690
Test name
Test status
Simulation time	34911265 ps
CPU time	0.84 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	208604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879210645 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.879210645
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.2514434121
Short name	T674
Test name
Test status
Simulation time	42585847 ps
CPU time	0.88 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514434121 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.2514434121
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.2478219920
Short name	T685
Test name
Test status
Simulation time	21149842 ps
CPU time	0.96 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	208816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478219920 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2478219920
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.1227527314
Short name	T743
Test name
Test status
Simulation time	2491669304 ps
CPU time	13.93 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227527314 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1227527314
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.749945869
Short name	T713
Test name
Test status
Simulation time	1707374253 ps
CPU time	7.75 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:30 AM UTC 24
Peak memory	209160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749945869 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.749945869
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.1721486723
Short name	T615
Test name
Test status
Simulation time	57725019 ps
CPU time	0.94 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721486723 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.1721486723
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2477231870
Short name	T692
Test name
Test status
Simulation time	28194961 ps
CPU time	0.98 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477231870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.2477231870
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2237118582
Short name	T693
Test name
Test status
Simulation time	106864598 ps
CPU time	1.16 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	209716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237118582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.2237118582
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.1530356320
Short name	T686
Test name
Test status
Simulation time	39199377 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530356320 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1530356320
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.428255561
Short name	T694
Test name
Test status
Simulation time	465746253 ps
CPU time	2.96 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428255561 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.428255561
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.4085068000
Short name	T681
Test name
Test status
Simulation time	24228949 ps
CPU time	0.95 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085068000 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.4085068000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.1781737129
Short name	T737
Test name
Test status
Simulation time	2374237979 ps
CPU time	13.38 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:35 AM UTC 24
Peak memory	210792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781737129 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.1781737129
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.2987820990
Short name	T841
Test name
Test status
Simulation time	13617871637 ps
CPU time	78.43 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:23:41 AM UTC 24
Peak memory	220280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987820990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.2987820990
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.2270148395
Short name	T691
Test name
Test status
Simulation time	118100060 ps
CPU time	1.32 seconds
Started	Sep 01 06:22:18 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270148395 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2270148395
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.2293257821
Short name	T715
Test name
Test status
Simulation time	14185475 ps
CPU time	0.76 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:22:31 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293257821 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.2293257821
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2070106653
Short name	T137
Test name
Test status
Simulation time	85044876 ps
CPU time	1.38 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070106653 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.2070106653
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.676760800
Short name	T675
Test name
Test status
Simulation time	15396787 ps
CPU time	0.68 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676760800 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.676760800
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.1431143372
Short name	T721
Test name
Test status
Simulation time	19851503 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431143372 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.1431143372
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.1141386788
Short name	T677
Test name
Test status
Simulation time	17277568 ps
CPU time	0.9 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210120 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141386788 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1141386788
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.2018455833
Short name	T689
Test name
Test status
Simulation time	233770910 ps
CPU time	1.73 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	209920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018455833 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.2018455833
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.806360800
Short name	T736
Test name
Test status
Simulation time	2427943500 ps
CPU time	12.93 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:35 AM UTC 24
Peak memory	210928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=806360800 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.806360800
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.2163890601
Short name	T682
Test name
Test status
Simulation time	71573425 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163890601 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.2163890601
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.200975489
Short name	T695
Test name
Test status
Simulation time	28737556 ps
CPU time	0.71 seconds
Started	Sep 01 06:22:22 AM UTC 24
Finished	Sep 01 06:22:24 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200975489 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.200975489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1368834474
Short name	T683
Test name
Test status
Simulation time	77597746 ps
CPU time	0.97 seconds
Started	Sep 01 06:22:21 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368834474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.1368834474
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.284908270
Short name	T679
Test name
Test status
Simulation time	23510129 ps
CPU time	0.95 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284908270 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.284908270
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.3134153705
Short name	T742
Test name
Test status
Simulation time	1283168988 ps
CPU time	5.51 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:22:36 AM UTC 24
Peak memory	210772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134153705 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3134153705
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.77167149
Short name	T673
Test name
Test status
Simulation time	37676885 ps
CPU time	0.78 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	209972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77167149 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.77167149
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.769148170
Short name	T831
Test name
Test status
Simulation time	10641232969 ps
CPU time	41.12 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:23:09 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769148170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.769148170
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.4149556878
Short name	T833
Test name
Test status
Simulation time	2833094089 ps
CPU time	47.12 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:23:13 AM UTC 24
Peak memory	227240 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149556878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.4149556878
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.1323249928
Short name	T678
Test name
Test status
Simulation time	27868138 ps
CPU time	0.91 seconds
Started	Sep 01 06:22:19 AM UTC 24
Finished	Sep 01 06:22:23 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323249928 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1323249928
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.1355208727
Short name	T701
Test name
Test status
Simulation time	44346397 ps
CPU time	0.8 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:27 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355208727 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.1355208727
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.52172609
Short name	T706
Test name
Test status
Simulation time	40579122 ps
CPU time	0.87 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:28 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52172609 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.52172609
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.284996741
Short name	T699
Test name
Test status
Simulation time	14708199 ps
CPU time	0.68 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:27 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284996741 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.284996741
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.735452121
Short name	T757
Test name
Test status
Simulation time	52968322 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	209980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735452121 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.735452121
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.2240266876
Short name	T704
Test name
Test status
Simulation time	18590553 ps
CPU time	0.79 seconds
Started	Sep 01 06:22:24 AM UTC 24
Finished	Sep 01 06:22:28 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240266876 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2240266876
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.1056766453
Short name	T712
Test name
Test status
Simulation time	442399066 ps
CPU time	3.97 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:30 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056766453 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1056766453
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.1115126784
Short name	T739
Test name
Test status
Simulation time	2070097546 ps
CPU time	8.72 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:36 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115126784 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.1115126784
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.3334452137
Short name	T762
Test name
Test status
Simulation time	65880571 ps
CPU time	1.14 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:39 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334452137 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.3334452137
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.911216242
Short name	T707
Test name
Test status
Simulation time	18882728 ps
CPU time	0.84 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:28 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911216242 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.911216242
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3289773369
Short name	T760
Test name
Test status
Simulation time	56842184 ps
CPU time	1.13 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:39 AM UTC 24
Peak memory	209668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289773369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.3289773369
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.619744737
Short name	T705
Test name
Test status
Simulation time	93830550 ps
CPU time	0.98 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:28 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619744737 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.619744737
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.227274885
Short name	T8
Test name
Test status
Simulation time	972324173 ps
CPU time	5.49 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227274885 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.227274885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.290429489
Short name	T726
Test name
Test status
Simulation time	42261763 ps
CPU time	0.93 seconds
Started	Sep 01 06:22:23 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	208616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290429489 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.290429489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.3404817375
Short name	T830
Test name
Test status
Simulation time	5570555729 ps
CPU time	41.64 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:23:08 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404817375 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.3404817375
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.1144348744
Short name	T845
Test name
Test status
Simulation time	19005294090 ps
CPU time	109.12 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:24:16 AM UTC 24
Peak memory	224388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144348744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1144348744
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.3672135964
Short name	T700
Test name
Test status
Simulation time	23544334 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:27 AM UTC 24
Peak memory	209968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672135964 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.3672135964
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.2380536082
Short name	T714
Test name
Test status
Simulation time	20163037 ps
CPU time	0.75 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:31 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380536082 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.2380536082
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.745292668
Short name	T723
Test name
Test status
Simulation time	20804292 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:27 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745292668 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.745292668
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.346290534
Short name	T711
Test name
Test status
Simulation time	47741980 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:26 AM UTC 24
Finished	Sep 01 06:22:29 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346290534 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.346290534
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.2701917238
Short name	T733
Test name
Test status
Simulation time	79953593 ps
CPU time	1.05 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:34 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701917238 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.2701917238
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.762224702
Short name	T703
Test name
Test status
Simulation time	74030440 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:27 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762224702 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.762224702
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.4204877396
Short name	T738
Test name
Test status
Simulation time	1852628124 ps
CPU time	8.33 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:35 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204877396 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.4204877396
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.262353037
Short name	T740
Test name
Test status
Simulation time	1580299498 ps
CPU time	8.1 seconds
Started	Sep 01 06:22:26 AM UTC 24
Finished	Sep 01 06:22:36 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262353037 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.262353037
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.768863136
Short name	T727
Test name
Test status
Simulation time	32933532 ps
CPU time	1.25 seconds
Started	Sep 01 06:22:27 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768863136 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.768863136
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.581855524
Short name	T725
Test name
Test status
Simulation time	54731653 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:27 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	208788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581855524 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.581855524
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1558045932
Short name	T724
Test name
Test status
Simulation time	18296539 ps
CPU time	0.88 seconds
Started	Sep 01 06:22:27 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558045932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.1558045932
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.2360062467
Short name	T718
Test name
Test status
Simulation time	11910601 ps
CPU time	0.72 seconds
Started	Sep 01 06:22:26 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360062467 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2360062467
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.863242553
Short name	T734
Test name
Test status
Simulation time	248426332 ps
CPU time	1.32 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:34 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863242553 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.863242553
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.2027610800
Short name	T702
Test name
Test status
Simulation time	38395497 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:25 AM UTC 24
Finished	Sep 01 06:22:27 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027610800 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2027610800
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.2828314720
Short name	T819
Test name
Test status
Simulation time	4659104006 ps
CPU time	20.87 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:54 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828314720 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.2828314720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.3034193222
Short name	T796
Test name
Test status
Simulation time	1225912262 ps
CPU time	16.57 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:50 AM UTC 24
Peak memory	220168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034193222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.3034193222
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.4284268695
Short name	T719
Test name
Test status
Simulation time	56172251 ps
CPU time	0.84 seconds
Started	Sep 01 06:22:26 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284268695 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.4284268695
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.1856566023
Short name	T758
Test name
Test status
Simulation time	99559637 ps
CPU time	0.88 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856566023 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.1856566023
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2176820704
Short name	T138
Test name
Test status
Simulation time	30120261 ps
CPU time	0.91 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176820704 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.2176820704
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.1266290607
Short name	T730
Test name
Test status
Simulation time	16634106 ps
CPU time	0.66 seconds
Started	Sep 01 06:22:31 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266290607 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1266290607
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.85958790
Short name	T753
Test name
Test status
Simulation time	51172128 ps
CPU time	0.91 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85958790 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.85958790
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.1644509863
Short name	T735
Test name
Test status
Simulation time	87503870 ps
CPU time	0.99 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:34 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644509863 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1644509863
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.972784002
Short name	T728
Test name
Test status
Simulation time	205467604 ps
CPU time	1.8 seconds
Started	Sep 01 06:22:30 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972784002 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.972784002
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.636968806
Short name	T745
Test name
Test status
Simulation time	1294450484 ps
CPU time	5.39 seconds
Started	Sep 01 06:22:30 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636968806 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.636968806
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.1518164943
Short name	T732
Test name
Test status
Simulation time	155514395 ps
CPU time	1.29 seconds
Started	Sep 01 06:22:31 AM UTC 24
Finished	Sep 01 06:22:34 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518164943 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.1518164943
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.881112906
Short name	T754
Test name
Test status
Simulation time	14566233 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881112906 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.881112906
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.2218534568
Short name	T731
Test name
Test status
Simulation time	30254908 ps
CPU time	0.92 seconds
Started	Sep 01 06:22:31 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218534568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.2218534568
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.3881325872
Short name	T722
Test name
Test status
Simulation time	95230310 ps
CPU time	1.02 seconds
Started	Sep 01 06:22:30 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881325872 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.3881325872
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.3769777318
Short name	T773
Test name
Test status
Simulation time	914697445 ps
CPU time	5.34 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769777318 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3769777318
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.2193825801
Short name	T720
Test name
Test status
Simulation time	18062072 ps
CPU time	0.81 seconds
Started	Sep 01 06:22:29 AM UTC 24
Finished	Sep 01 06:22:32 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193825801 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2193825801
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.1018597717
Short name	T787
Test name
Test status
Simulation time	1258012704 ps
CPU time	10.27 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	210784 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018597717 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.1018597717
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.3281428999
Short name	T839
Test name
Test status
Simulation time	5610053594 ps
CPU time	49.2 seconds
Started	Sep 01 06:22:32 AM UTC 24
Finished	Sep 01 06:23:27 AM UTC 24
Peak memory	220548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281428999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3281428999
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.1759598363
Short name	T729
Test name
Test status
Simulation time	22204648 ps
CPU time	0.78 seconds
Started	Sep 01 06:22:31 AM UTC 24
Finished	Sep 01 06:22:33 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759598363 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1759598363
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.3725420983
Short name	T751
Test name
Test status
Simulation time	15888299 ps
CPU time	0.7 seconds
Started	Sep 01 06:22:35 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725420983 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.3725420983
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1490093670
Short name	T746
Test name
Test status
Simulation time	13419653 ps
CPU time	0.67 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490093670 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1490093670
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.1022705363
Short name	T744
Test name
Test status
Simulation time	19434024 ps
CPU time	0.71 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	209056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022705363 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1022705363
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.539260217
Short name	T748
Test name
Test status
Simulation time	27055001 ps
CPU time	0.82 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539260217 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.539260217
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.3845087018
Short name	T794
Test name
Test status
Simulation time	71403134 ps
CPU time	1.38 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:49 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845087018 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3845087018
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.767995887
Short name	T824
Test name
Test status
Simulation time	2068903721 ps
CPU time	9.67 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	210716 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767995887 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.767995887
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.1161572853
Short name	T778
Test name
Test status
Simulation time	1943326229 ps
CPU time	9.62 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:46 AM UTC 24
Peak memory	210332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161572853 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.1161572853
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.3868611114
Short name	T750
Test name
Test status
Simulation time	80956624 ps
CPU time	1 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868611114 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.3868611114
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3619022795
Short name	T747
Test name
Test status
Simulation time	34409764 ps
CPU time	0.87 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:37 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619022795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.3619022795
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3110326996
Short name	T752
Test name
Test status
Simulation time	347780387 ps
CPU time	1.77 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:38 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110326996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.3110326996
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.2062259787
Short name	T792
Test name
Test status
Simulation time	42507704 ps
CPU time	0.86 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:49 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062259787 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2062259787
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.763776241
Short name	T763
Test name
Test status
Simulation time	832937223 ps
CPU time	3.21 seconds
Started	Sep 01 06:22:35 AM UTC 24
Finished	Sep 01 06:22:39 AM UTC 24
Peak memory	209952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763776241 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.763776241
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.1934683021
Short name	T771
Test name
Test status
Simulation time	20714058 ps
CPU time	0.9 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934683021 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.1934683021
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.457803348
Short name	T828
Test name
Test status
Simulation time	6570504929 ps
CPU time	25.93 seconds
Started	Sep 01 06:22:35 AM UTC 24
Finished	Sep 01 06:23:03 AM UTC 24
Peak memory	210796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457803348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.457803348
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.2389890276
Short name	T837
Test name
Test status
Simulation time	8112477065 ps
CPU time	45.22 seconds
Started	Sep 01 06:22:35 AM UTC 24
Finished	Sep 01 06:23:22 AM UTC 24
Peak memory	223596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389890276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2389890276
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.3952230466
Short name	T793
Test name
Test status
Simulation time	107654623 ps
CPU time	1.15 seconds
Started	Sep 01 06:22:34 AM UTC 24
Finished	Sep 01 06:22:49 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952230466 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3952230466
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.526971742
Short name	T772
Test name
Test status
Simulation time	15932475 ps
CPU time	0.88 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526971742 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.526971742
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3149911084
Short name	T811
Test name
Test status
Simulation time	22417322 ps
CPU time	0.93 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149911084 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.3149911084
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.1723208524
Short name	T810
Test name
Test status
Simulation time	52112659 ps
CPU time	0.9 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	209252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723208524 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1723208524
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.922555489
Short name	T815
Test name
Test status
Simulation time	112654865 ps
CPU time	1.15 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922555489 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.922555489
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.370931847
Short name	T766
Test name
Test status
Simulation time	31497673 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:36 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370931847 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.370931847
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.1354773132
Short name	T800
Test name
Test status
Simulation time	1642546830 ps
CPU time	9.58 seconds
Started	Sep 01 06:22:36 AM UTC 24
Finished	Sep 01 06:22:51 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354773132 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1354773132
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1682032693
Short name	T823
Test name
Test status
Simulation time	2178355649 ps
CPU time	16.19 seconds
Started	Sep 01 06:22:36 AM UTC 24
Finished	Sep 01 06:22:57 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682032693 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.1682032693
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.54767945
Short name	T816
Test name
Test status
Simulation time	53801518 ps
CPU time	1.2 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54767945 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.54767945
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.213438582
Short name	T813
Test name
Test status
Simulation time	37963671 ps
CPU time	1.12 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213438582 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.213438582
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3778703847
Short name	T812
Test name
Test status
Simulation time	71139053 ps
CPU time	1.01 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778703847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.3778703847
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.4261738885
Short name	T765
Test name
Test status
Simulation time	34141561 ps
CPU time	0.7 seconds
Started	Sep 01 06:22:36 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261738885 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.4261738885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.619232146
Short name	T799
Test name
Test status
Simulation time	1291103106 ps
CPU time	4.63 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:22:50 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619232146 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.619232146
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.1999900587
Short name	T767
Test name
Test status
Simulation time	72056351 ps
CPU time	0.93 seconds
Started	Sep 01 06:22:36 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999900587 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1999900587
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.2258904626
Short name	T840
Test name
Test status
Simulation time	8515484779 ps
CPU time	43.55 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:23:30 AM UTC 24
Peak memory	210936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258904626 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.2258904626
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.4291693972
Short name	T838
Test name
Test status
Simulation time	4349965764 ps
CPU time	37.4 seconds
Started	Sep 01 06:22:38 AM UTC 24
Finished	Sep 01 06:23:24 AM UTC 24
Peak memory	224424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291693972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.4291693972
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.4196938420
Short name	T814
Test name
Test status
Simulation time	18939874 ps
CPU time	0.98 seconds
Started	Sep 01 06:22:37 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196938420 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.4196938420
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.1395244789
Short name	T784
Test name
Test status
Simulation time	16257185 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395244789 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.1395244789
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3547257709
Short name	T808
Test name
Test status
Simulation time	44973127 ps
CPU time	1.04 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547257709 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.3547257709
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.908181799
Short name	T803
Test name
Test status
Simulation time	19465970 ps
CPU time	0.81 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:52 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908181799 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.908181799
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.3529296719
Short name	T807
Test name
Test status
Simulation time	39447664 ps
CPU time	0.85 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529296719 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.3529296719
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.390358074
Short name	T775
Test name
Test status
Simulation time	24613898 ps
CPU time	0.98 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390358074 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.390358074
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.2260071578
Short name	T797
Test name
Test status
Simulation time	1034083668 ps
CPU time	8.63 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:50 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260071578 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.2260071578
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.569332781
Short name	T795
Test name
Test status
Simulation time	1457980098 ps
CPU time	8.17 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:50 AM UTC 24
Peak memory	210388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569332781 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.569332781
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.431625418
Short name	T804
Test name
Test status
Simulation time	26172349 ps
CPU time	0.94 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:52 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431625418 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.431625418
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3396790923
Short name	T809
Test name
Test status
Simulation time	20532330 ps
CPU time	1.03 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396790923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.3396790923
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.3711610951
Short name	T806
Test name
Test status
Simulation time	56282489 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711610951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.3711610951
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.361695951
Short name	T802
Test name
Test status
Simulation time	25698951 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:52 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361695951 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.361695951
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.1113226885
Short name	T821
Test name
Test status
Simulation time	757047860 ps
CPU time	3.68 seconds
Started	Sep 01 06:22:40 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113226885 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1113226885
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.2075809511
Short name	T774
Test name
Test status
Simulation time	51818601 ps
CPU time	0.94 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:42 AM UTC 24
Peak memory	208704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075809511 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2075809511
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.810645933
Short name	T835
Test name
Test status
Simulation time	4407722628 ps
CPU time	33.1 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:23:20 AM UTC 24
Peak memory	211000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810645933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.810645933
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.4159695688
Short name	T834
Test name
Test status
Simulation time	2603826243 ps
CPU time	21.71 seconds
Started	Sep 01 06:22:40 AM UTC 24
Finished	Sep 01 06:23:14 AM UTC 24
Peak memory	220328 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159695688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.4159695688
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.3552606741
Short name	T805
Test name
Test status
Simulation time	81871319 ps
CPU time	1.05 seconds
Started	Sep 01 06:22:39 AM UTC 24
Finished	Sep 01 06:22:52 AM UTC 24
Peak memory	210088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552606741 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3552606741
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.3792091852
Short name	T818
Test name
Test status
Simulation time	14150616 ps
CPU time	0.79 seconds
Started	Sep 01 06:22:48 AM UTC 24
Finished	Sep 01 06:22:53 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792091852 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.3792091852
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2072985697
Short name	T782
Test name
Test status
Simulation time	68491627 ps
CPU time	0.89 seconds
Started	Sep 01 06:22:45 AM UTC 24
Finished	Sep 01 06:22:47 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072985697 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.2072985697
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.2785168048
Short name	T790
Test name
Test status
Simulation time	16591717 ps
CPU time	0.92 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785168048 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2785168048
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.3287970877
Short name	T791
Test name
Test status
Simulation time	45940677 ps
CPU time	0.97 seconds
Started	Sep 01 06:22:46 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3287970877 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.3287970877
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.4289602365
Short name	T785
Test name
Test status
Simulation time	22190331 ps
CPU time	0.79 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289602365 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.4289602365
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.3693515052
Short name	T820
Test name
Test status
Simulation time	918404250 ps
CPU time	7.79 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:55 AM UTC 24
Peak memory	210560 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693515052 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3693515052
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.4055627483
Short name	T827
Test name
Test status
Simulation time	1696662374 ps
CPU time	13.45 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:23:01 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055627483 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.4055627483
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.3696297633
Short name	T781
Test name
Test status
Simulation time	29247429 ps
CPU time	0.92 seconds
Started	Sep 01 06:22:44 AM UTC 24
Finished	Sep 01 06:22:47 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696297633 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.3696297633
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.4037982890
Short name	T780
Test name
Test status
Simulation time	16147188 ps
CPU time	0.77 seconds
Started	Sep 01 06:22:44 AM UTC 24
Finished	Sep 01 06:22:47 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037982890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.4037982890
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.372330086
Short name	T779
Test name
Test status
Simulation time	22430328 ps
CPU time	0.76 seconds
Started	Sep 01 06:22:44 AM UTC 24
Finished	Sep 01 06:22:47 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372330086 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.372330086
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.640591095
Short name	T786
Test name
Test status
Simulation time	39460265 ps
CPU time	0.76 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640591095 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.640591095
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.3919510456
Short name	T825
Test name
Test status
Simulation time	1293508961 ps
CPU time	7 seconds
Started	Sep 01 06:22:47 AM UTC 24
Finished	Sep 01 06:22:58 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919510456 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3919510456
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.2700080257
Short name	T788
Test name
Test status
Simulation time	37028307 ps
CPU time	1.03 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	209872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700080257 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2700080257
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.2563642144
Short name	T822
Test name
Test status
Simulation time	513022865 ps
CPU time	3.15 seconds
Started	Sep 01 06:22:48 AM UTC 24
Finished	Sep 01 06:22:56 AM UTC 24
Peak memory	210528 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563642144 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.2563642144
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.1082830191
Short name	T844
Test name
Test status
Simulation time	6862970326 ps
CPU time	60.74 seconds
Started	Sep 01 06:22:47 AM UTC 24
Finished	Sep 01 06:23:53 AM UTC 24
Peak memory	224304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082830191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.1082830191
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.3438610719
Short name	T789
Test name
Test status
Simulation time	68929606 ps
CPU time	0.99 seconds
Started	Sep 01 06:22:43 AM UTC 24
Finished	Sep 01 06:22:48 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438610719 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3438610719
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.3328008686
Short name	T223
Test name
Test status
Simulation time	13542839 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328008686 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.3328008686
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.4238429823
Short name	T129
Test name
Test status
Simulation time	24732818 ps
CPU time	1.35 seconds
Started	Sep 01 06:20:00 AM UTC 24
Finished	Sep 01 06:20:02 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238429823 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.4238429823
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.1362748591
Short name	T125
Test name
Test status
Simulation time	25460456 ps
CPU time	1.11 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362748591 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1362748591
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.8475309
Short name	T220
Test name
Test status
Simulation time	35563887 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8475309 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.8475309
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.2414486346
Short name	T178
Test name
Test status
Simulation time	26714035 ps
CPU time	1.05 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414486346 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2414486346
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.2005291258
Short name	T14
Test name
Test status
Simulation time	825939240 ps
CPU time	6.01 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:05 AM UTC 24
Peak memory	210552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005291258 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2005291258
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.718884000
Short name	T248
Test name
Test status
Simulation time	1815441032 ps
CPU time	15.94 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:15 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718884000 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.718884000
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.2813631804
Short name	T212
Test name
Test status
Simulation time	127341621 ps
CPU time	2.15 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:02 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813631804 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.2813631804
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.823580217
Short name	T127
Test name
Test status
Simulation time	19349368 ps
CPU time	0.98 seconds
Started	Sep 01 06:20:00 AM UTC 24
Finished	Sep 01 06:20:01 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823580217 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.823580217
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.607923241
Short name	T128
Test name
Test status
Simulation time	13946635 ps
CPU time	1.12 seconds
Started	Sep 01 06:19:59 AM UTC 24
Finished	Sep 01 06:20:02 AM UTC 24
Peak memory	210168 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607923241 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.607923241
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.2350584630
Short name	T124
Test name
Test status
Simulation time	16184237 ps
CPU time	1.18 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350584630 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2350584630
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.1075634903
Short name	T46
Test name
Test status
Simulation time	949989147 ps
CPU time	4.52 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:07 AM UTC 24
Peak memory	210708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075634903 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1075634903
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.3538679705
Short name	T123
Test name
Test status
Simulation time	19032060 ps
CPU time	1.24 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:00 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538679705 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3538679705
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.1072152994
Short name	T171
Test name
Test status
Simulation time	4040460827 ps
CPU time	31.63 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	210868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072152994 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.1072152994
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.1541916884
Short name	T126
Test name
Test status
Simulation time	34743286 ps
CPU time	1.55 seconds
Started	Sep 01 06:19:58 AM UTC 24
Finished	Sep 01 06:20:01 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541916884 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1541916884
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.2018571353
Short name	T228
Test name
Test status
Simulation time	107192425 ps
CPU time	1.8 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:09 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018571353 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.2018571353
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.4045700936
Short name	T131
Test name
Test status
Simulation time	31340530 ps
CPU time	1.16 seconds
Started	Sep 01 06:20:04 AM UTC 24
Finished	Sep 01 06:20:06 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045700936 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.4045700936
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.1798925097
Short name	T199
Test name
Test status
Simulation time	15724258 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:04 AM UTC 24
Finished	Sep 01 06:20:06 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798925097 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.1798925097
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.2996731404
Short name	T229
Test name
Test status
Simulation time	254885439 ps
CPU time	2.23 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:09 AM UTC 24
Peak memory	209912 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996731404 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.2996731404
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.2915508480
Short name	T222
Test name
Test status
Simulation time	26990482 ps
CPU time	1.05 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915508480 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2915508480
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.2572239753
Short name	T39
Test name
Test status
Simulation time	234813708 ps
CPU time	2.89 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:06 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572239753 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2572239753
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.653005772
Short name	T242
Test name
Test status
Simulation time	1854451130 ps
CPU time	10.27 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:14 AM UTC 24
Peak memory	210244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653005772 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.653005772
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.198514224
Short name	T43
Test name
Test status
Simulation time	93935615 ps
CPU time	1.56 seconds
Started	Sep 01 06:20:04 AM UTC 24
Finished	Sep 01 06:20:06 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198514224 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.198514224
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.1072959675
Short name	T44
Test name
Test status
Simulation time	69874006 ps
CPU time	1.57 seconds
Started	Sep 01 06:20:04 AM UTC 24
Finished	Sep 01 06:20:06 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072959675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.1072959675
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2966863390
Short name	T45
Test name
Test status
Simulation time	126164252 ps
CPU time	1.7 seconds
Started	Sep 01 06:20:04 AM UTC 24
Finished	Sep 01 06:20:06 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966863390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.2966863390
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.3860847331
Short name	T224
Test name
Test status
Simulation time	16320125 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860847331 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3860847331
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.2437451544
Short name	T230
Test name
Test status
Simulation time	234332269 ps
CPU time	3.28 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:10 AM UTC 24
Peak memory	209880 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437451544 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2437451544
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.3967671360
Short name	T221
Test name
Test status
Simulation time	49271737 ps
CPU time	1.16 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967671360 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3967671360
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.1987420077
Short name	T108
Test name
Test status
Simulation time	1247093313 ps
CPU time	12.96 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:20 AM UTC 24
Peak memory	210456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987420077 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.1987420077
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.66615728
Short name	T97
Test name
Test status
Simulation time	3164294250 ps
CPU time	54.68 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:21:02 AM UTC 24
Peak memory	220296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66615728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.66615728
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.990207882
Short name	T225
Test name
Test status
Simulation time	18774004 ps
CPU time	1.08 seconds
Started	Sep 01 06:20:02 AM UTC 24
Finished	Sep 01 06:20:04 AM UTC 24
Peak memory	209748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990207882 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.990207882
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.596451793
Short name	T231
Test name
Test status
Simulation time	16406033 ps
CPU time	1.03 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:10 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596451793 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.596451793
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.2785399344
Short name	T205
Test name
Test status
Simulation time	72066699 ps
CPU time	1.63 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:11 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785399344 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.2785399344
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.2280095927
Short name	T49
Test name
Test status
Simulation time	40500460 ps
CPU time	0.89 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:08 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280095927 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2280095927
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.3666680907
Short name	T233
Test name
Test status
Simulation time	164385659 ps
CPU time	2.12 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:11 AM UTC 24
Peak memory	210296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666680907 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.3666680907
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.1064511198
Short name	T48
Test name
Test status
Simulation time	16203764 ps
CPU time	1.1 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:08 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064511198 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1064511198
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.1647902530
Short name	T17
Test name
Test status
Simulation time	1876147981 ps
CPU time	17.79 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:25 AM UTC 24
Peak memory	210828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647902530 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1647902530
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.3188688395
Short name	T243
Test name
Test status
Simulation time	379499258 ps
CPU time	5.58 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:14 AM UTC 24
Peak memory	210400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188688395 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.3188688395
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.180355646
Short name	T226
Test name
Test status
Simulation time	25608750 ps
CPU time	1.28 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:09 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180355646 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.180355646
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2891292476
Short name	T232
Test name
Test status
Simulation time	58381799 ps
CPU time	1.37 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:10 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891292476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.2891292476
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.1095554639
Short name	T51
Test name
Test status
Simulation time	43561166 ps
CPU time	1.14 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:09 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095554639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.1095554639
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.4018701189
Short name	T227
Test name
Test status
Simulation time	113054615 ps
CPU time	1.58 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:09 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018701189 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.4018701189
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.4109857323
Short name	T252
Test name
Test status
Simulation time	1053969257 ps
CPU time	6.85 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:16 AM UTC 24
Peak memory	210772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109857323 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.4109857323
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.4273967616
Short name	T47
Test name
Test status
Simulation time	14360882 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:08 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273967616 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.4273967616
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.2898765112
Short name	T37
Test name
Test status
Simulation time	2189409878 ps
CPU time	20.06 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898765112 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.2898765112
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.664402683
Short name	T209
Test name
Test status
Simulation time	9674108774 ps
CPU time	86.04 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:21:36 AM UTC 24
Peak memory	220592 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664402683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.664402683
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.3002179171
Short name	T50
Test name
Test status
Simulation time	107823386 ps
CPU time	1.33 seconds
Started	Sep 01 06:20:06 AM UTC 24
Finished	Sep 01 06:20:09 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002179171 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.3002179171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.4018866194
Short name	T244
Test name
Test status
Simulation time	28090753 ps
CPU time	1.22 seconds
Started	Sep 01 06:20:12 AM UTC 24
Finished	Sep 01 06:20:14 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018866194 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.4018866194
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.4175725624
Short name	T132
Test name
Test status
Simulation time	46466998 ps
CPU time	1.48 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175725624 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.4175725624
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.4149914060
Short name	T200
Test name
Test status
Simulation time	16230406 ps
CPU time	1.17 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:12 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149914060 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.4149914060
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.897982337
Short name	T237
Test name
Test status
Simulation time	23793431 ps
CPU time	1.18 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897982337 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.897982337
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.3480835720
Short name	T240
Test name
Test status
Simulation time	92751754 ps
CPU time	1.82 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480835720 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3480835720
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.1648482627
Short name	T19
Test name
Test status
Simulation time	2208800059 ps
CPU time	18.14 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:29 AM UTC 24
Peak memory	210660 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648482627 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1648482627
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.2202216558
Short name	T112
Test name
Test status
Simulation time	2274983988 ps
CPU time	12.66 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:24 AM UTC 24
Peak memory	210548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202216558 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.2202216558
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.505727690
Short name	T239
Test name
Test status
Simulation time	72629023 ps
CPU time	1.54 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	208892 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505727690 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.505727690
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2296588158
Short name	T236
Test name
Test status
Simulation time	26851346 ps
CPU time	1.25 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296588158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.2296588158
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3691735252
Short name	T241
Test name
Test status
Simulation time	85996847 ps
CPU time	1.77 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691735252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.3691735252
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.1219793746
Short name	T235
Test name
Test status
Simulation time	46578419 ps
CPU time	1.33 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:12 AM UTC 24
Peak memory	210016 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219793746 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1219793746
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.2583199310
Short name	T256
Test name
Test status
Simulation time	579820808 ps
CPU time	4.55 seconds
Started	Sep 01 06:20:12 AM UTC 24
Finished	Sep 01 06:20:17 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583199310 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.2583199310
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.881327452
Short name	T234
Test name
Test status
Simulation time	131157528 ps
CPU time	1.9 seconds
Started	Sep 01 06:20:08 AM UTC 24
Finished	Sep 01 06:20:11 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881327452 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.881327452
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.3778484604
Short name	T389
Test name
Test status
Simulation time	4829494944 ps
CPU time	44.93 seconds
Started	Sep 01 06:20:12 AM UTC 24
Finished	Sep 01 06:20:58 AM UTC 24
Peak memory	210736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778484604 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.3778484604
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.226535507
Short name	T95
Test name
Test status
Simulation time	1239955287 ps
CPU time	20.65 seconds
Started	Sep 01 06:20:12 AM UTC 24
Finished	Sep 01 06:20:34 AM UTC 24
Peak memory	220212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226535507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.226535507
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.527038222
Short name	T238
Test name
Test status
Simulation time	38036689 ps
CPU time	1.5 seconds
Started	Sep 01 06:20:10 AM UTC 24
Finished	Sep 01 06:20:13 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527038222 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.527038222
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.2873783974
Short name	T102
Test name
Test status
Simulation time	28996239 ps
CPU time	1.26 seconds
Started	Sep 01 06:20:17 AM UTC 24
Finished	Sep 01 06:20:19 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873783974 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.2873783974
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2850001361
Short name	T254
Test name
Test status
Simulation time	48430715 ps
CPU time	1.41 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:20:17 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850001361 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.2850001361
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.3793240436
Short name	T247
Test name
Test status
Simulation time	11211700 ps
CPU time	0.94 seconds
Started	Sep 01 06:20:13 AM UTC 24
Finished	Sep 01 06:20:15 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793240436 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.3793240436
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.2808244171
Short name	T208
Test name
Test status
Simulation time	76544472 ps
CPU time	1.64 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:20:17 AM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808244171 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.2808244171
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.4264743509
Short name	T246
Test name
Test status
Simulation time	43093824 ps
CPU time	1.36 seconds
Started	Sep 01 06:20:12 AM UTC 24
Finished	Sep 01 06:20:14 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264743509 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.4264743509
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.728534207
Short name	T41
Test name
Test status
Simulation time	1522351861 ps
CPU time	17.58 seconds
Started	Sep 01 06:20:13 AM UTC 24
Finished	Sep 01 06:20:32 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728534207 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.728534207
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.160208903
Short name	T262
Test name
Test status
Simulation time	975380258 ps
CPU time	10.59 seconds
Started	Sep 01 06:20:13 AM UTC 24
Finished	Sep 01 06:20:25 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160208903 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.160208903
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.1899608343
Short name	T251
Test name
Test status
Simulation time	24549085 ps
CPU time	1.37 seconds
Started	Sep 01 06:20:13 AM UTC 24
Finished	Sep 01 06:20:16 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899608343 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.1899608343
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2076417092
Short name	T255
Test name
Test status
Simulation time	75292290 ps
CPU time	1.58 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:20:17 AM UTC 24
Peak memory	210068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076417092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.2076417092
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1114903544
Short name	T253
Test name
Test status
Simulation time	32235755 ps
CPU time	1.26 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:20:17 AM UTC 24
Peak memory	210124 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114903544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.1114903544
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.2092629047
Short name	T249
Test name
Test status
Simulation time	14697074 ps
CPU time	1.13 seconds
Started	Sep 01 06:20:13 AM UTC 24
Finished	Sep 01 06:20:15 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092629047 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2092629047
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.1184591891
Short name	T193
Test name
Test status
Simulation time	1055889135 ps
CPU time	7.45 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:20:23 AM UTC 24
Peak memory	210832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184591891 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1184591891
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.3735875808
Short name	T245
Test name
Test status
Simulation time	25716938 ps
CPU time	1.28 seconds
Started	Sep 01 06:20:12 AM UTC 24
Finished	Sep 01 06:20:14 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3735875808 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3735875808
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.2657600548
Short name	T452
Test name
Test status
Simulation time	6991472808 ps
CPU time	58.9 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:21:15 AM UTC 24
Peak memory	211052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657600548 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.2657600548
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.4271612167
Short name	T67
Test name
Test status
Simulation time	1195977645 ps
CPU time	18.99 seconds
Started	Sep 01 06:20:15 AM UTC 24
Finished	Sep 01 06:20:35 AM UTC 24
Peak memory	220392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271612167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.4271612167
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2864993640
Short name	T250
Test name
Test status
Simulation time	26763205 ps
CPU time	1.27 seconds
Started	Sep 01 06:20:13 AM UTC 24
Finished	Sep 01 06:20:16 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864993640 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_31/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2864993640
Directory	/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/9.clkmgr_trans/latest

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