Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	211620	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

507498

1

T4

28

T5

3

T6

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	208294	1			T4	42		T6	5		T27	15
values[0x0]	242352	1			T4	27		T5	10		T6	6
values[0x1]	268472	1			T4	12		T5	5		T6	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	147248	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

571870

1

T4

37

T5

3

T6

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2393	1			T4	1		T56	1		T10	1
valid_sources[0x01]	2224	1			T29	5		T30	6		T54	2
valid_sources[0x02]	2484	1			T56	1		T10	1		T11	1
valid_sources[0x03]	3300	1			T5	1		T27	1		T56	1
valid_sources[0x04]	3203	1			T30	4		T110	2		T11	1
valid_sources[0x05]	3275	1			T56	3		T112	1		T10	1
valid_sources[0x06]	2356	1			T31	1		T32	1		T10	3
valid_sources[0x07]	2623	1			T51	6		T10	1		T26	1
valid_sources[0x08]	2494	1			T30	1		T32	1		T56	1
valid_sources[0x09]	2542	1			T4	1		T30	4		T51	7
valid_sources[0x0a]	2682	1			T31	2		T10	1		T50	5
valid_sources[0x0b]	2601	1			T32	2		T10	2		T11	4
valid_sources[0x0c]	2354	1			T4	1		T10	3		T11	3
valid_sources[0x0d]	2790	1			T53	1		T56	3		T112	2
valid_sources[0x0e]	3660	1			T32	2		T77	3		T10	2
valid_sources[0x0f]	3096	1			T32	1		T11	2		T46	1
valid_sources[0x10]	2388	1			T11	2		T25	4		T50	3
valid_sources[0x11]	2586	1			T31	2		T54	1		T110	2
valid_sources[0x12]	3196	1			T66	2		T77	1		T11	2
valid_sources[0x13]	2591	1			T30	1		T54	1		T56	2
valid_sources[0x14]	2861	1			T30	4		T51	4		T54	1
valid_sources[0x15]	2694	1			T30	1		T67	1		T11	2
valid_sources[0x16]	2159	1			T31	1		T66	1		T10	1
valid_sources[0x17]	2813	1			T4	5		T66	1		T10	1
valid_sources[0x18]	4132	1			T112	2		T10	2		T46	2
valid_sources[0x19]	2285	1			T52	3		T10	1		T11	3
valid_sources[0x1a]	3096	1			T6	1		T51	1		T56	2
valid_sources[0x1b]	2866	1			T4	3		T32	1		T56	1
valid_sources[0x1c]	2521	1			T30	1		T10	1		T11	1
valid_sources[0x1d]	3154	1			T32	1		T77	1		T11	1
valid_sources[0x1e]	2856	1			T209	1		T10	1		T11	3
valid_sources[0x1f]	2356	1			T30	5		T54	1		T56	1
valid_sources[0x20]	2764	1			T27	3		T53	1		T67	1
valid_sources[0x21]	2681	1			T77	2		T209	1		T50	10
valid_sources[0x22]	2880	1			T4	3		T27	3		T11	1
valid_sources[0x23]	2931	1			T31	1		T54	2		T11	1
valid_sources[0x24]	3267	1			T31	2		T112	1		T171	1
valid_sources[0x25]	3474	1			T54	1		T56	1		T77	1
valid_sources[0x26]	2567	1			T30	1		T77	4		T11	1
valid_sources[0x27]	2680	1			T5	1		T31	1		T111	1
valid_sources[0x28]	3083	1			T30	2		T31	2		T32	1
valid_sources[0x29]	2678	1			T4	4		T10	1		T46	2
valid_sources[0x2a]	2499	1			T10	2		T11	1		T114	1
valid_sources[0x2b]	2308	1			T30	4		T10	1		T46	1
valid_sources[0x2c]	3101	1			T110	3		T11	1		T46	2
valid_sources[0x2d]	2671	1			T32	1		T51	3		T77	1
valid_sources[0x2e]	2495	1			T27	1		T32	1		T56	1
valid_sources[0x2f]	2386	1			T51	4		T111	2		T66	5
valid_sources[0x30]	2993	1			T30	5		T111	2		T112	1
valid_sources[0x31]	2508	1			T27	2		T32	1		T54	1
valid_sources[0x32]	2995	1			T10	3		T11	2		T46	1
valid_sources[0x33]	3042	1			T52	1		T20	81		T10	1
valid_sources[0x34]	2288	1			T56	2		T77	2		T10	2
valid_sources[0x35]	2799	1			T53	1		T56	1		T112	1
valid_sources[0x36]	2767	1			T4	3		T31	1		T53	1
valid_sources[0x37]	2399	1			T5	1		T30	4		T11	3
valid_sources[0x38]	2511	1			T30	1		T31	2		T56	1
valid_sources[0x39]	2543	1			T27	1		T77	2		T10	1
valid_sources[0x3a]	2339	1			T5	2		T66	1		T10	1
valid_sources[0x3b]	2717	1			T51	2		T54	1		T56	1
valid_sources[0x3c]	2925	1			T10	1		T11	2		T46	5
valid_sources[0x3d]	3107	1			T74	1		T46	4		T50	1
valid_sources[0x3e]	2478	1			T30	1		T77	1		T171	1
valid_sources[0x3f]	3006	1			T10	4		T11	2		T46	3
valid_sources[0x40]	2471	1			T31	1		T11	5		T50	4
valid_sources[0x41]	3185	1			T66	1		T11	2		T46	2
valid_sources[0x42]	2407	1			T53	1		T54	2		T112	3
valid_sources[0x43]	2258	1			T27	3		T10	1		T11	1
valid_sources[0x44]	2841	1			T46	3		T48	2		T50	3
valid_sources[0x45]	2925	1			T4	2		T113	12		T10	3
valid_sources[0x46]	2646	1			T5	1		T10	2		T11	4
valid_sources[0x47]	3198	1			T4	8		T53	2		T74	1
valid_sources[0x48]	2900	1			T56	1		T10	3		T11	2
valid_sources[0x49]	3166	1			T32	2		T54	1		T56	1
valid_sources[0x4a]	2669	1			T4	1		T56	1		T65	100
valid_sources[0x4b]	4188	1			T31	1		T56	1		T10	4
valid_sources[0x4c]	2919	1			T27	3		T43	1		T110	5
valid_sources[0x4d]	2641	1			T42	46		T54	1		T10	4
valid_sources[0x4e]	2989	1			T110	3		T74	3		T10	1
valid_sources[0x4f]	3399	1			T4	2		T32	3		T56	1
valid_sources[0x50]	2840	1			T27	4		T54	1		T111	2
valid_sources[0x51]	3080	1			T4	1		T5	1		T21	31
valid_sources[0x52]	3150	1			T31	2		T112	3		T10	2
valid_sources[0x53]	2641	1			T10	3		T46	1		T50	4
valid_sources[0x54]	2985	1			T53	2		T10	1		T11	1
valid_sources[0x55]	2680	1			T53	1		T77	3		T113	1
valid_sources[0x56]	2946	1			T4	1		T53	1		T54	1
valid_sources[0x57]	2305	1			T30	6		T31	2		T46	3
valid_sources[0x58]	4186	1			T32	3		T54	2		T110	9
valid_sources[0x59]	2810	1			T67	1		T10	2		T25	35
valid_sources[0x5a]	2816	1			T4	1		T32	1		T54	1
valid_sources[0x5b]	2584	1			T30	1		T56	1		T11	4
valid_sources[0x5c]	2703	1			T31	1		T54	1		T10	4
valid_sources[0x5d]	2295	1			T27	1		T111	1		T10	5
valid_sources[0x5e]	2848	1			T4	2		T27	2		T30	2
valid_sources[0x5f]	2718	1			T30	4		T32	3		T10	1
valid_sources[0x60]	3056	1			T32	1		T54	1		T50	1
valid_sources[0x61]	2649	1			T56	1		T10	2		T11	1
valid_sources[0x62]	2795	1			T30	4		T10	1		T11	2
valid_sources[0x63]	2787	1			T53	2		T56	1		T10	1
valid_sources[0x64]	2607	1			T4	3		T30	1		T31	1
valid_sources[0x65]	3468	1			T31	1		T51	2		T56	1
valid_sources[0x66]	2404	1			T4	2		T30	3		T111	1
valid_sources[0x67]	3346	1			T1	188		T171	1		T11	1
valid_sources[0x68]	2697	1			T32	1		T77	1		T11	1
valid_sources[0x69]	2617	1			T4	1		T30	2		T31	1
valid_sources[0x6a]	2727	1			T77	1		T11	2		T26	1
valid_sources[0x6b]	2358	1			T76	56		T77	4		T171	1
valid_sources[0x6c]	2598	1			T31	1		T53	1		T11	1
valid_sources[0x6d]	3085	1			T12	658		T10	1		T24	35
valid_sources[0x6e]	4773	1			T54	1		T10	3		T46	4
valid_sources[0x6f]	2256	1			T67	1		T10	2		T11	2
valid_sources[0x70]	2641	1			T4	1		T30	5		T51	15
valid_sources[0x71]	2972	1			T56	1		T74	6		T77	4
valid_sources[0x72]	2220	1			T56	1		T113	6		T10	1
valid_sources[0x73]	3209	1			T111	2		T209	1		T11	4
valid_sources[0x74]	2445	1			T32	1		T56	2		T72	16
valid_sources[0x75]	2612	1			T10	1		T11	5		T181	2
valid_sources[0x76]	2525	1			T4	2		T31	2		T32	1
valid_sources[0x77]	2626	1			T54	1		T66	5		T10	3
valid_sources[0x78]	2964	1			T11	2		T26	1		T46	2
valid_sources[0x79]	3224	1			T4	2		T10	1		T11	3
valid_sources[0x7a]	2264	1			T51	1		T66	2		T10	2
valid_sources[0x7b]	2748	1			T32	1		T54	1		T77	2
valid_sources[0x7c]	2220	1			T30	1		T54	1		T56	1
valid_sources[0x7d]	4234	1			T32	1		T10	2		T11	1
valid_sources[0x7e]	2905	1			T32	1		T56	2		T11	4
valid_sources[0x7f]	2682	1			T6	2		T77	5		T10	1
valid_sources[0x80]	2901	1			T4	1		T6	1		T30	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

141355

1

T4

17

T6

3

T27

6

values[0x0]

all_enables

biggest_size

195939

1

T4

9

T5

3

T27

2

values[0x1]

all_enables

biggest_size

170204

1

T4

2

T6

1

T27

3