Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T28
0	1	Covered	T5,T52,T74
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T28,T55,T64
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	168205749	8386	0	0
GateOpen_A	168205749	15499	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168205749	8386	0	0
T1	86700	0	0	0
T4	16621	4	0	0
T5	8360	9	0	0
T6	10591	0	0	0
T20	0	4	0	0
T27	4713	0	0	0
T28	8454	13	0	0
T29	3650	0	0	0
T30	6325	0	0	0
T31	14831	0	0	0
T32	17900	0	0	0
T51	0	4	0	0
T52	0	7	0	0
T55	0	11	0	0
T64	0	22	0	0
T66	0	4	0	0
T74	0	19	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168205749	15499	0	0
T1	86700	20	0	0
T4	16621	8	0	0
T5	8360	13	0	0
T6	10591	4	0	0
T27	4713	0	0	0
T28	8454	17	0	0
T29	3650	4	0	0
T30	6325	4	0	0
T31	14831	0	0	0
T32	17900	0	0	0
T43	0	4	0	0
T51	0	4	0	0
T52	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T28
0	1	Covered	T5,T52,T74
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T28,T55,T64
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	18107401	2011	0	0
GateOpen_A	18107401	3785	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18107401	2011	0	0
T1	7385	0	0	0
T4	1825	1	0	0
T5	907	3	0	0
T6	1237	0	0	0
T20	0	1	0	0
T27	538	0	0	0
T28	924	3	0	0
T29	409	0	0	0
T30	690	0	0	0
T31	1642	0	0	0
T32	2123	0	0	0
T51	0	1	0	0
T52	0	1	0	0
T55	0	3	0	0
T64	0	6	0	0
T66	0	1	0	0
T74	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18107401	3785	0	0
T1	7385	5	0	0
T4	1825	2	0	0
T5	907	4	0	0
T6	1237	1	0	0
T27	538	0	0	0
T28	924	4	0	0
T29	409	1	0	0
T30	690	1	0	0
T31	1642	0	0	0
T32	2123	0	0	0
T43	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T28
0	1	Covered	T5,T52,T74
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T28,T55,T64
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	36215311	2141	0	0
GateOpen_A	36215311	3915	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36215311	2141	0	0
T1	14770	0	0	0
T4	3649	1	0	0
T5	1813	2	0	0
T6	2473	0	0	0
T20	0	1	0	0
T27	1078	0	0	0
T28	1847	3	0	0
T29	818	0	0	0
T30	1379	0	0	0
T31	3283	0	0	0
T32	4253	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	3	0	0
T64	0	6	0	0
T66	0	1	0	0
T74	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36215311	3915	0	0
T1	14770	5	0	0
T4	3649	2	0	0
T5	1813	3	0	0
T6	2473	1	0	0
T27	1078	0	0	0
T28	1847	4	0	0
T29	818	1	0	0
T30	1379	1	0	0
T31	3283	0	0	0
T32	4253	0	0	0
T43	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T28
0	1	Covered	T5,T52,T74
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T28,T55,T64
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	74346532	2137	0	0
GateOpen_A	74346532	3918	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74346532	2137	0	0
T1	43029	0	0	0
T4	7431	1	0	0
T5	3760	2	0	0
T6	4587	0	0	0
T20	0	1	0	0
T27	2065	0	0	0
T28	3759	3	0	0
T29	1615	0	0	0
T30	2837	0	0	0
T31	6604	0	0	0
T32	7682	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	3	0	0
T64	0	6	0	0
T66	0	1	0	0
T74	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74346532	3918	0	0
T1	43029	5	0	0
T4	7431	2	0	0
T5	3760	3	0	0
T6	4587	1	0	0
T27	2065	0	0	0
T28	3759	4	0	0
T29	1615	1	0	0
T30	2837	1	0	0
T31	6604	0	0	0
T32	7682	0	0	0
T43	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T28
0	1	Covered	T5,T52,T74
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T28,T55,T64
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	39536505	2097	0	0
GateOpen_A	39536505	3881	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39536505	2097	0	0
T1	21516	0	0	0
T4	3716	1	0	0
T5	1880	2	0	0
T6	2294	0	0	0
T20	0	1	0	0
T27	1032	0	0	0
T28	1924	4	0	0
T29	808	0	0	0
T30	1419	0	0	0
T31	3302	0	0	0
T32	3842	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T64	0	4	0	0
T66	0	1	0	0
T74	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39536505	3881	0	0
T1	21516	5	0	0
T4	3716	2	0	0
T5	1880	3	0	0
T6	2294	1	0	0
T27	1032	0	0	0
T28	1924	5	0	0
T29	808	1	0	0
T30	1419	1	0	0
T31	3302	0	0	0
T32	3842	0	0	0
T43	0	1	0	0
T51	0	1	0	0
T52	0	2	0	0