Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	192191885	31869	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192191885	31869	0	0
T9	131485	54	0	0
T10	364915	77	0	0
T11	251620	155	0	0
T13	0	76	0	0
T14	0	140	0	0
T15	0	115	0	0
T16	0	194	0	0
T17	0	51	0	0
T18	0	264	0	0
T19	0	90	0	0
T20	10410	0	0	0
T21	7085	0	0	0
T22	3940	0	0	0
T23	6325	0	0	0
T24	6950	0	0	0
T25	12900	0	0	0
T26	11670	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38438377	4693	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	4693	0	0
T9	26297	8	0	0
T10	72983	11	0	0
T11	50324	25	0	0
T13	0	12	0	0
T14	0	23	0	0
T15	0	18	0	0
T16	0	24	0	0
T17	0	8	0	0
T18	0	38	0	0
T19	0	12	0	0
T20	2082	0	0	0
T21	1417	0	0	0
T22	788	0	0	0
T23	1265	0	0	0
T24	1390	0	0	0
T25	2580	0	0	0
T26	2334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38438377	4663	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	4663	0	0
T9	26297	8	0	0
T10	72983	11	0	0
T11	50324	25	0	0
T13	0	12	0	0
T14	0	22	0	0
T15	0	18	0	0
T16	0	28	0	0
T17	0	8	0	0
T18	0	38	0	0
T19	0	13	0	0
T20	2082	0	0	0
T21	1417	0	0	0
T22	788	0	0	0
T23	1265	0	0	0
T24	1390	0	0	0
T25	2580	0	0	0
T26	2334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38438377	6422	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	6422	0	0
T9	26297	11	0	0
T10	72983	17	0	0
T11	50324	31	0	0
T13	0	15	0	0
T14	0	28	0	0
T15	0	24	0	0
T16	0	39	0	0
T17	0	10	0	0
T18	0	54	0	0
T19	0	18	0	0
T20	2082	0	0	0
T21	1417	0	0	0
T22	788	0	0	0
T23	1265	0	0	0
T24	1390	0	0	0
T25	2580	0	0	0
T26	2334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38438377	6400	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	6400	0	0
T9	26297	11	0	0
T10	72983	15	0	0
T11	50324	32	0	0
T13	0	16	0	0
T14	0	29	0	0
T15	0	23	0	0
T16	0	38	0	0
T17	0	10	0	0
T18	0	53	0	0
T19	0	17	0	0
T20	2082	0	0	0
T21	1417	0	0	0
T22	788	0	0	0
T23	1265	0	0	0
T24	1390	0	0	0
T25	2580	0	0	0
T26	2334	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38438377	9691	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	9691	0	0
T9	26297	16	0	0
T10	72983	23	0	0
T11	50324	42	0	0
T13	0	21	0	0
T14	0	38	0	0
T15	0	32	0	0
T16	0	65	0	0
T17	0	15	0	0
T18	0	81	0	0
T19	0	30	0	0
T20	2082	0	0	0
T21	1417	0	0	0
T22	788	0	0	0
T23	1265	0	0	0
T24	1390	0	0	0
T25	2580	0	0	0
T26	2334	0	0	0