Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T62,T63

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	38438377	35255326	0	0
AllClkBypReqTrue_A	38438377	83000	0	0
IoClkBypReqFalse_A	38438377	35195077	0	2415
IoClkBypReqTrue_A	38438377	138357	0	0
LcClkBypAckFalse_A	38438377	35258755	0	0
LcClkBypAckTrue_A	38438377	79571	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	35255326	0	0
T1	2688	1001	0	0
T4	1702	1658	0	0
T5	978	917	0	0
T6	1146	1083	0	0
T27	2149	1932	0	0
T28	1156	1106	0	0
T29	1614	1324	0	0
T30	2836	2728	0	0
T31	1512	1481	0	0
T32	1841	1697	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	83000	0	0
T1	2688	0	0	0
T6	1146	42	0	0
T27	2149	148	0	0
T28	1156	0	0	0
T29	1614	127	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	117	0	0
T42	2031	14	0	0
T43	1744	68	0	0
T72	0	25	0	0
T110	0	276	0	0
T111	0	204	0	0
T112	0	21	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	35195077	0	2415
T1	2688	991	0	3
T4	1702	1656	0	3
T5	978	915	0	3
T6	1146	1063	0	3
T27	2149	2048	0	3
T28	1156	1104	0	3
T29	1614	1251	0	3
T30	2836	2726	0	3
T31	1512	1479	0	3
T32	1841	1436	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	138357	0	0
T1	2688	0	0	0
T6	1146	60	0	0
T27	2149	30	0	0
T28	1156	0	0	0
T29	1614	198	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	376	0	0
T42	2031	403	0	0
T43	1744	120	0	0
T75	0	447	0	0
T110	0	468	0	0
T111	0	297	0	0
T112	0	208	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	35258755	0	0
T1	2688	1001	0	0
T4	1702	1658	0	0
T5	978	917	0	0
T6	1146	1074	0	0
T27	2149	2053	0	0
T28	1156	1106	0	0
T29	1614	1330	0	0
T30	2836	2728	0	0
T31	1512	1481	0	0
T32	1841	1648	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	79571	0	0
T1	2688	0	0	0
T6	1146	51	0	0
T27	2149	27	0	0
T28	1156	0	0	0
T29	1614	121	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	166	0	0
T42	2031	182	0	0
T43	1744	0	0	0
T75	0	181	0	0
T110	0	354	0	0
T111	0	147	0	0
T112	0	44	0	0
T113	0	107	0	0