Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	330903028	9996	0	0
TransStop_A	330903028	5049	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330903028	9996	0	0
T1	179296	0	0	0
T4	30964	4	0	0
T5	15664	0	0	0
T6	19116	0	0	0
T20	0	4	0	0
T27	8600	0	0	0
T28	17356	0	0	0
T29	6732	0	0	0
T30	11820	33	0	0
T31	27516	13	0	0
T32	32008	0	0	0
T51	0	4	0	0
T53	0	12	0	0
T56	0	24	0	0
T66	0	4	0	0
T76	0	16	0	0
T77	0	29	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	330903028	5049	0	0
T1	179296	0	0	0
T4	30964	4	0	0
T5	15664	0	0	0
T6	19116	0	0	0
T20	0	4	0	0
T27	8600	0	0	0
T28	17356	0	0	0
T29	6732	0	0	0
T30	11820	9	0	0
T31	27516	10	0	0
T32	32008	0	0	0
T45	0	9	0	0
T51	0	4	0	0
T53	0	3	0	0
T56	0	11	0	0
T66	0	4	0	0
T76	0	8	0	0
T77	0	16	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	82725757	2498	0	0
TransStop_A	82725757	1258	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	2498	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	8	0	0
T31	6879	3	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	4	0	0
T56	0	2	0	0
T66	0	1	0	0
T76	0	5	0	0
T77	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	1258	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	1	0	0
T31	6879	2	0	0
T32	8002	0	0	0
T45	0	4	0	0
T51	0	1	0	0
T53	0	1	0	0
T66	0	1	0	0
T76	0	3	0	0
T77	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	82725757	2456	0	0
TransStop_A	82725757	1255	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	2456	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	9	0	0
T31	6879	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	4	0	0
T56	0	8	0	0
T66	0	1	0	0
T76	0	3	0	0
T77	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	1255	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	3	0	0
T31	6879	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	3	0	0
T66	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	82725757	2582	0	0
TransStop_A	82725757	1298	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	2582	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	7	0	0
T31	6879	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	3	0	0
T56	0	9	0	0
T66	0	1	0	0
T76	0	3	0	0
T77	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	1298	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	2	0	0
T31	6879	3	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	4	0	0
T66	0	1	0	0
T76	0	1	0	0
T77	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	82725757	2460	0	0
TransStop_A	82725757	1238	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	2460	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	9	0	0
T31	6879	2	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	5	0	0
T66	0	1	0	0
T76	0	5	0	0
T77	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725757	1238	0	0
T1	44824	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T20	0	1	0	0
T27	2150	0	0	0
T28	4339	0	0	0
T29	1683	0	0	0
T30	2955	3	0	0
T31	6879	1	0	0
T32	8002	0	0	0
T45	0	5	0	0
T51	0	1	0	0
T56	0	4	0	0
T66	0	1	0	0
T76	0	3	0	0
T77	0	5	0	0