Line Coverage for Module :
prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T6 T27 T29
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T6 T27 T29
Line Coverage for Module :
prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Module :
prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
984289231 |
927235922 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
984289231 |
927235922 |
0 |
0 |
| T1 |
465162 |
183492 |
0 |
0 |
| T4 |
88438 |
86445 |
0 |
0 |
| T5 |
44956 |
42452 |
0 |
0 |
| T6 |
55762 |
54874 |
0 |
0 |
| T27 |
29837 |
28971 |
0 |
0 |
| T28 |
48242 |
46099 |
0 |
0 |
| T29 |
23048 |
21006 |
0 |
0 |
| T30 |
40258 |
38887 |
0 |
0 |
| T31 |
78742 |
77216 |
0 |
0 |
| T32 |
93579 |
92423 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T6 T27 T29
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T6 T27 T29
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
38438377 |
35340772 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
38438377 |
35340772 |
0 |
0 |
| T1 |
2688 |
1006 |
0 |
0 |
| T4 |
1702 |
1659 |
0 |
0 |
| T5 |
978 |
918 |
0 |
0 |
| T6 |
1146 |
1126 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
1156 |
1107 |
0 |
0 |
| T29 |
1614 |
1452 |
0 |
0 |
| T30 |
2836 |
2729 |
0 |
0 |
| T31 |
1512 |
1482 |
0 |
0 |
| T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 2 | 2 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T6 T27 T29
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 assign mubi_out = mubi_int;
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T6 T27 T29
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
38438377 |
35340772 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
38438377 |
35340772 |
0 |
0 |
| T1 |
2688 |
1006 |
0 |
0 |
| T4 |
1702 |
1659 |
0 |
0 |
| T5 |
978 |
918 |
0 |
0 |
| T6 |
1146 |
1126 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
1156 |
1107 |
0 |
0 |
| T29 |
1614 |
1452 |
0 |
0 |
| T30 |
2836 |
2729 |
0 |
0 |
| T31 |
1512 |
1482 |
0 |
0 |
| T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T6 T27 T29
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
38438377 |
35340772 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
38438377 |
35340772 |
0 |
0 |
| T1 |
2688 |
1006 |
0 |
0 |
| T4 |
1702 |
1659 |
0 |
0 |
| T5 |
978 |
918 |
0 |
0 |
| T6 |
1146 |
1126 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
1156 |
1107 |
0 |
0 |
| T29 |
1614 |
1452 |
0 |
0 |
| T30 |
2836 |
2729 |
0 |
0 |
| T31 |
1512 |
1482 |
0 |
0 |
| T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18106988 |
17536185 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18106988 |
17536185 |
0 |
0 |
| T1 |
7384 |
4010 |
0 |
0 |
| T4 |
1824 |
1810 |
0 |
0 |
| T5 |
906 |
882 |
0 |
0 |
| T6 |
1236 |
1225 |
0 |
0 |
| T27 |
537 |
530 |
0 |
0 |
| T28 |
923 |
892 |
0 |
0 |
| T29 |
409 |
402 |
0 |
0 |
| T30 |
689 |
682 |
0 |
0 |
| T31 |
1641 |
1617 |
0 |
0 |
| T32 |
2123 |
2113 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
82725328 |
77824277 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
82725328 |
77824277 |
0 |
0 |
| T1 |
44823 |
16711 |
0 |
0 |
| T4 |
7741 |
7544 |
0 |
0 |
| T5 |
3916 |
3676 |
0 |
0 |
| T6 |
4779 |
4695 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
4338 |
4141 |
0 |
0 |
| T29 |
1682 |
1513 |
0 |
0 |
| T30 |
2955 |
2843 |
0 |
0 |
| T31 |
6878 |
6738 |
0 |
0 |
| T32 |
8002 |
7890 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39536103 |
37195362 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39536103 |
37195362 |
0 |
0 |
| T1 |
21515 |
8021 |
0 |
0 |
| T4 |
3716 |
3621 |
0 |
0 |
| T5 |
1880 |
1765 |
0 |
0 |
| T6 |
2293 |
2254 |
0 |
0 |
| T27 |
1032 |
999 |
0 |
0 |
| T28 |
1923 |
1829 |
0 |
0 |
| T29 |
807 |
726 |
0 |
0 |
| T30 |
1418 |
1364 |
0 |
0 |
| T31 |
3302 |
3235 |
0 |
0 |
| T32 |
3841 |
3787 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
74346096 |
69793057 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
74346096 |
69793057 |
0 |
0 |
| T1 |
43028 |
16042 |
0 |
0 |
| T4 |
7431 |
7241 |
0 |
0 |
| T5 |
3759 |
3528 |
0 |
0 |
| T6 |
4587 |
4507 |
0 |
0 |
| T27 |
2064 |
1998 |
0 |
0 |
| T28 |
3758 |
3569 |
0 |
0 |
| T29 |
1614 |
1452 |
0 |
0 |
| T30 |
2836 |
2729 |
0 |
0 |
| T31 |
6603 |
6468 |
0 |
0 |
| T32 |
7682 |
7574 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
36214891 |
35073183 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
36214891 |
35073183 |
0 |
0 |
| T1 |
14769 |
8021 |
0 |
0 |
| T4 |
3648 |
3620 |
0 |
0 |
| T5 |
1812 |
1764 |
0 |
0 |
| T6 |
2473 |
2452 |
0 |
0 |
| T27 |
1078 |
1064 |
0 |
0 |
| T28 |
1846 |
1784 |
0 |
0 |
| T29 |
818 |
804 |
0 |
0 |
| T30 |
1378 |
1364 |
0 |
0 |
| T31 |
3282 |
3234 |
0 |
0 |
| T32 |
4253 |
4232 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18106988 |
17536185 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18106988 |
17536185 |
0 |
0 |
| T1 |
7384 |
4010 |
0 |
0 |
| T4 |
1824 |
1810 |
0 |
0 |
| T5 |
906 |
882 |
0 |
0 |
| T6 |
1236 |
1225 |
0 |
0 |
| T27 |
537 |
530 |
0 |
0 |
| T28 |
923 |
892 |
0 |
0 |
| T29 |
409 |
402 |
0 |
0 |
| T30 |
689 |
682 |
0 |
0 |
| T31 |
1641 |
1617 |
0 |
0 |
| T32 |
2123 |
2113 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
82725328 |
77824277 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
82725328 |
77824277 |
0 |
0 |
| T1 |
44823 |
16711 |
0 |
0 |
| T4 |
7741 |
7544 |
0 |
0 |
| T5 |
3916 |
3676 |
0 |
0 |
| T6 |
4779 |
4695 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
4338 |
4141 |
0 |
0 |
| T29 |
1682 |
1513 |
0 |
0 |
| T30 |
2955 |
2843 |
0 |
0 |
| T31 |
6878 |
6738 |
0 |
0 |
| T32 |
8002 |
7890 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18106988 |
17536185 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18106988 |
17536185 |
0 |
0 |
| T1 |
7384 |
4010 |
0 |
0 |
| T4 |
1824 |
1810 |
0 |
0 |
| T5 |
906 |
882 |
0 |
0 |
| T6 |
1236 |
1225 |
0 |
0 |
| T27 |
537 |
530 |
0 |
0 |
| T28 |
923 |
892 |
0 |
0 |
| T29 |
409 |
402 |
0 |
0 |
| T30 |
689 |
682 |
0 |
0 |
| T31 |
1641 |
1617 |
0 |
0 |
| T32 |
2123 |
2113 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
18106988 |
17536185 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
18106988 |
17536185 |
0 |
0 |
| T1 |
7384 |
4010 |
0 |
0 |
| T4 |
1824 |
1810 |
0 |
0 |
| T5 |
906 |
882 |
0 |
0 |
| T6 |
1236 |
1225 |
0 |
0 |
| T27 |
537 |
530 |
0 |
0 |
| T28 |
923 |
892 |
0 |
0 |
| T29 |
409 |
402 |
0 |
0 |
| T30 |
689 |
682 |
0 |
0 |
| T31 |
1641 |
1617 |
0 |
0 |
| T32 |
2123 |
2113 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
36214891 |
35073183 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
36214891 |
35073183 |
0 |
0 |
| T1 |
14769 |
8021 |
0 |
0 |
| T4 |
3648 |
3620 |
0 |
0 |
| T5 |
1812 |
1764 |
0 |
0 |
| T6 |
2473 |
2452 |
0 |
0 |
| T27 |
1078 |
1064 |
0 |
0 |
| T28 |
1846 |
1784 |
0 |
0 |
| T29 |
818 |
804 |
0 |
0 |
| T30 |
1378 |
1364 |
0 |
0 |
| T31 |
3282 |
3234 |
0 |
0 |
| T32 |
4253 |
4232 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
74346096 |
69793057 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
74346096 |
69793057 |
0 |
0 |
| T1 |
43028 |
16042 |
0 |
0 |
| T4 |
7431 |
7241 |
0 |
0 |
| T5 |
3759 |
3528 |
0 |
0 |
| T6 |
4587 |
4507 |
0 |
0 |
| T27 |
2064 |
1998 |
0 |
0 |
| T28 |
3758 |
3569 |
0 |
0 |
| T29 |
1614 |
1452 |
0 |
0 |
| T30 |
2836 |
2729 |
0 |
0 |
| T31 |
6603 |
6468 |
0 |
0 |
| T32 |
7682 |
7574 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
39536103 |
37195362 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
39536103 |
37195362 |
0 |
0 |
| T1 |
21515 |
8021 |
0 |
0 |
| T4 |
3716 |
3621 |
0 |
0 |
| T5 |
1880 |
1765 |
0 |
0 |
| T6 |
2293 |
2254 |
0 |
0 |
| T27 |
1032 |
999 |
0 |
0 |
| T28 |
1923 |
1829 |
0 |
0 |
| T29 |
807 |
726 |
0 |
0 |
| T30 |
1418 |
1364 |
0 |
0 |
| T31 |
3302 |
3235 |
0 |
0 |
| T32 |
3841 |
3787 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
82725328 |
77824277 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
82725328 |
77824277 |
0 |
0 |
| T1 |
44823 |
16711 |
0 |
0 |
| T4 |
7741 |
7544 |
0 |
0 |
| T5 |
3916 |
3676 |
0 |
0 |
| T6 |
4779 |
4695 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
4338 |
4141 |
0 |
0 |
| T29 |
1682 |
1513 |
0 |
0 |
| T30 |
2955 |
2843 |
0 |
0 |
| T31 |
6878 |
6738 |
0 |
0 |
| T32 |
8002 |
7890 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
82725328 |
77824277 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
82725328 |
77824277 |
0 |
0 |
| T1 |
44823 |
16711 |
0 |
0 |
| T4 |
7741 |
7544 |
0 |
0 |
| T5 |
3916 |
3676 |
0 |
0 |
| T6 |
4779 |
4695 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
4338 |
4141 |
0 |
0 |
| T29 |
1682 |
1513 |
0 |
0 |
| T30 |
2955 |
2843 |
0 |
0 |
| T31 |
6878 |
6738 |
0 |
0 |
| T32 |
8002 |
7890 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
82725328 |
77824277 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
82725328 |
77824277 |
0 |
0 |
| T1 |
44823 |
16711 |
0 |
0 |
| T4 |
7741 |
7544 |
0 |
0 |
| T5 |
3916 |
3676 |
0 |
0 |
| T6 |
4779 |
4695 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
4338 |
4141 |
0 |
0 |
| T29 |
1682 |
1513 |
0 |
0 |
| T30 |
2955 |
2843 |
0 |
0 |
| T31 |
6878 |
6738 |
0 |
0 |
| T32 |
8002 |
7890 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 3 | 3 | 100.00 |
| CONT_ASSIGN | 34 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
33 logic [MuBi4Width-1:0] mubi, mubi_int, mubi_out;
34 1/1 assign mubi = MuBi4Width'(mubi_i);
Tests: T4 T5 T6
35
36 // first generation block decides whether a flop should be present
37 if (AsyncOn) begin : gen_flops
38 prim_flop #(
39 .Width(MuBi4Width),
40 .ResetValue(MuBi4Width'(ResetValue))
41 ) u_prim_flop (
42 .clk_i,
43 .rst_ni,
44 .d_i ( mubi ),
45 .q_o ( mubi_int )
46 );
47 end else begin : gen_no_flops
48 assign mubi_int = mubi;
49
50 // This unused companion logic helps remove lint errors
51 // for modules where clock and reset are used for assertions only
52 // This logic will be removed for sythesis since it is unloaded.
53 mubi4_t unused_logic;
54 always_ff @(posedge clk_i or negedge rst_ni) begin
55 if (!rst_ni) begin
56 unused_logic <= MuBi4False;
57 end else begin
58 unused_logic <= mubi_i;
59 end
60 end
61 end
62
63 // second generation block determines output buffer type
64 // 1. If EnSecBuf -> always leads to a sec buffer regardless of first block
65 // 2. If not EnSecBuf and not AsyncOn -> use normal buffer
66 // 3. If not EnSecBuf and AsyncOn -> feed through
67 if (EnSecBuf) begin : gen_sec_buf
68 prim_sec_anchor_buf #(
69 .Width(4)
70 ) u_prim_sec_buf (
71 .in_i(mubi_int),
72 .out_o(mubi_out)
73 );
74 end else if (!AsyncOn) begin : gen_prim_buf
75 prim_buf #(
76 .Width(4)
77 ) u_prim_buf (
78 .in_i(mubi_int),
79 .out_o(mubi_out)
80 );
81 end else begin : gen_feedthru
82 1/1 assign mubi_out = mubi_int;
Tests: T4 T5 T6
83 end
84
85 1/1 assign mubi_o = mubi4_t'(mubi_out);
Tests: T4 T5 T6
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
OutputsKnown_A |
82725328 |
77824277 |
0 |
0 |
OutputsKnown_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
82725328 |
77824277 |
0 |
0 |
| T1 |
44823 |
16711 |
0 |
0 |
| T4 |
7741 |
7544 |
0 |
0 |
| T5 |
3916 |
3676 |
0 |
0 |
| T6 |
4779 |
4695 |
0 |
0 |
| T27 |
2149 |
2081 |
0 |
0 |
| T28 |
4338 |
4141 |
0 |
0 |
| T29 |
1682 |
1513 |
0 |
0 |
| T30 |
2955 |
2843 |
0 |
0 |
| T31 |
6878 |
6738 |
0 |
0 |
| T32 |
8002 |
7890 |
0 |
0 |