Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	39391736	546092	0	0
clk_enables_rd_A	39391736	10644	0	0
clk_hints_rd_A	39391736	10057	0	0
extclk_ctrl_rd_A	39391736	12315	0	0
extclk_ctrl_regwen_rd_A	39391736	7983	0	0
jitter_enable_rd_A	39391736	20150	0	0
jitter_regwen_rd_A	39391736	7924	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	546092	0	0
T7	40361	0	0	0
T16	139422	0	0	0
T34	0	5471	0	0
T35	0	8081	0	0
T39	108510	5126	0	0
T41	0	8987	0	0
T70	275394	0	0	0
T88	0	11584	0	0
T89	0	10708	0	0
T90	0	14756	0	0
T91	0	9898	0	0
T92	0	19947	0	0
T93	0	7430	0	0
T94	2481	0	0	0
T95	1264	0	0	0
T96	1814	0	0	0
T97	23883	0	0	0
T98	903	0	0	0
T99	73996	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	10644	0	0
T35	0	267	0	0
T41	0	385	0	0
T60	0	15	0	0
T68	4810	0	0	0
T69	0	6	0	0
T73	19991	0	0	0
T89	0	519	0	0
T157	1916	5	0	0
T158	0	4	0	0
T159	0	3	0	0
T160	0	12	0	0
T161	0	357	0	0
T162	1668	0	0	0
T163	921	0	0	0
T164	1117	0	0	0
T165	799	0	0	0
T166	2001	0	0	0
T167	1018	0	0	0
T168	990	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	10057	0	0
T35	0	326	0	0
T41	0	338	0	0
T60	0	6	0	0
T68	4810	0	0	0
T69	0	8	0	0
T73	19991	0	0	0
T89	0	416	0	0
T94	0	8	0	0
T157	1916	8	0	0
T158	0	4	0	0
T162	1668	0	0	0
T163	921	0	0	0
T164	1117	0	0	0
T165	799	0	0	0
T166	2001	0	0	0
T167	1018	0	0	0
T168	990	0	0	0
T169	0	3	0	0
T170	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	12315	0	0
T1	2688	0	0	0
T26	0	47	0	0
T27	2149	78	0	0
T28	1156	0	0	0
T29	1614	13	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T46	0	62	0	0
T51	1589	0	0	0
T72	0	8	0	0
T101	0	10	0	0
T112	0	24	0	0
T171	0	22	0	0
T172	0	65	0	0
T173	0	68	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	7983	0	0
T35	0	285	0	0
T41	0	329	0	0
T46	65908	26	0	0
T47	1388	0	0	0
T48	10855	0	0	0
T49	1236	0	0	0
T89	0	505	0	0
T161	0	229	0	0
T174	0	36	0	0
T175	0	26	0	0
T176	0	41	0	0
T177	0	43	0	0
T178	0	25	0	0
T179	1451	0	0	0
T180	780	0	0	0
T181	926	0	0	0
T182	3182	0	0	0
T183	1620	0	0	0
T184	1592	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	20150	0	0
T35	0	341	0	0
T41	0	885	0	0
T60	0	479	0	0
T68	4810	0	0	0
T69	0	106	0	0
T73	19991	0	0	0
T89	0	719	0	0
T94	0	129	0	0
T157	1916	145	0	0
T158	0	109	0	0
T162	1668	0	0	0
T163	921	0	0	0
T164	1117	0	0	0
T165	799	0	0	0
T166	2001	0	0	0
T167	1018	0	0	0
T168	990	0	0	0
T169	0	70	0	0
T170	0	102	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39391736	7924	0	0
T35	242780	316	0	0
T36	46039	0	0	0
T41	0	405	0	0
T89	0	430	0	0
T161	0	268	0	0
T185	0	321	0	0
T186	0	87	0	0
T187	0	314	0	0
T188	0	425	0	0
T189	0	487	0	0
T190	0	271	0	0
T191	1075	0	0	0
T192	1565	0	0	0
T193	21175	0	0	0
T194	3021	0	0	0
T195	109359	0	0	0
T196	1961	0	0	0
T197	1449	0	0	0
T198	1193	0	0	0