Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Module :
prim_reg_cdc
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393917360 |
771689 |
0 |
0 |
T1 |
26880 |
285 |
0 |
0 |
T2 |
0 |
529 |
0 |
0 |
T3 |
0 |
2398 |
0 |
0 |
T9 |
0 |
478 |
0 |
0 |
T10 |
0 |
1370 |
0 |
0 |
T11 |
0 |
1203 |
0 |
0 |
T12 |
0 |
1382 |
0 |
0 |
T32 |
18410 |
0 |
0 |
0 |
T38 |
0 |
886 |
0 |
0 |
T42 |
20310 |
0 |
0 |
0 |
T43 |
17440 |
0 |
0 |
0 |
T46 |
0 |
2258 |
0 |
0 |
T50 |
0 |
1766 |
0 |
0 |
T51 |
15890 |
0 |
0 |
0 |
T52 |
12890 |
0 |
0 |
0 |
T53 |
10440 |
0 |
0 |
0 |
T54 |
17810 |
0 |
0 |
0 |
T55 |
8160 |
0 |
0 |
0 |
T56 |
28490 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
521203156 |
493160134 |
0 |
0 |
T1 |
263038 |
105610 |
0 |
0 |
T4 |
48720 |
47672 |
0 |
0 |
T5 |
24546 |
23230 |
0 |
0 |
T6 |
30736 |
30266 |
0 |
0 |
T27 |
13720 |
13344 |
0 |
0 |
T28 |
25576 |
24430 |
0 |
0 |
T29 |
10660 |
9794 |
0 |
0 |
T30 |
18552 |
17964 |
0 |
0 |
T31 |
43412 |
42584 |
0 |
0 |
T32 |
51802 |
51192 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393917360 |
148609 |
0 |
0 |
T1 |
26880 |
114 |
0 |
0 |
T2 |
0 |
60 |
0 |
0 |
T3 |
0 |
448 |
0 |
0 |
T9 |
0 |
100 |
0 |
0 |
T10 |
0 |
260 |
0 |
0 |
T11 |
0 |
340 |
0 |
0 |
T12 |
0 |
392 |
0 |
0 |
T32 |
18410 |
0 |
0 |
0 |
T38 |
0 |
160 |
0 |
0 |
T42 |
20310 |
0 |
0 |
0 |
T43 |
17440 |
0 |
0 |
0 |
T46 |
0 |
262 |
0 |
0 |
T50 |
0 |
520 |
0 |
0 |
T51 |
15890 |
0 |
0 |
0 |
T52 |
12890 |
0 |
0 |
0 |
T53 |
10440 |
0 |
0 |
0 |
T54 |
17810 |
0 |
0 |
0 |
T55 |
8160 |
0 |
0 |
0 |
T56 |
28490 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
393917360 |
361932350 |
0 |
0 |
T1 |
26880 |
10060 |
0 |
0 |
T4 |
17020 |
16590 |
0 |
0 |
T5 |
9780 |
9180 |
0 |
0 |
T6 |
11460 |
11260 |
0 |
0 |
T27 |
21490 |
20810 |
0 |
0 |
T28 |
11560 |
11070 |
0 |
0 |
T29 |
16140 |
14520 |
0 |
0 |
T30 |
28360 |
27290 |
0 |
0 |
T31 |
15120 |
14820 |
0 |
0 |
T32 |
18410 |
18150 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
42463 |
0 |
0 |
T1 |
2688 |
19 |
0 |
0 |
T2 |
0 |
34 |
0 |
0 |
T3 |
0 |
113 |
0 |
0 |
T9 |
0 |
35 |
0 |
0 |
T10 |
0 |
92 |
0 |
0 |
T11 |
0 |
89 |
0 |
0 |
T12 |
0 |
70 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
60 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
110 |
0 |
0 |
T50 |
0 |
88 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77304370 |
72575152 |
0 |
0 |
T1 |
43028 |
16042 |
0 |
0 |
T4 |
7431 |
7241 |
0 |
0 |
T5 |
3759 |
3528 |
0 |
0 |
T6 |
4587 |
4507 |
0 |
0 |
T27 |
2064 |
1998 |
0 |
0 |
T28 |
3758 |
3569 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
6603 |
6468 |
0 |
0 |
T32 |
7682 |
7574 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
11937 |
0 |
0 |
T1 |
2688 |
8 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
32 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
18 |
0 |
0 |
T50 |
0 |
36 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
61583 |
0 |
0 |
T1 |
2688 |
19 |
0 |
0 |
T2 |
0 |
52 |
0 |
0 |
T3 |
0 |
162 |
0 |
0 |
T9 |
0 |
48 |
0 |
0 |
T10 |
0 |
132 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T12 |
0 |
98 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
89 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
155 |
0 |
0 |
T50 |
0 |
124 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
37650258 |
36464198 |
0 |
0 |
T1 |
14769 |
8021 |
0 |
0 |
T4 |
3648 |
3620 |
0 |
0 |
T5 |
1812 |
1764 |
0 |
0 |
T6 |
2473 |
2452 |
0 |
0 |
T27 |
1078 |
1064 |
0 |
0 |
T28 |
1846 |
1784 |
0 |
0 |
T29 |
818 |
804 |
0 |
0 |
T30 |
1378 |
1364 |
0 |
0 |
T31 |
3282 |
3234 |
0 |
0 |
T32 |
4253 |
4232 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
11937 |
0 |
0 |
T1 |
2688 |
8 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
32 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
18 |
0 |
0 |
T50 |
0 |
36 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
98622 |
0 |
0 |
T1 |
2688 |
19 |
0 |
0 |
T2 |
0 |
94 |
0 |
0 |
T3 |
0 |
262 |
0 |
0 |
T9 |
0 |
79 |
0 |
0 |
T10 |
0 |
211 |
0 |
0 |
T11 |
0 |
177 |
0 |
0 |
T12 |
0 |
140 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
146 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
261 |
0 |
0 |
T50 |
0 |
176 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18824682 |
18231761 |
0 |
0 |
T1 |
7384 |
4010 |
0 |
0 |
T4 |
1824 |
1810 |
0 |
0 |
T5 |
906 |
882 |
0 |
0 |
T6 |
1236 |
1225 |
0 |
0 |
T27 |
537 |
530 |
0 |
0 |
T28 |
923 |
892 |
0 |
0 |
T29 |
409 |
402 |
0 |
0 |
T30 |
689 |
682 |
0 |
0 |
T31 |
1641 |
1617 |
0 |
0 |
T32 |
2123 |
2113 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
11937 |
0 |
0 |
T1 |
2688 |
8 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
32 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
18 |
0 |
0 |
T50 |
0 |
36 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
42109 |
0 |
0 |
T1 |
2688 |
19 |
0 |
0 |
T2 |
0 |
32 |
0 |
0 |
T3 |
0 |
112 |
0 |
0 |
T9 |
0 |
34 |
0 |
0 |
T10 |
0 |
91 |
0 |
0 |
T11 |
0 |
86 |
0 |
0 |
T12 |
0 |
70 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
60 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
92 |
0 |
0 |
T50 |
0 |
88 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
85806994 |
80722448 |
0 |
0 |
T1 |
44823 |
16711 |
0 |
0 |
T4 |
7741 |
7544 |
0 |
0 |
T5 |
3916 |
3676 |
0 |
0 |
T6 |
4779 |
4695 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
4338 |
4141 |
0 |
0 |
T29 |
1682 |
1513 |
0 |
0 |
T30 |
2955 |
2843 |
0 |
0 |
T31 |
6878 |
6738 |
0 |
0 |
T32 |
8002 |
7890 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
11937 |
0 |
0 |
T1 |
2688 |
8 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
32 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
28 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
18 |
0 |
0 |
T50 |
0 |
36 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T9,T10,T11 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T9,T10,T11 |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_en_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
59336 |
0 |
0 |
T1 |
2688 |
14 |
0 |
0 |
T2 |
0 |
52 |
0 |
0 |
T3 |
0 |
116 |
0 |
0 |
T9 |
0 |
49 |
0 |
0 |
T10 |
0 |
158 |
0 |
0 |
T11 |
0 |
122 |
0 |
0 |
T12 |
0 |
63 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
88 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
106 |
0 |
0 |
T50 |
0 |
78 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
41015274 |
38586508 |
0 |
0 |
T1 |
21515 |
8021 |
0 |
0 |
T4 |
3716 |
3621 |
0 |
0 |
T5 |
1880 |
1765 |
0 |
0 |
T6 |
2293 |
2254 |
0 |
0 |
T27 |
1032 |
999 |
0 |
0 |
T28 |
1923 |
1829 |
0 |
0 |
T29 |
807 |
726 |
0 |
0 |
T30 |
1418 |
1364 |
0 |
0 |
T31 |
3302 |
3235 |
0 |
0 |
T32 |
3841 |
3787 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
11411 |
0 |
0 |
T1 |
2688 |
4 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
16 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
11 |
0 |
0 |
T50 |
0 |
18 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
64802 |
0 |
0 |
T1 |
2688 |
39 |
0 |
0 |
T2 |
0 |
32 |
0 |
0 |
T3 |
0 |
226 |
0 |
0 |
T9 |
0 |
34 |
0 |
0 |
T10 |
0 |
92 |
0 |
0 |
T11 |
0 |
91 |
0 |
0 |
T12 |
0 |
139 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
60 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
220 |
0 |
0 |
T50 |
0 |
178 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
77304370 |
72575152 |
0 |
0 |
T1 |
43028 |
16042 |
0 |
0 |
T4 |
7431 |
7241 |
0 |
0 |
T5 |
3759 |
3528 |
0 |
0 |
T6 |
4587 |
4507 |
0 |
0 |
T27 |
2064 |
1998 |
0 |
0 |
T28 |
3758 |
3569 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
6603 |
6468 |
0 |
0 |
T32 |
7682 |
7574 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
17907 |
0 |
0 |
T1 |
2688 |
16 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
56 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
36 |
0 |
0 |
T50 |
0 |
72 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
93927 |
0 |
0 |
T1 |
2688 |
39 |
0 |
0 |
T2 |
0 |
53 |
0 |
0 |
T3 |
0 |
324 |
0 |
0 |
T9 |
0 |
46 |
0 |
0 |
T10 |
0 |
132 |
0 |
0 |
T11 |
0 |
124 |
0 |
0 |
T12 |
0 |
195 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
89 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
310 |
0 |
0 |
T50 |
0 |
250 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
37650258 |
36464198 |
0 |
0 |
T1 |
14769 |
8021 |
0 |
0 |
T4 |
3648 |
3620 |
0 |
0 |
T5 |
1812 |
1764 |
0 |
0 |
T6 |
2473 |
2452 |
0 |
0 |
T27 |
1078 |
1064 |
0 |
0 |
T28 |
1846 |
1784 |
0 |
0 |
T29 |
818 |
804 |
0 |
0 |
T30 |
1378 |
1364 |
0 |
0 |
T31 |
3282 |
3234 |
0 |
0 |
T32 |
4253 |
4232 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
17923 |
0 |
0 |
T1 |
2688 |
16 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
56 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
36 |
0 |
0 |
T50 |
0 |
72 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
151248 |
0 |
0 |
T1 |
2688 |
39 |
0 |
0 |
T2 |
0 |
93 |
0 |
0 |
T3 |
0 |
520 |
0 |
0 |
T9 |
0 |
73 |
0 |
0 |
T10 |
0 |
212 |
0 |
0 |
T11 |
0 |
179 |
0 |
0 |
T12 |
0 |
278 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
147 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
534 |
0 |
0 |
T50 |
0 |
356 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
18824682 |
18231761 |
0 |
0 |
T1 |
7384 |
4010 |
0 |
0 |
T4 |
1824 |
1810 |
0 |
0 |
T5 |
906 |
882 |
0 |
0 |
T6 |
1236 |
1225 |
0 |
0 |
T27 |
537 |
530 |
0 |
0 |
T28 |
923 |
892 |
0 |
0 |
T29 |
409 |
402 |
0 |
0 |
T30 |
689 |
682 |
0 |
0 |
T31 |
1641 |
1617 |
0 |
0 |
T32 |
2123 |
2113 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
17970 |
0 |
0 |
T1 |
2688 |
16 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
56 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
36 |
0 |
0 |
T50 |
0 |
72 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
64018 |
0 |
0 |
T1 |
2688 |
39 |
0 |
0 |
T2 |
0 |
32 |
0 |
0 |
T3 |
0 |
223 |
0 |
0 |
T9 |
0 |
33 |
0 |
0 |
T10 |
0 |
92 |
0 |
0 |
T11 |
0 |
88 |
0 |
0 |
T12 |
0 |
139 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
59 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
179 |
0 |
0 |
T50 |
0 |
178 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
85806994 |
80722448 |
0 |
0 |
T1 |
44823 |
16711 |
0 |
0 |
T4 |
7741 |
7544 |
0 |
0 |
T5 |
3916 |
3676 |
0 |
0 |
T6 |
4779 |
4695 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
4338 |
4141 |
0 |
0 |
T29 |
1682 |
1513 |
0 |
0 |
T30 |
2955 |
2843 |
0 |
0 |
T31 |
6878 |
6738 |
0 |
0 |
T32 |
8002 |
7890 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
17943 |
0 |
0 |
T1 |
2688 |
16 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
64 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
56 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
36 |
0 |
0 |
T50 |
0 |
72 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
64
65 1/1 assign src_req = src_we_i | src_re_i;
Tests: T1 T2 T3
66
67 // busy indication back-pressures upstream if the register is accessed
68 // again. The busy indication is also used as a "commit" indication for
69 // resolving software and hardware write conflicts
70 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
71 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
72 1/1 src_busy_q <= '0;
Tests: T4 T5 T6
73 1/1 end else if (src_req) begin
Tests: T4 T5 T6
74 1/1 src_busy_q <= 1'b1;
Tests: T1 T2 T3
75 1/1 end else if (src_ack) begin
Tests: T4 T5 T6
76 1/1 src_busy_q <= 1'b0;
Tests: T1 T2 T3
77 end
MISSING_ELSE
78 end
79
80 // A src_ack should only be sent if there was a src_req.
81 // src_busy_q asserts whenever there is a src_req. By association,
82 // whenever src_ack is seen, then src_busy must be high.
83 `ASSERT(SrcAckBusyChk_A, src_ack |-> src_busy_q, clk_src_i, !rst_src_ni)
84
85 1/1 assign src_busy_o = src_busy_q;
Tests: T1 T2 T3
86
87 // src_q acts as both the write holding register and the software read back
88 // register.
89 // When software performs a write, the write data is captured in src_q for
90 // CDC purposes. When not performing a write, the src_q reflects the most recent
91 // hardware value. For registers with no hardware access, this is simply the
92 // the value programmed by software (or in the case R1C, W1C etc) the value after
93 // the operation. For registers with hardware access, this reflects a potentially
94 // delayed version of the real value, as the software facing updates lag real
95 // time updates.
96 //
97 // To resolve software and hardware conflicts, the process is as follows:
98 // When software issues a write, this module asserts "busy". While busy,
99 // src_q does not take on destination value updates. Since the
100 // logic has committed to updating based on software command, there is an irreversible
101 // window from which hardware writes are ignored. Once the busy window completes,
102 // the cdc portion then begins sampling once more.
103 //
104 // This is consistent with prim_subreg_arb where during software / hardware conflicts,
105 // software is always prioritized. The main difference is the conflict resolution window
106 // is now larger instead of just one destination clock cycle.
107
108 logic busy;
109 1/1 assign busy = src_busy_q & !src_ack;
Tests: T1 T2 T3
110
111 // This is the current destination value
112 logic [DataWidth-1:0] dst_qs;
113 logic src_update;
114 always_ff @(posedge clk_src_i or negedge rst_src_ni) begin
115 1/1 if (!rst_src_ni) begin
Tests: T4 T5 T6
116 1/1 src_q <= ResetVal;
Tests: T4 T5 T6
117 1/1 txn_bits_q <= '0;
Tests: T4 T5 T6
118 1/1 end else if (src_req) begin
Tests: T4 T5 T6
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 1/1 src_q <= src_wd_i & BitMask;
Tests: T1 T2 T3
124 1/1 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
Tests: T1 T2 T3
125 1/1 end else if (src_busy_q && src_ack || src_update && !busy) begin
Tests: T4 T5 T6
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 1/1 src_q <= dst_qs;
Tests: T1 T2 T3
135 1/1 txn_bits_q <= '0;
Tests: T1 T2 T3
136 end
MISSING_ELSE
137 end
138
139 // The current design (tlul_adapter_reg) does not spit out a request if the destination it chooses
140 // (decoded from address) is busy. So this creates a situation in the current design where
141 // src_req_i and busy can never be high at the same time.
142 // While the code above could be coded directly to be expressed as `src_req & !busy`, which makes
143 // the intent clearer, it ends up causing coverage holes from the tool's perspective since that
144 // condition cannot be met.
145 // Thus we add an assertion here to ensure the condition is always satisfied.
146 `ASSERT(BusySrcReqChk_A, busy |-> !src_req, clk_src_i, !rst_src_ni)
147
148 // reserved bits are not used
149 logic unused_wd;
150 1/1 assign unused_wd = ^src_wd_i;
Tests: T4 T5 T6
151
152 // src_q is always updated in the clk_src domain.
153 // when performing an update to the destination domain, it is guaranteed
154 // to not change by protocol.
155 1/1 assign src_qs_o = src_q;
Tests: T1 T2 T3
156 1/1 assign dst_wd_o = src_q;
Tests: T1 T2 T3
157
158 ////////////////////////////
159 // CDC handling
160 ////////////////////////////
161
162 logic dst_req_from_src;
163 logic dst_req;
164
165
166 // the software transaction is pulse synced across the domain.
167 // the prim_reg_cdc_arb module handles conflicts with ongoing hardware updates.
168 prim_pulse_sync u_src_to_dst_req (
169 .clk_src_i,
170 .rst_src_ni,
171 .clk_dst_i,
172 .rst_dst_ni,
173 .src_pulse_i(src_req),
174 .dst_pulse_o(dst_req_from_src)
175 );
176
177 prim_reg_cdc_arb #(
178 .DataWidth(DataWidth),
179 .ResetVal(ResetVal),
180 .DstWrReq(DstWrReq)
181 ) u_arb (
182 .clk_src_i,
183 .rst_src_ni,
184 .clk_dst_i,
185 .rst_dst_ni,
186 .src_ack_o(src_ack),
187 .src_update_o(src_update),
188 .dst_req_i(dst_req_from_src),
189 .dst_req_o(dst_req),
190 .dst_update_i,
191 .dst_ds_i,
192 .dst_qs_i,
193 .dst_qs_o(dst_qs)
194 );
195
196
197 // Each is valid only when destination request pulse is high; this is important in not propagating
198 // the internal assertion of 'dst_req' by the 'prim_pulse_sync' channel when just one domain is
199 // reset.
200 1/1 assign {dst_we_o, dst_re_o, dst_regwen_o} = txn_bits_q & {TxnWidth{dst_req}};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Total | Covered | Percent |
Conditions | 12 | 11 | 91.67 |
Logical | 12 | 11 | 91.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Covered | T1,T3,T12 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T4,T5,T6 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
71 if (!rst_src_ni) begin
-1-
72 src_busy_q <= '0;
==>
73 end else if (src_req) begin
-2-
74 src_busy_q <= 1'b1;
==>
75 end else if (src_ack) begin
-3-
76 src_busy_q <= 1'b0;
==>
77 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
115 if (!rst_src_ni) begin
-1-
116 src_q <= ResetVal;
==>
117 txn_bits_q <= '0;
118 end else if (src_req) begin
-2-
119 // See assertion below
120 // At the beginning of a software initiated transaction, the following
121 // values are captured in the src_q/txn_bits_q flops to ensure they cannot
122 // change for the duration of the synchronization operation.
123 src_q <= src_wd_i & BitMask;
==>
124 txn_bits_q <= {src_we_i, src_re_i, src_regwen_i};
125 end else if (src_busy_q && src_ack || src_update && !busy) begin
-3-
126 // sample data whenever a busy transaction finishes OR
127 // when an update pulse is seen.
128 // TODO: We should add a cover group to test different sync timings
129 // between src_ack and src_update. ie. there can be 3 scenarios:
130 // 1. update one cycle before ack
131 // 2. ack one cycle before update
132 // 3. update / ack on the same cycle
133 // During all 3 cases the read data should be correct
134 src_q <= dst_qs;
==>
135 txn_bits_q <= '0;
136 end
MISSING_ELSE
==>
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T4,T5,T6 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T4,T5,T6 |
Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
93581 |
0 |
0 |
T1 |
2688 |
39 |
0 |
0 |
T2 |
0 |
55 |
0 |
0 |
T3 |
0 |
340 |
0 |
0 |
T9 |
0 |
47 |
0 |
0 |
T10 |
0 |
158 |
0 |
0 |
T11 |
0 |
123 |
0 |
0 |
T12 |
0 |
190 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
88 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
291 |
0 |
0 |
T50 |
0 |
250 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
41015274 |
38586508 |
0 |
0 |
T1 |
21515 |
8021 |
0 |
0 |
T4 |
3716 |
3621 |
0 |
0 |
T5 |
1880 |
1765 |
0 |
0 |
T6 |
2293 |
2254 |
0 |
0 |
T27 |
1032 |
999 |
0 |
0 |
T28 |
1923 |
1829 |
0 |
0 |
T29 |
807 |
726 |
0 |
0 |
T30 |
1418 |
1364 |
0 |
0 |
T31 |
3302 |
3235 |
0 |
0 |
T32 |
3841 |
3787 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
17707 |
0 |
0 |
T1 |
2688 |
14 |
0 |
0 |
T2 |
0 |
6 |
0 |
0 |
T3 |
0 |
48 |
0 |
0 |
T9 |
0 |
10 |
0 |
0 |
T10 |
0 |
26 |
0 |
0 |
T11 |
0 |
34 |
0 |
0 |
T12 |
0 |
42 |
0 |
0 |
T32 |
1841 |
0 |
0 |
0 |
T38 |
0 |
16 |
0 |
0 |
T42 |
2031 |
0 |
0 |
0 |
T43 |
1744 |
0 |
0 |
0 |
T46 |
0 |
35 |
0 |
0 |
T50 |
0 |
70 |
0 |
0 |
T51 |
1589 |
0 |
0 |
0 |
T52 |
1289 |
0 |
0 |
0 |
T53 |
1044 |
0 |
0 |
0 |
T54 |
1781 |
0 |
0 |
0 |
T55 |
816 |
0 |
0 |
0 |
T56 |
2849 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
39391736 |
36193235 |
0 |
0 |
T1 |
2688 |
1006 |
0 |
0 |
T4 |
1702 |
1659 |
0 |
0 |
T5 |
978 |
918 |
0 |
0 |
T6 |
1146 |
1126 |
0 |
0 |
T27 |
2149 |
2081 |
0 |
0 |
T28 |
1156 |
1107 |
0 |
0 |
T29 |
1614 |
1452 |
0 |
0 |
T30 |
2836 |
2729 |
0 |
0 |
T31 |
1512 |
1482 |
0 |
0 |
T32 |
1841 |
1815 |
0 |
0 |