Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	115315131	432	0	0
StatusRise_A	115315131	432	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115315131	432	0	0
T1	8064	0	0	0
T23	0	9	0	0
T28	3468	11	0	0
T29	4842	0	0	0
T30	8508	0	0	0
T31	4536	0	0	0
T32	5523	0	0	0
T42	6093	0	0	0
T43	5232	0	0	0
T51	4767	0	0	0
T52	3867	0	0	0
T55	0	8	0	0
T64	0	15	0	0
T164	0	17	0	0
T180	0	1	0	0
T191	0	3	0	0
T199	0	14	0	0
T200	0	1	0	0
T201	0	2	0	0
T202	0	2	0	0
T203	0	3	0	0
T204	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	115315131	432	0	0
T1	8064	0	0	0
T23	0	9	0	0
T28	3468	11	0	0
T29	4842	0	0	0
T30	8508	0	0	0
T31	4536	0	0	0
T32	5523	0	0	0
T42	6093	0	0	0
T43	5232	0	0	0
T51	4767	0	0	0
T52	3867	0	0	0
T55	0	8	0	0
T64	0	15	0	0
T164	0	17	0	0
T180	0	1	0	0
T191	0	3	0	0
T199	0	14	0	0
T200	0	1	0	0
T201	0	2	0	0
T202	0	2	0	0
T203	0	3	0	0
T204	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38438377	146	0	0
StatusRise_A	38438377	146	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	146	0	0
T1	2688	0	0	0
T23	0	3	0	0
T28	1156	4	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T51	1589	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	5	0	0
T164	0	7	0	0
T180	0	1	0	0
T199	0	6	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	146	0	0
T1	2688	0	0	0
T23	0	3	0	0
T28	1156	4	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T51	1589	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	5	0	0
T164	0	7	0	0
T180	0	1	0	0
T199	0	6	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38438377	150	0	0
StatusRise_A	38438377	150	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	150	0	0
T1	2688	0	0	0
T23	0	3	0	0
T28	1156	3	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T51	1589	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	150	0	0
T1	2688	0	0	0
T23	0	3	0	0
T28	1156	3	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T51	1589	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38438377	136	0	0
StatusRise_A	38438377	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	136	0	0
T1	2688	0	0	0
T23	0	3	0	0
T28	1156	4	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T51	1589	0	0	0
T52	1289	0	0	0
T55	0	2	0	0
T64	0	4	0	0
T164	0	6	0	0
T191	0	1	0	0
T199	0	5	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38438377	136	0	0
T1	2688	0	0	0
T23	0	3	0	0
T28	1156	4	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	1512	0	0	0
T32	1841	0	0	0
T42	2031	0	0	0
T43	1744	0	0	0
T51	1589	0	0	0
T52	1289	0	0	0
T55	0	2	0	0
T64	0	4	0	0
T164	0	6	0	0
T191	0	1	0	0
T199	0	5	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0