Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	868974100	34385	0	0
CgEnOn_A	868974100	24596	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	868974100	34385	0	0
T1	457098	15	0	0
T4	47583	7	0	0
T5	24021	19	0	0
T6	29705	3	0	0
T23	0	15	0	0
T27	13307	3	0	0
T28	44774	31	0	0
T29	18206	3	0	0
T30	31750	11	0	0
T31	74206	6	0	0
T32	88056	3	0	0
T42	60349	0	0	0
T43	7954	0	0	0
T51	28341	1	0	0
T52	5815	0	0	0
T53	0	4	0	0
T55	0	18	0	0
T64	0	30	0	0
T164	0	20	0	0
T191	0	10	0	0
T199	0	15	0	0
T201	0	5	0	0
T202	0	5	0	0
T203	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	868974100	24596	0	0
T1	457098	0	0	0
T4	47583	4	0	0
T5	24021	16	0	0
T6	29705	0	0	0
T20	0	3	0	0
T23	0	15	0	0
T27	13307	0	0	0
T28	44774	28	0	0
T29	18206	0	0	0
T30	31750	8	0	0
T31	74206	3	0	0
T32	88056	0	0	0
T42	60349	0	0	0
T43	7954	0	0	0
T51	28341	4	0	0
T52	5815	8	0	0
T53	0	4	0	0
T55	0	27	0	0
T56	0	2	0	0
T64	0	48	0	0
T66	0	4	0	0
T74	0	19	0	0
T164	0	20	0	0
T191	0	10	0	0
T199	0	15	0	0
T201	0	5	0	0
T202	0	5	0	0
T203	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36214891	164	0	0
CgEnOn_A	36214891	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36214891	164	0	0
T1	14769	0	0	0
T23	0	3	0	0
T28	1846	3	0	0
T29	818	0	0	0
T30	1378	0	0	0
T31	3282	0	0	0
T32	4253	0	0	0
T42	6665	0	0	0
T43	781	0	0	0
T51	2923	0	0	0
T52	552	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36214891	164	0	0
T1	14769	0	0	0
T23	0	3	0	0
T28	1846	3	0	0
T29	818	0	0	0
T30	1378	0	0	0
T31	3282	0	0	0
T32	4253	0	0	0
T42	6665	0	0	0
T43	781	0	0	0
T51	2923	0	0	0
T52	552	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18106988	164	0	0
CgEnOn_A	18106988	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	164	0	0
T1	7384	0	0	0
T23	0	3	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T42	3332	0	0	0
T43	391	0	0	0
T51	1461	0	0	0
T52	276	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	164	0	0
T1	7384	0	0	0
T23	0	3	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T42	3332	0	0	0
T43	391	0	0	0
T51	1461	0	0	0
T52	276	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18106988	164	0	0
CgEnOn_A	18106988	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	164	0	0
T1	7384	0	0	0
T23	0	3	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T42	3332	0	0	0
T43	391	0	0	0
T51	1461	0	0	0
T52	276	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	164	0	0
T1	7384	0	0	0
T23	0	3	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T42	3332	0	0	0
T43	391	0	0	0
T51	1461	0	0	0
T52	276	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18106988	164	0	0
CgEnOn_A	18106988	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	164	0	0
T1	7384	0	0	0
T23	0	3	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T42	3332	0	0	0
T43	391	0	0	0
T51	1461	0	0	0
T52	276	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	164	0	0
T1	7384	0	0	0
T23	0	3	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T42	3332	0	0	0
T43	391	0	0	0
T51	1461	0	0	0
T52	276	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	74346096	164	0	0
CgEnOn_A	74346096	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74346096	164	0	0
T1	43028	0	0	0
T23	0	3	0	0
T28	3758	3	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	6603	0	0	0
T32	7682	0	0	0
T42	12192	0	0	0
T43	1675	0	0	0
T51	5870	0	0	0
T52	1238	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74346096	153	0	0
T1	43028	0	0	0
T23	0	3	0	0
T28	3758	3	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	6603	0	0	0
T32	7682	0	0	0
T42	12192	0	0	0
T43	1675	0	0	0
T51	5870	0	0	0
T52	1238	0	0	0
T55	0	3	0	0
T64	0	6	0	0
T164	0	4	0	0
T191	0	2	0	0
T199	0	3	0	0
T201	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82725328	150	0	0
CgEnOn_A	82725328	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	150	0	0
T1	44823	0	0	0
T23	0	3	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	0	0	0
T31	6878	0	0	0
T32	8002	0	0	0
T42	12700	0	0	0
T43	1744	0	0	0
T51	6115	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	5	0	0
T164	0	7	0	0
T180	0	1	0	0
T199	0	6	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	147	0	0
T1	44823	0	0	0
T23	0	3	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	0	0	0
T31	6878	0	0	0
T32	8002	0	0	0
T42	12700	0	0	0
T43	1744	0	0	0
T51	6115	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	5	0	0
T164	0	7	0	0
T180	0	1	0	0
T199	0	6	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82725328	150	0	0
CgEnOn_A	82725328	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	150	0	0
T1	44823	0	0	0
T23	0	3	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	0	0	0
T31	6878	0	0	0
T32	8002	0	0	0
T42	12700	0	0	0
T43	1744	0	0	0
T51	6115	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	5	0	0
T164	0	7	0	0
T180	0	1	0	0
T199	0	6	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	147	0	0
T1	44823	0	0	0
T23	0	3	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	0	0	0
T31	6878	0	0	0
T32	8002	0	0	0
T42	12700	0	0	0
T43	1744	0	0	0
T51	6115	0	0	0
T52	1289	0	0	0
T55	0	3	0	0
T64	0	5	0	0
T164	0	7	0	0
T180	0	1	0	0
T199	0	6	0	0
T200	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39536103	143	0	0
CgEnOn_A	39536103	136	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39536103	143	0	0
T1	21515	0	0	0
T23	0	3	0	0
T28	1923	4	0	0
T29	807	0	0	0
T30	1418	0	0	0
T31	3302	0	0	0
T32	3841	0	0	0
T42	6096	0	0	0
T43	837	0	0	0
T51	2935	0	0	0
T52	619	0	0	0
T55	0	2	0	0
T64	0	4	0	0
T164	0	6	0	0
T191	0	1	0	0
T199	0	5	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39536103	136	0	0
T1	21515	0	0	0
T23	0	3	0	0
T28	1923	4	0	0
T29	807	0	0	0
T30	1418	0	0	0
T31	3302	0	0	0
T32	3841	0	0	0
T42	6096	0	0	0
T43	837	0	0	0
T51	2935	0	0	0
T52	619	0	0	0
T55	0	2	0	0
T64	0	4	0	0
T164	0	6	0	0
T191	0	1	0	0
T199	0	5	0	0
T201	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T64
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	18106988	5632	0	0
CgEnOn_A	18106988	3200	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	5632	0	0
T1	7384	5	0	0
T4	1824	2	0	0
T5	906	7	0	0
T6	1236	1	0	0
T27	537	1	0	0
T28	923	4	0	0
T29	409	1	0	0
T30	689	1	0	0
T31	1641	1	0	0
T32	2123	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	18106988	3200	0	0
T1	7384	0	0	0
T4	1824	1	0	0
T5	906	6	0	0
T6	1236	0	0	0
T20	0	1	0	0
T27	537	0	0	0
T28	923	3	0	0
T29	409	0	0	0
T30	689	0	0	0
T31	1641	0	0	0
T32	2123	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	3	0	0
T64	0	6	0	0
T66	0	1	0	0
T74	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T64
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	36214891	5639	0	0
CgEnOn_A	36214891	3207	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36214891	5639	0	0
T1	14769	5	0	0
T4	3648	2	0	0
T5	1812	6	0	0
T6	2473	1	0	0
T27	1078	1	0	0
T28	1846	4	0	0
T29	818	1	0	0
T30	1378	1	0	0
T31	3282	1	0	0
T32	4253	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	36214891	3207	0	0
T1	14769	0	0	0
T4	3648	1	0	0
T5	1812	5	0	0
T6	2473	0	0	0
T20	0	1	0	0
T27	1078	0	0	0
T28	1846	3	0	0
T29	818	0	0	0
T30	1378	0	0	0
T31	3282	0	0	0
T32	4253	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T55	0	3	0	0
T64	0	6	0	0
T66	0	1	0	0
T74	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T64
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	74346096	5651	0	0
CgEnOn_A	74346096	3208	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74346096	5651	0	0
T1	43028	5	0	0
T4	7431	2	0	0
T5	3759	6	0	0
T6	4587	1	0	0
T27	2064	1	0	0
T28	3758	4	0	0
T29	1614	1	0	0
T30	2836	1	0	0
T31	6603	1	0	0
T32	7682	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	74346096	3208	0	0
T1	43028	0	0	0
T4	7431	1	0	0
T5	3759	5	0	0
T6	4587	0	0	0
T20	0	1	0	0
T27	2064	0	0	0
T28	3758	3	0	0
T29	1614	0	0	0
T30	2836	0	0	0
T31	6603	0	0	0
T32	7682	0	0	0
T51	0	1	0	0
T52	0	3	0	0
T55	0	3	0	0
T64	0	6	0	0
T66	0	1	0	0
T74	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T55,T64
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39536103	5604	0	0
CgEnOn_A	39536103	3158	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39536103	5604	0	0
T1	21515	5	0	0
T4	3716	2	0	0
T5	1880	5	0	0
T6	2293	1	0	0
T27	1032	1	0	0
T28	1923	5	0	0
T29	807	1	0	0
T30	1418	1	0	0
T31	3302	1	0	0
T32	3841	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39536103	3158	0	0
T1	21515	0	0	0
T4	3716	1	0	0
T5	1880	4	0	0
T6	2293	0	0	0
T20	0	1	0	0
T27	1032	0	0	0
T28	1923	4	0	0
T29	807	0	0	0
T30	1418	0	0	0
T31	3302	0	0	0
T32	3841	0	0	0
T51	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T64	0	4	0	0
T66	0	1	0	0
T74	0	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82725328	2648	0	0
CgEnOn_A	82725328	2645	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2648	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	8	0	0
T31	6878	3	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	4	0	0
T55	0	3	0	0
T56	0	2	0	0
T66	0	1	0	0
T76	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2645	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	8	0	0
T31	6878	3	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	4	0	0
T55	0	3	0	0
T56	0	2	0	0
T66	0	1	0	0
T76	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82725328	2606	0	0
CgEnOn_A	82725328	2603	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2606	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	9	0	0
T31	6878	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	4	0	0
T55	0	3	0	0
T56	0	8	0	0
T66	0	1	0	0
T76	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2603	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	9	0	0
T31	6878	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	4	0	0
T55	0	3	0	0
T56	0	8	0	0
T66	0	1	0	0
T76	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82725328	2732	0	0
CgEnOn_A	82725328	2729	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2732	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	7	0	0
T31	6878	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	3	0	0
T55	0	3	0	0
T56	0	9	0	0
T66	0	1	0	0
T76	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2729	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	7	0	0
T31	6878	4	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	3	0	0
T55	0	3	0	0
T56	0	9	0	0
T66	0	1	0	0
T76	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T28,T1,T55
1	0	Covered	T4,T30,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	82725328	2610	0	0
CgEnOn_A	82725328	2607	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2610	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	9	0	0
T31	6878	2	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	3	0	0
T56	0	5	0	0
T66	0	1	0	0
T76	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	82725328	2607	0	0
T1	44823	0	0	0
T4	7741	1	0	0
T5	3916	0	0	0
T6	4779	0	0	0
T27	2149	0	0	0
T28	4338	4	0	0
T29	1682	0	0	0
T30	2955	9	0	0
T31	6878	2	0	0
T32	8002	0	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	3	0	0
T56	0	5	0	0
T66	0	1	0	0
T76	0	5	0	0