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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 1010
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T1001 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.2079781462 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 14170871 ps
T1002 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2398568823 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 14830781 ps
T1003 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.776668851 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 13893355 ps
T1004 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.2689790554 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 33210032 ps
T1005 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.4191100342 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 14527443 ps
T1006 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.723394315 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 37254128 ps
T1007 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1567095885 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 12120967 ps
T1008 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.2792345396 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 37403581 ps
T1009 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.2146110406 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 13358532 ps
T1010 /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.1757900399 Sep 04 02:03:51 AM UTC 24 Sep 04 02:03:53 AM UTC 24 47604556 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.429826521
Short name T1
Test name
Test status
Simulation time 448252373 ps
CPU time 1.96 seconds
Started Sep 04 01:59:15 AM UTC 24
Finished Sep 04 01:59:18 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429826521 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.429826521
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.337342284
Short name T11
Test name
Test status
Simulation time 2013032606 ps
CPU time 9.05 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 01:59:11 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337342284 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.337342284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2866251687
Short name T42
Test name
Test status
Simulation time 127033009 ps
CPU time 1.88 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:02 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866251687
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.2866251687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.4020431197
Short name T4
Test name
Test status
Simulation time 77433463 ps
CPU time 1.04 seconds
Started Sep 04 01:58:58 AM UTC 24
Finished Sep 04 01:59:00 AM UTC 24
Peak memory 209652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020431197 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.4020431197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.1664480711
Short name T35
Test name
Test status
Simulation time 4954671898 ps
CPU time 53.04 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:57 AM UTC 24
Peak memory 220296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664480711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.1664480711
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4216293465
Short name T86
Test name
Test status
Simulation time 114285198 ps
CPU time 2.43 seconds
Started Sep 04 02:03:20 AM UTC 24
Finished Sep 04 02:03:24 AM UTC 24
Peak memory 222036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216293
465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.4216293465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.1086414211
Short name T57
Test name
Test status
Simulation time 1815698095 ps
CPU time 14.25 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:19 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086414211 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.1086414211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.4285047547
Short name T48
Test name
Test status
Simulation time 678542425 ps
CPU time 6.18 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 01:59:13 AM UTC 24
Peak memory 241408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285047547 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.4285047547
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.4043523509
Short name T77
Test name
Test status
Simulation time 45018980 ps
CPU time 1.42 seconds
Started Sep 04 01:59:04 AM UTC 24
Finished Sep 04 01:59:07 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043523509 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.4043523509
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.986753470
Short name T28
Test name
Test status
Simulation time 46290126 ps
CPU time 1.09 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986753470 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.986753470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.539635867
Short name T29
Test name
Test status
Simulation time 16845068 ps
CPU time 1.02 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539635867 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.539635867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.543690147
Short name T70
Test name
Test status
Simulation time 5296147138 ps
CPU time 36.26 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 01:59:38 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543690147 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.543690147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.4149489600
Short name T120
Test name
Test status
Simulation time 312199519 ps
CPU time 3.59 seconds
Started Sep 04 02:03:11 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 212348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149489600 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.4149489600
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2251179571
Short name T140
Test name
Test status
Simulation time 500707078 ps
CPU time 4.65 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 213004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2251179571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_
errors_with_csr_rw.2251179571
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.2561996116
Short name T69
Test name
Test status
Simulation time 3189605355 ps
CPU time 24.56 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:29 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561996116 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.2561996116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.1782196466
Short name T39
Test name
Test status
Simulation time 1085133166 ps
CPU time 22.52 seconds
Started Sep 04 01:59:11 AM UTC 24
Finished Sep 04 01:59:34 AM UTC 24
Peak memory 222156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782196466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1782196466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.3911043619
Short name T67
Test name
Test status
Simulation time 20096059 ps
CPU time 1.12 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:05 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911043619 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.3911043619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.3893544693
Short name T46
Test name
Test status
Simulation time 686593390 ps
CPU time 6.01 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 01:59:13 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893544693 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3893544693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1107956898
Short name T134
Test name
Test status
Simulation time 1194062058 ps
CPU time 5.42 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:38 AM UTC 24
Peak memory 212352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107956898 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.1107956898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2199449335
Short name T143
Test name
Test status
Simulation time 984183842 ps
CPU time 3.84 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:32 AM UTC 24
Peak memory 212492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199449
335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.2199449335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1226111399
Short name T113
Test name
Test status
Simulation time 24930646 ps
CPU time 1.1 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 01:59:08 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226111399 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.1226111399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.2164804279
Short name T8
Test name
Test status
Simulation time 256038476 ps
CPU time 2.1 seconds
Started Sep 04 02:03:00 AM UTC 24
Finished Sep 04 02:03:03 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164804279 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2164804279
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.3854290720
Short name T298
Test name
Test status
Simulation time 2382442988 ps
CPU time 19.59 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 211028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854290720 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3854290720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2275839489
Short name T135
Test name
Test status
Simulation time 93696206 ps
CPU time 2.18 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 212468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275839489 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.2275839489
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1828251762
Short name T103
Test name
Test status
Simulation time 196797281 ps
CPU time 2.66 seconds
Started Sep 04 02:03:12 AM UTC 24
Finished Sep 04 02:03:15 AM UTC 24
Peak memory 212136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828251762 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.1828251762
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.2663308026
Short name T63
Test name
Test status
Simulation time 405663986 ps
CPU time 3.45 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 01:59:05 AM UTC 24
Peak memory 242816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663308026 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.2663308026
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1481501498
Short name T141
Test name
Test status
Simulation time 150259320 ps
CPU time 1.42 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481501
498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.1481501498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.674931552
Short name T154
Test name
Test status
Simulation time 55204064 ps
CPU time 1.72 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:37 AM UTC 24
Peak memory 228156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=674931552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_
errors_with_csr_rw.674931552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2162119550
Short name T82
Test name
Test status
Simulation time 65423814 ps
CPU time 1.47 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162119
550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.2162119550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.3854136725
Short name T130
Test name
Test status
Simulation time 418936185 ps
CPU time 3.83 seconds
Started Sep 04 02:03:20 AM UTC 24
Finished Sep 04 02:03:25 AM UTC 24
Peak memory 212276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854136725 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.3854136725
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.1263563742
Short name T271
Test name
Test status
Simulation time 585071924 ps
CPU time 6.64 seconds
Started Sep 04 01:59:57 AM UTC 24
Finished Sep 04 02:00:05 AM UTC 24
Peak memory 210684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263563742 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1263563742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2398993457
Short name T863
Test name
Test status
Simulation time 145315410 ps
CPU time 3.73 seconds
Started Sep 04 02:03:12 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 212660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398993457 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.2398993457
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1862161848
Short name T126
Test name
Test status
Simulation time 19835656 ps
CPU time 1.04 seconds
Started Sep 04 02:03:12 AM UTC 24
Finished Sep 04 02:03:14 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862161848 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.1862161848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1721278286
Short name T861
Test name
Test status
Simulation time 100943363 ps
CPU time 1.89 seconds
Started Sep 04 02:03:13 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1721278286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_csr_mem_rw_with_rand_reset.1721278286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.148689886
Short name T127
Test name
Test status
Simulation time 74062741 ps
CPU time 1.41 seconds
Started Sep 04 02:03:12 AM UTC 24
Finished Sep 04 02:03:14 AM UTC 24
Peak memory 212228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148689886 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.148689886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.1891401532
Short name T858
Test name
Test status
Simulation time 13235187 ps
CPU time 1.01 seconds
Started Sep 04 02:03:12 AM UTC 24
Finished Sep 04 02:03:14 AM UTC 24
Peak memory 210964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891401532 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.1891401532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.4104483057
Short name T104
Test name
Test status
Simulation time 32455681 ps
CPU time 1.55 seconds
Started Sep 04 02:03:13 AM UTC 24
Finished Sep 04 02:03:15 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104
483057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.4104483057
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.180200156
Short name T78
Test name
Test status
Simulation time 88271072 ps
CPU time 2.31 seconds
Started Sep 04 02:03:11 AM UTC 24
Finished Sep 04 02:03:15 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802001
56 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.180200156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4186105631
Short name T79
Test name
Test status
Simulation time 141956594 ps
CPU time 3.01 seconds
Started Sep 04 02:03:11 AM UTC 24
Finished Sep 04 02:03:15 AM UTC 24
Peak memory 222232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4186105631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_
errors_with_csr_rw.4186105631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.506147256
Short name T860
Test name
Test status
Simulation time 40850743 ps
CPU time 3.35 seconds
Started Sep 04 02:03:11 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 212792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506147256 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.506147256
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1632666201
Short name T107
Test name
Test status
Simulation time 63724702 ps
CPU time 1.41 seconds
Started Sep 04 02:03:16 AM UTC 24
Finished Sep 04 02:03:18 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1632666201 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.1632666201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3966696038
Short name T891
Test name
Test status
Simulation time 1070817791 ps
CPU time 9.96 seconds
Started Sep 04 02:03:16 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 212340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966696038 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.3966696038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1927359470
Short name T865
Test name
Test status
Simulation time 58874429 ps
CPU time 0.98 seconds
Started Sep 04 02:03:15 AM UTC 24
Finished Sep 04 02:03:17 AM UTC 24
Peak memory 212164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927359470 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.1927359470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2344556918
Short name T868
Test name
Test status
Simulation time 45812970 ps
CPU time 1.59 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:19 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2344556918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_csr_mem_rw_with_rand_reset.2344556918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.9487003
Short name T105
Test name
Test status
Simulation time 64686453 ps
CPU time 1.02 seconds
Started Sep 04 02:03:15 AM UTC 24
Finished Sep 04 02:03:17 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9487003 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.9487003
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.3486867958
Short name T862
Test name
Test status
Simulation time 27078206 ps
CPU time 1.07 seconds
Started Sep 04 02:03:14 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486867958 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.3486867958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1955323697
Short name T106
Test name
Test status
Simulation time 104354000 ps
CPU time 1.36 seconds
Started Sep 04 02:03:16 AM UTC 24
Finished Sep 04 02:03:18 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955
323697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.1955323697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.160455709
Short name T80
Test name
Test status
Simulation time 68666033 ps
CPU time 1.8 seconds
Started Sep 04 02:03:14 AM UTC 24
Finished Sep 04 02:03:17 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604557
09 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.160455709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3944023682
Short name T83
Test name
Test status
Simulation time 145417134 ps
CPU time 3.49 seconds
Started Sep 04 02:03:14 AM UTC 24
Finished Sep 04 02:03:19 AM UTC 24
Peak memory 212764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3944023682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_
errors_with_csr_rw.3944023682
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.200484151
Short name T864
Test name
Test status
Simulation time 73033310 ps
CPU time 1.65 seconds
Started Sep 04 02:03:14 AM UTC 24
Finished Sep 04 02:03:17 AM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200484151 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.200484151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2523461534
Short name T121
Test name
Test status
Simulation time 222105287 ps
CPU time 2.86 seconds
Started Sep 04 02:03:14 AM UTC 24
Finished Sep 04 02:03:18 AM UTC 24
Peak memory 212424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523461534 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.2523461534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.90014255
Short name T918
Test name
Test status
Simulation time 26552339 ps
CPU time 1.11 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=90014255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 10.clkmgr_csr_mem_rw_with_rand_reset.90014255
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1719511657
Short name T916
Test name
Test status
Simulation time 15395407 ps
CPU time 0.85 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719511657 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.1719511657
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.3188883666
Short name T915
Test name
Test status
Simulation time 29882346 ps
CPU time 0.71 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188883666 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.3188883666
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3572086221
Short name T917
Test name
Test status
Simulation time 83260326 ps
CPU time 1 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572
086221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.3572086221
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2444309550
Short name T156
Test name
Test status
Simulation time 275263813 ps
CPU time 3.06 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:35 AM UTC 24
Peak memory 212740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2444309550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg
_errors_with_csr_rw.2444309550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.1117565276
Short name T920
Test name
Test status
Simulation time 56648942 ps
CPU time 1.72 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:34 AM UTC 24
Peak memory 211940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117565276 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.1117565276
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1276523038
Short name T926
Test name
Test status
Simulation time 39827463 ps
CPU time 1.17 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1276523038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_csr_mem_rw_with_rand_reset.1276523038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.1851924232
Short name T921
Test name
Test status
Simulation time 56258652 ps
CPU time 0.9 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:35 AM UTC 24
Peak memory 212224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851924232 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.1851924232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.2260027575
Short name T923
Test name
Test status
Simulation time 116890842 ps
CPU time 0.97 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:35 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260027575 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.2260027575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3277638305
Short name T931
Test name
Test status
Simulation time 103562775 ps
CPU time 1.59 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277
638305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.3277638305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1745170880
Short name T149
Test name
Test status
Simulation time 878894559 ps
CPU time 3.5 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 212676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745170
880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.1745170880
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3647403537
Short name T155
Test name
Test status
Simulation time 148340782 ps
CPU time 1.66 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:34 AM UTC 24
Peak memory 211580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3647403537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg
_errors_with_csr_rw.3647403537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.230059947
Short name T935
Test name
Test status
Simulation time 443737497 ps
CPU time 3.79 seconds
Started Sep 04 02:03:31 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 212720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230059947 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.230059947
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2151048206
Short name T930
Test name
Test status
Simulation time 139757119 ps
CPU time 1.66 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151048206 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.2151048206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3544066925
Short name T933
Test name
Test status
Simulation time 38076372 ps
CPU time 1.37 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3544066925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.clkmgr_csr_mem_rw_with_rand_reset.3544066925
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.3095446205
Short name T927
Test name
Test status
Simulation time 25984138 ps
CPU time 1.01 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095446205 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.3095446205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.664389948
Short name T925
Test name
Test status
Simulation time 13520782 ps
CPU time 0.8 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:35 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664389948 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.664389948
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1022896444
Short name T929
Test name
Test status
Simulation time 29260855 ps
CPU time 1.1 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022
896444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.1022896444
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.702610842
Short name T928
Test name
Test status
Simulation time 55553045 ps
CPU time 1.31 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7026108
42 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.702610842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.829424392
Short name T150
Test name
Test status
Simulation time 154439364 ps
CPU time 2.67 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:37 AM UTC 24
Peak memory 221984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=829424392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_
errors_with_csr_rw.829424392
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.2493134331
Short name T932
Test name
Test status
Simulation time 81516355 ps
CPU time 1.55 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493134331 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.2493134331
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2013999939
Short name T124
Test name
Test status
Simulation time 87862059 ps
CPU time 1.94 seconds
Started Sep 04 02:03:33 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 211876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013999939 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.2013999939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.4229163046
Short name T943
Test name
Test status
Simulation time 130033192 ps
CPU time 1.14 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4229163046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_csr_mem_rw_with_rand_reset.4229163046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.1889025232
Short name T940
Test name
Test status
Simulation time 175943946 ps
CPU time 1.1 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:39 AM UTC 24
Peak memory 211768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889025232 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.1889025232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.2068544651
Short name T938
Test name
Test status
Simulation time 15118473 ps
CPU time 0.65 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:39 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068544651 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.2068544651
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4141555952
Short name T942
Test name
Test status
Simulation time 38232390 ps
CPU time 1.04 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:39 AM UTC 24
Peak memory 211928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141
555952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.4141555952
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.4294381135
Short name T934
Test name
Test status
Simulation time 77270372 ps
CPU time 1.41 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:36 AM UTC 24
Peak memory 228352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4294381
135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.4294381135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.1486345895
Short name T936
Test name
Test status
Simulation time 261007279 ps
CPU time 2.53 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:38 AM UTC 24
Peak memory 212384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486345895 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.1486345895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1873612406
Short name T125
Test name
Test status
Simulation time 200807678 ps
CPU time 2.63 seconds
Started Sep 04 02:03:34 AM UTC 24
Finished Sep 04 02:03:38 AM UTC 24
Peak memory 212744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1873612406 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.1873612406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.3095790702
Short name T951
Test name
Test status
Simulation time 158845311 ps
CPU time 1.68 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3095790702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_csr_mem_rw_with_rand_reset.3095790702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.1092144606
Short name T944
Test name
Test status
Simulation time 18228731 ps
CPU time 0.92 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092144606 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.1092144606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.3798564539
Short name T939
Test name
Test status
Simulation time 12578217 ps
CPU time 0.69 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:39 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798564539 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.3798564539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.397330066
Short name T947
Test name
Test status
Simulation time 103709478 ps
CPU time 1.18 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973
30066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.397330066
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.4132108800
Short name T961
Test name
Test status
Simulation time 1059048913 ps
CPU time 3.45 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:42 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132108
800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.4132108800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1150746106
Short name T949
Test name
Test status
Simulation time 233483850 ps
CPU time 1.8 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 221236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1150746106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg
_errors_with_csr_rw.1150746106
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.2106144409
Short name T959
Test name
Test status
Simulation time 205677660 ps
CPU time 2.88 seconds
Started Sep 04 02:03:37 AM UTC 24
Finished Sep 04 02:03:42 AM UTC 24
Peak memory 212764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106144409 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.2106144409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3006613973
Short name T950
Test name
Test status
Simulation time 82235139 ps
CPU time 1.28 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3006613973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_csr_mem_rw_with_rand_reset.3006613973
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.1818983470
Short name T948
Test name
Test status
Simulation time 42642958 ps
CPU time 1.08 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818983470 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.1818983470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.4244608933
Short name T946
Test name
Test status
Simulation time 25955824 ps
CPU time 0.67 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244608933 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.4244608933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3833521051
Short name T952
Test name
Test status
Simulation time 88603425 ps
CPU time 1.67 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3833
521051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.3833521051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.424883781
Short name T151
Test name
Test status
Simulation time 67463781 ps
CPU time 1.21 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:40 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248837
81 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.424883781
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3758230390
Short name T955
Test name
Test status
Simulation time 136808570 ps
CPU time 1.99 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 220756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3758230390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg
_errors_with_csr_rw.3758230390
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.641743789
Short name T960
Test name
Test status
Simulation time 398224527 ps
CPU time 3.12 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:42 AM UTC 24
Peak memory 212608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641743789 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.641743789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.4172450393
Short name T956
Test name
Test status
Simulation time 76787320 ps
CPU time 1.92 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 211880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172450393 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.4172450393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.513753911
Short name T965
Test name
Test status
Simulation time 69277723 ps
CPU time 0.99 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:45 AM UTC 24
Peak memory 211796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=513753911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 16.clkmgr_csr_mem_rw_with_rand_reset.513753911
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.554999815
Short name T962
Test name
Test status
Simulation time 49907631 ps
CPU time 0.71 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:45 AM UTC 24
Peak memory 212048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554999815 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.554999815
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.3867173832
Short name T937
Test name
Test status
Simulation time 166732773 ps
CPU time 0.97 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:45 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867173832 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.3867173832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1987870321
Short name T966
Test name
Test status
Simulation time 61532478 ps
CPU time 1.24 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1987
870321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.1987870321
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2563353431
Short name T957
Test name
Test status
Simulation time 122540223 ps
CPU time 1.92 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 220760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563353
431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.2563353431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1874054595
Short name T954
Test name
Test status
Simulation time 97317877 ps
CPU time 1.67 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 211640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1874054595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg
_errors_with_csr_rw.1874054595
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.1059833378
Short name T953
Test name
Test status
Simulation time 28530209 ps
CPU time 1.58 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 212008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059833378 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.1059833378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2978736213
Short name T958
Test name
Test status
Simulation time 195977230 ps
CPU time 1.9 seconds
Started Sep 04 02:03:38 AM UTC 24
Finished Sep 04 02:03:41 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978736213 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.2978736213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.121727080
Short name T968
Test name
Test status
Simulation time 36053197 ps
CPU time 1.1 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=121727080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 17.clkmgr_csr_mem_rw_with_rand_reset.121727080
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.1629282204
Short name T964
Test name
Test status
Simulation time 36317280 ps
CPU time 0.73 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629282204 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.1629282204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.2326654738
Short name T963
Test name
Test status
Simulation time 20985667 ps
CPU time 0.61 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:45 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326654738 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.2326654738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.402218493
Short name T974
Test name
Test status
Simulation time 72343843 ps
CPU time 1.44 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022
18493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.402218493
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1495994931
Short name T967
Test name
Test status
Simulation time 152582726 ps
CPU time 1.35 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495994
931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.1495994931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.3087548017
Short name T978
Test name
Test status
Simulation time 250259870 ps
CPU time 2.45 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 222364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3087548017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg
_errors_with_csr_rw.3087548017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.1052984235
Short name T941
Test name
Test status
Simulation time 63118179 ps
CPU time 1.41 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052984235 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.1052984235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2228395715
Short name T132
Test name
Test status
Simulation time 88218834 ps
CPU time 2.11 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 212400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228395715 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.2228395715
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3310189277
Short name T976
Test name
Test status
Simulation time 88608392 ps
CPU time 1.51 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3310189277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_csr_mem_rw_with_rand_reset.3310189277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.1155515167
Short name T922
Test name
Test status
Simulation time 21563743 ps
CPU time 0.98 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155515167 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.1155515167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.666775590
Short name T924
Test name
Test status
Simulation time 15456674 ps
CPU time 0.83 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666775590 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.666775590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.587021954
Short name T973
Test name
Test status
Simulation time 27349124 ps
CPU time 1.19 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5870
21954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.587021954
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.804973835
Short name T152
Test name
Test status
Simulation time 113220369 ps
CPU time 1.72 seconds
Started Sep 04 02:03:43 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8049738
35 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.804973835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3066018795
Short name T980
Test name
Test status
Simulation time 590220409 ps
CPU time 2.9 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:48 AM UTC 24
Peak memory 229192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3066018795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg
_errors_with_csr_rw.3066018795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.689564432
Short name T982
Test name
Test status
Simulation time 1659696250 ps
CPU time 6.62 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 212224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689564432 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.689564432
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3836863419
Short name T136
Test name
Test status
Simulation time 124348118 ps
CPU time 1.77 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836863419 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.3836863419
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3557013880
Short name T972
Test name
Test status
Simulation time 30087777 ps
CPU time 0.97 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3557013880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_csr_mem_rw_with_rand_reset.3557013880
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.4152826843
Short name T970
Test name
Test status
Simulation time 72850379 ps
CPU time 0.93 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152826843 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.4152826843
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.3378621486
Short name T945
Test name
Test status
Simulation time 12919133 ps
CPU time 0.74 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378621486 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.3378621486
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.467541167
Short name T977
Test name
Test status
Simulation time 150949423 ps
CPU time 1.55 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 211948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4675
41167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.467541167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3048513196
Short name T979
Test name
Test status
Simulation time 203671718 ps
CPU time 2.05 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 212660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048513
196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.3048513196
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.165950659
Short name T975
Test name
Test status
Simulation time 145278052 ps
CPU time 1.72 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:47 AM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=165950659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_
errors_with_csr_rw.165950659
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.3015888327
Short name T981
Test name
Test status
Simulation time 335532454 ps
CPU time 2.71 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:48 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015888327 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.3015888327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1815198461
Short name T133
Test name
Test status
Simulation time 139236823 ps
CPU time 2.6 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:48 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815198461 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.1815198461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3545680689
Short name T109
Test name
Test status
Simulation time 53047511 ps
CPU time 1.47 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:20 AM UTC 24
Peak memory 211984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545680689 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.3545680689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2967296827
Short name T892
Test name
Test status
Simulation time 658033408 ps
CPU time 8.19 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 212340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967296827 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.2967296827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3988227504
Short name T867
Test name
Test status
Simulation time 51634210 ps
CPU time 0.96 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:19 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988227504 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.3988227504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1704929452
Short name T874
Test name
Test status
Simulation time 32836870 ps
CPU time 1.91 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 212000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1704929452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.clkmgr_csr_mem_rw_with_rand_reset.1704929452
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.2606598513
Short name T108
Test name
Test status
Simulation time 60350215 ps
CPU time 1.23 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:19 AM UTC 24
Peak memory 211808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606598513 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.2606598513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.1583021067
Short name T866
Test name
Test status
Simulation time 16361654 ps
CPU time 0.99 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:19 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583021067 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.1583021067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.214391702
Short name T869
Test name
Test status
Simulation time 115650178 ps
CPU time 1.49 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:20 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143
91702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.214391702
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3548704000
Short name T81
Test name
Test status
Simulation time 174603363 ps
CPU time 2.13 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:20 AM UTC 24
Peak memory 212408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548704
000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.3548704000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3824436930
Short name T85
Test name
Test status
Simulation time 146197971 ps
CPU time 1.84 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:20 AM UTC 24
Peak memory 211588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3824436930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_
errors_with_csr_rw.3824436930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.1122952669
Short name T872
Test name
Test status
Simulation time 95955861 ps
CPU time 2.98 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122952669 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.1122952669
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1140174620
Short name T122
Test name
Test status
Simulation time 120420041 ps
CPU time 2.94 seconds
Started Sep 04 02:03:17 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 212424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140174620 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.1140174620
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.3138948313
Short name T971
Test name
Test status
Simulation time 15412287 ps
CPU time 0.85 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138948313 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.3138948313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.693607317
Short name T969
Test name
Test status
Simulation time 15646483 ps
CPU time 0.66 seconds
Started Sep 04 02:03:44 AM UTC 24
Finished Sep 04 02:03:46 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693607317 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.693607317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.346902777
Short name T983
Test name
Test status
Simulation time 12816568 ps
CPU time 0.6 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346902777 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.346902777
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.1824707393
Short name T984
Test name
Test status
Simulation time 11156583 ps
CPU time 0.63 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824707393 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.1824707393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.2437686606
Short name T985
Test name
Test status
Simulation time 41195925 ps
CPU time 0.74 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437686606 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.2437686606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.3658984690
Short name T989
Test name
Test status
Simulation time 18182014 ps
CPU time 0.71 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658984690 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.3658984690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.1236156477
Short name T987
Test name
Test status
Simulation time 22170022 ps
CPU time 0.71 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236156477 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.1236156477
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.2296884204
Short name T988
Test name
Test status
Simulation time 13794967 ps
CPU time 0.71 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296884204 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.2296884204
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.568053017
Short name T986
Test name
Test status
Simulation time 28449888 ps
CPU time 0.66 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568053017 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.568053017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.1199064030
Short name T991
Test name
Test status
Simulation time 12707369 ps
CPU time 0.65 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199064030 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.1199064030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2325703309
Short name T875
Test name
Test status
Simulation time 107124518 ps
CPU time 1.67 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:22 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325703309 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.2325703309
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.46685906
Short name T914
Test name
Test status
Simulation time 1988608566 ps
CPU time 12.66 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 212380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46685906 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.46685906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1841296749
Short name T871
Test name
Test status
Simulation time 31024369 ps
CPU time 1.18 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841296749 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.1841296749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.507087671
Short name T880
Test name
Test status
Simulation time 42896011 ps
CPU time 1.63 seconds
Started Sep 04 02:03:20 AM UTC 24
Finished Sep 04 02:03:23 AM UTC 24
Peak memory 211736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=507087671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 3.clkmgr_csr_mem_rw_with_rand_reset.507087671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.3867059
Short name T873
Test name
Test status
Simulation time 79186224 ps
CPU time 1.47 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867059 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.3867059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.3908549801
Short name T870
Test name
Test status
Simulation time 12010334 ps
CPU time 0.99 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:21 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908549801 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.3908549801
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2517379947
Short name T878
Test name
Test status
Simulation time 199650443 ps
CPU time 1.53 seconds
Started Sep 04 02:03:20 AM UTC 24
Finished Sep 04 02:03:23 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517
379947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.2517379947
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2615315141
Short name T84
Test name
Test status
Simulation time 110094357 ps
CPU time 2.84 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:22 AM UTC 24
Peak memory 221976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2615315141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_
errors_with_csr_rw.2615315141
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.1177333636
Short name T876
Test name
Test status
Simulation time 96377221 ps
CPU time 2.18 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:22 AM UTC 24
Peak memory 212476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177333636 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.1177333636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2046390391
Short name T881
Test name
Test status
Simulation time 815445723 ps
CPU time 3.42 seconds
Started Sep 04 02:03:19 AM UTC 24
Finished Sep 04 02:03:23 AM UTC 24
Peak memory 212424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046390391 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.2046390391
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.1604925433
Short name T990
Test name
Test status
Simulation time 17920317 ps
CPU time 0.66 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604925433 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.1604925433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.2108026388
Short name T992
Test name
Test status
Simulation time 19239111 ps
CPU time 0.65 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108026388 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.2108026388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.177823200
Short name T994
Test name
Test status
Simulation time 32288070 ps
CPU time 0.73 seconds
Started Sep 04 02:03:50 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177823200 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.177823200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.3207803768
Short name T993
Test name
Test status
Simulation time 14103164 ps
CPU time 0.62 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207803768 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.3207803768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.1223013039
Short name T999
Test name
Test status
Simulation time 76934919 ps
CPU time 0.74 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223013039 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.1223013039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.2390908810
Short name T995
Test name
Test status
Simulation time 13632297 ps
CPU time 0.69 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390908810 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.2390908810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.1515591640
Short name T996
Test name
Test status
Simulation time 29502767 ps
CPU time 0.72 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515591640 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.1515591640
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.2683613429
Short name T1000
Test name
Test status
Simulation time 26689946 ps
CPU time 0.75 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683613429 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.2683613429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.4218319281
Short name T997
Test name
Test status
Simulation time 14601811 ps
CPU time 0.67 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4218319281 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.4218319281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.2079781462
Short name T1001
Test name
Test status
Simulation time 14170871 ps
CPU time 0.71 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079781462 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.2079781462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.2670337356
Short name T887
Test name
Test status
Simulation time 138678666 ps
CPU time 2.33 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 212412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670337356 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.2670337356
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.25744524
Short name T897
Test name
Test status
Simulation time 323870296 ps
CPU time 4.59 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:28 AM UTC 24
Peak memory 212344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25744524 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.25744524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.784933412
Short name T879
Test name
Test status
Simulation time 35134381 ps
CPU time 1.23 seconds
Started Sep 04 02:03:21 AM UTC 24
Finished Sep 04 02:03:23 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=784933412 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.784933412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.46723689
Short name T888
Test name
Test status
Simulation time 166480403 ps
CPU time 2.48 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 212196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=46723689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_mem_rw_with_rand_reset.46723689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.2077671590
Short name T882
Test name
Test status
Simulation time 14244407 ps
CPU time 0.98 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:24 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077671590 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.2077671590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.3734123648
Short name T877
Test name
Test status
Simulation time 30886341 ps
CPU time 1.03 seconds
Started Sep 04 02:03:21 AM UTC 24
Finished Sep 04 02:03:23 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734123648 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.3734123648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2187306892
Short name T883
Test name
Test status
Simulation time 64143591 ps
CPU time 1.29 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:24 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187
306892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.2187306892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.284575059
Short name T146
Test name
Test status
Simulation time 866352864 ps
CPU time 4.57 seconds
Started Sep 04 02:03:20 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 229104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=284575059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_e
rrors_with_csr_rw.284575059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.2987407297
Short name T886
Test name
Test status
Simulation time 114666282 ps
CPU time 3.99 seconds
Started Sep 04 02:03:20 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 212772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987407297 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.2987407297
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.1220416935
Short name T998
Test name
Test status
Simulation time 14739253 ps
CPU time 0.62 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:52 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220416935 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.1220416935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.723394315
Short name T1006
Test name
Test status
Simulation time 37254128 ps
CPU time 0.78 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723394315 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.723394315
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.776668851
Short name T1003
Test name
Test status
Simulation time 13893355 ps
CPU time 0.63 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776668851 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.776668851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.2689790554
Short name T1004
Test name
Test status
Simulation time 33210032 ps
CPU time 0.64 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689790554 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.2689790554
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2398568823
Short name T1002
Test name
Test status
Simulation time 14830781 ps
CPU time 0.62 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398568823 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.2398568823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.4191100342
Short name T1005
Test name
Test status
Simulation time 14527443 ps
CPU time 0.62 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191100342 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.4191100342
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.2792345396
Short name T1008
Test name
Test status
Simulation time 37403581 ps
CPU time 0.7 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2792345396 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.2792345396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.2146110406
Short name T1009
Test name
Test status
Simulation time 13358532 ps
CPU time 0.67 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146110406 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.2146110406
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.1757900399
Short name T1010
Test name
Test status
Simulation time 47604556 ps
CPU time 0.66 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757900399 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.1757900399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.1567095885
Short name T1007
Test name
Test status
Simulation time 12120967 ps
CPU time 0.62 seconds
Started Sep 04 02:03:51 AM UTC 24
Finished Sep 04 02:03:53 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567095885 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.1567095885
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1739925652
Short name T889
Test name
Test status
Simulation time 80982309 ps
CPU time 1.14 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1739925652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_csr_mem_rw_with_rand_reset.1739925652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.78793739
Short name T890
Test name
Test status
Simulation time 41952398 ps
CPU time 1.28 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 211616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78793739 -assert nopos
tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.78793739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.3893243693
Short name T884
Test name
Test status
Simulation time 12232155 ps
CPU time 0.99 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:25 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893243693 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.3893243693
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3758511743
Short name T896
Test name
Test status
Simulation time 663378879 ps
CPU time 2.91 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:28 AM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758
511743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.3758511743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.4275640722
Short name T139
Test name
Test status
Simulation time 73496568 ps
CPU time 2.13 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:25 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275640
722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.4275640722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3193609918
Short name T147
Test name
Test status
Simulation time 294449915 ps
CPU time 2.69 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 222076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3193609918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_
errors_with_csr_rw.3193609918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.2451972235
Short name T885
Test name
Test status
Simulation time 33630739 ps
CPU time 1.8 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:25 AM UTC 24
Peak memory 211932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451972235 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.2451972235
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.2794957205
Short name T123
Test name
Test status
Simulation time 189263826 ps
CPU time 3 seconds
Started Sep 04 02:03:22 AM UTC 24
Finished Sep 04 02:03:26 AM UTC 24
Peak memory 212400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794957205 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.2794957205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2184332445
Short name T859
Test name
Test status
Simulation time 24119654 ps
CPU time 1.31 seconds
Started Sep 04 02:03:25 AM UTC 24
Finished Sep 04 02:03:28 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2184332445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_csr_mem_rw_with_rand_reset.2184332445
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.3878440710
Short name T894
Test name
Test status
Simulation time 52822792 ps
CPU time 1.16 seconds
Started Sep 04 02:03:25 AM UTC 24
Finished Sep 04 02:03:27 AM UTC 24
Peak memory 211872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878440710 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.3878440710
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.1825041931
Short name T893
Test name
Test status
Simulation time 47108606 ps
CPU time 0.87 seconds
Started Sep 04 02:03:25 AM UTC 24
Finished Sep 04 02:03:27 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825041931 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.1825041931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2130058513
Short name T895
Test name
Test status
Simulation time 45046066 ps
CPU time 1.29 seconds
Started Sep 04 02:03:25 AM UTC 24
Finished Sep 04 02:03:28 AM UTC 24
Peak memory 211680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130
058513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.2130058513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2578457906
Short name T142
Test name
Test status
Simulation time 283735115 ps
CPU time 2.45 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:27 AM UTC 24
Peak memory 212480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578457
906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.2578457906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.539382680
Short name T900
Test name
Test status
Simulation time 407274125 ps
CPU time 4.16 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 212796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539382680 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.539382680
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1479322671
Short name T131
Test name
Test status
Simulation time 59602887 ps
CPU time 1.79 seconds
Started Sep 04 02:03:24 AM UTC 24
Finished Sep 04 02:03:27 AM UTC 24
Peak memory 211956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479322671 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.1479322671
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.4080044177
Short name T901
Test name
Test status
Simulation time 21492751 ps
CPU time 1.38 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4080044177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.clkmgr_csr_mem_rw_with_rand_reset.4080044177
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.4199362944
Short name T899
Test name
Test status
Simulation time 45770407 ps
CPU time 1.04 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 212108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199362944 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.4199362944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.2197305588
Short name T898
Test name
Test status
Simulation time 13393709 ps
CPU time 0.91 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197305588 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.2197305588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3339519443
Short name T903
Test name
Test status
Simulation time 232348926 ps
CPU time 1.82 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:30 AM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339
519443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.3339519443
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3904784788
Short name T145
Test name
Test status
Simulation time 140454584 ps
CPU time 2.07 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:30 AM UTC 24
Peak memory 222036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3904784788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_
errors_with_csr_rw.3904784788
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.805702939
Short name T904
Test name
Test status
Simulation time 39517253 ps
CPU time 2.63 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:30 AM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=805702939 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.805702939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1300597780
Short name T902
Test name
Test status
Simulation time 100214808 ps
CPU time 1.61 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 211940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300597780 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.1300597780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3130879360
Short name T909
Test name
Test status
Simulation time 52230133 ps
CPU time 1.28 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 211800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3130879360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_csr_mem_rw_with_rand_reset.3130879360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.3670734697
Short name T908
Test name
Test status
Simulation time 41016314 ps
CPU time 1.24 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 212112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670734697 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.3670734697
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.360921742
Short name T905
Test name
Test status
Simulation time 34621943 ps
CPU time 0.92 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360921742 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.360921742
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.921316924
Short name T907
Test name
Test status
Simulation time 55421375 ps
CPU time 1.19 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 211812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9213
16924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.921316924
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.883978298
Short name T87
Test name
Test status
Simulation time 209482530 ps
CPU time 2.02 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:30 AM UTC 24
Peak memory 212800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8839782
98 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.883978298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3374804690
Short name T148
Test name
Test status
Simulation time 97912294 ps
CPU time 2.48 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 221760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3374804690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_
errors_with_csr_rw.3374804690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.2008163686
Short name T906
Test name
Test status
Simulation time 128449008 ps
CPU time 2.91 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 212404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008163686 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.2008163686
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.896423277
Short name T128
Test name
Test status
Simulation time 137760687 ps
CPU time 2.75 seconds
Started Sep 04 02:03:27 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 212032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896423277 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.896423277
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.69160326
Short name T912
Test name
Test status
Simulation time 39457248 ps
CPU time 1.19 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:32 AM UTC 24
Peak memory 211740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=69160326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 9.clkmgr_csr_mem_rw_with_rand_reset.69160326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.1343778394
Short name T911
Test name
Test status
Simulation time 44723131 ps
CPU time 1.2 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343778394 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.1343778394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.1521562170
Short name T910
Test name
Test status
Simulation time 38795709 ps
CPU time 1.03 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521562170 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.1521562170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3380234791
Short name T913
Test name
Test status
Simulation time 82709411 ps
CPU time 1.43 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:32 AM UTC 24
Peak memory 211868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380
234791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.3380234791
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2767141187
Short name T153
Test name
Test status
Simulation time 81987963 ps
CPU time 1.35 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 211688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767141
187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.2767141187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1263196330
Short name T144
Test name
Test status
Simulation time 177219848 ps
CPU time 3.14 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 212388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1263196330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_
errors_with_csr_rw.1263196330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.4129949172
Short name T919
Test name
Test status
Simulation time 285450479 ps
CPU time 3.4 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:33 AM UTC 24
Peak memory 212588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129949172 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.4129949172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3330390471
Short name T129
Test name
Test status
Simulation time 521587894 ps
CPU time 3.7 seconds
Started Sep 04 02:03:29 AM UTC 24
Finished Sep 04 02:03:34 AM UTC 24
Peak memory 212336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330390471 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.3330390471
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.1332095029
Short name T54
Test name
Test status
Simulation time 71308729 ps
CPU time 1.4 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 01:59:03 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332095029 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.1332095029
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.3389106956
Short name T32
Test name
Test status
Simulation time 80042380 ps
CPU time 1.54 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:02 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389106956 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.3389106956
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.3778080823
Short name T6
Test name
Test status
Simulation time 47807154 ps
CPU time 1.13 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778080823 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3778080823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.1529682378
Short name T10
Test name
Test status
Simulation time 1520474584 ps
CPU time 9.55 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:10 AM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529682378 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1529682378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.2196136248
Short name T2
Test name
Test status
Simulation time 374613670 ps
CPU time 4.21 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:04 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196136248 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.2196136248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.2583166662
Short name T31
Test name
Test status
Simulation time 68811835 ps
CPU time 1.37 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583166662 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.2583166662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1047442865
Short name T27
Test name
Test status
Simulation time 21524970 ps
CPU time 0.9 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047442865
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.1047442865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.2129446453
Short name T5
Test name
Test status
Simulation time 39186890 ps
CPU time 0.77 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129446453 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2129446453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.1409602610
Short name T3
Test name
Test status
Simulation time 887262460 ps
CPU time 5.19 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:06 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409602610 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1409602610
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.4227289743
Short name T41
Test name
Test status
Simulation time 8675870222 ps
CPU time 65.03 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 02:00:07 AM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227289743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.4227289743
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.1378170126
Short name T30
Test name
Test status
Simulation time 29572825 ps
CPU time 1.27 seconds
Started Sep 04 01:58:59 AM UTC 24
Finished Sep 04 01:59:01 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378170126 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.1378170126
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3268983051
Short name T110
Test name
Test status
Simulation time 90617443 ps
CPU time 1.48 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:04 AM UTC 24
Peak memory 206320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268983051 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.3268983051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.3283533180
Short name T55
Test name
Test status
Simulation time 54476668 ps
CPU time 1.14 seconds
Started Sep 04 01:59:01 AM UTC 24
Finished Sep 04 01:59:03 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283533180 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3283533180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.1180821856
Short name T111
Test name
Test status
Simulation time 80068244 ps
CPU time 1.5 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:04 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180821856 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.1180821856
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.1701361125
Short name T43
Test name
Test status
Simulation time 17474251 ps
CPU time 0.96 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 01:59:02 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701361125 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1701361125
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.1271492089
Short name T38
Test name
Test status
Simulation time 983398858 ps
CPU time 5.86 seconds
Started Sep 04 01:59:01 AM UTC 24
Finished Sep 04 01:59:07 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271492089 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.1271492089
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.2854086316
Short name T53
Test name
Test status
Simulation time 36056597 ps
CPU time 1.05 seconds
Started Sep 04 01:59:01 AM UTC 24
Finished Sep 04 01:59:03 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854086316 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.2854086316
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2010585700
Short name T72
Test name
Test status
Simulation time 18620788 ps
CPU time 1.06 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:04 AM UTC 24
Peak memory 207416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010585700
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.2010585700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.256354780
Short name T112
Test name
Test status
Simulation time 140668260 ps
CPU time 1.89 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:05 AM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256354780 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.256354780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.1578701813
Short name T52
Test name
Test status
Simulation time 12922406 ps
CPU time 0.93 seconds
Started Sep 04 01:59:01 AM UTC 24
Finished Sep 04 01:59:03 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1578701813 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1578701813
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.353563011
Short name T12
Test name
Test status
Simulation time 955302849 ps
CPU time 5.66 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:09 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353563011 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.353563011
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.2915986594
Short name T65
Test name
Test status
Simulation time 402440408 ps
CPU time 3.9 seconds
Started Sep 04 01:59:02 AM UTC 24
Finished Sep 04 01:59:07 AM UTC 24
Peak memory 242820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915986594 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.2915986594
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.1483108371
Short name T51
Test name
Test status
Simulation time 61173476 ps
CPU time 1.04 seconds
Started Sep 04 01:59:00 AM UTC 24
Finished Sep 04 01:59:02 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483108371 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1483108371
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.2112334404
Short name T56
Test name
Test status
Simulation time 28520238 ps
CPU time 1.34 seconds
Started Sep 04 01:59:01 AM UTC 24
Finished Sep 04 01:59:03 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112334404 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2112334404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.1726868068
Short name T260
Test name
Test status
Simulation time 28509327 ps
CPU time 1.19 seconds
Started Sep 04 01:59:51 AM UTC 24
Finished Sep 04 01:59:54 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726868068 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.1726868068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1894738979
Short name T117
Test name
Test status
Simulation time 92424286 ps
CPU time 1.82 seconds
Started Sep 04 01:59:50 AM UTC 24
Finished Sep 04 01:59:53 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894738979 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.1894738979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.3631438939
Short name T203
Test name
Test status
Simulation time 23400512 ps
CPU time 0.96 seconds
Started Sep 04 01:59:49 AM UTC 24
Finished Sep 04 01:59:51 AM UTC 24
Peak memory 209900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631438939 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3631438939
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.1672278030
Short name T256
Test name
Test status
Simulation time 30568175 ps
CPU time 1.24 seconds
Started Sep 04 01:59:50 AM UTC 24
Finished Sep 04 01:59:52 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672278030 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.1672278030
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.369819649
Short name T252
Test name
Test status
Simulation time 67621948 ps
CPU time 1.41 seconds
Started Sep 04 01:59:47 AM UTC 24
Finished Sep 04 01:59:49 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369819649 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.369819649
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.1527591616
Short name T36
Test name
Test status
Simulation time 1534645638 ps
CPU time 10.26 seconds
Started Sep 04 01:59:48 AM UTC 24
Finished Sep 04 01:59:59 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527591616 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1527591616
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.3724079492
Short name T272
Test name
Test status
Simulation time 1221549701 ps
CPU time 16.91 seconds
Started Sep 04 01:59:48 AM UTC 24
Finished Sep 04 02:00:06 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724079492 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.3724079492
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.293892345
Short name T255
Test name
Test status
Simulation time 80713356 ps
CPU time 1.65 seconds
Started Sep 04 01:59:49 AM UTC 24
Finished Sep 04 01:59:51 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293892345 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.293892345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1092040347
Short name T257
Test name
Test status
Simulation time 23158658 ps
CPU time 1.31 seconds
Started Sep 04 01:59:50 AM UTC 24
Finished Sep 04 01:59:52 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092040347
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.1092040347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3057770495
Short name T258
Test name
Test status
Simulation time 55487699 ps
CPU time 1.48 seconds
Started Sep 04 01:59:50 AM UTC 24
Finished Sep 04 01:59:53 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057770495
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.3057770495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.150205573
Short name T253
Test name
Test status
Simulation time 16596393 ps
CPU time 1.06 seconds
Started Sep 04 01:59:48 AM UTC 24
Finished Sep 04 01:59:50 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150205573 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.150205573
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.2710811672
Short name T195
Test name
Test status
Simulation time 1139222325 ps
CPU time 8 seconds
Started Sep 04 01:59:50 AM UTC 24
Finished Sep 04 01:59:59 AM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710811672 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2710811672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.2538902587
Short name T250
Test name
Test status
Simulation time 14959557 ps
CPU time 1.18 seconds
Started Sep 04 01:59:46 AM UTC 24
Finished Sep 04 01:59:49 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538902587 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2538902587
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.1410224587
Short name T193
Test name
Test status
Simulation time 882354459 ps
CPU time 5.87 seconds
Started Sep 04 01:59:51 AM UTC 24
Finished Sep 04 01:59:58 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410224587 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.1410224587
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.189991949
Short name T91
Test name
Test status
Simulation time 2153158093 ps
CPU time 46.57 seconds
Started Sep 04 01:59:50 AM UTC 24
Finished Sep 04 02:00:38 AM UTC 24
Peak memory 222280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189991949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.189991949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.2941012378
Short name T254
Test name
Test status
Simulation time 68144029 ps
CPU time 1.37 seconds
Started Sep 04 01:59:48 AM UTC 24
Finished Sep 04 01:59:50 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941012378 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2941012378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.2329727466
Short name T266
Test name
Test status
Simulation time 50302949 ps
CPU time 1.32 seconds
Started Sep 04 01:59:59 AM UTC 24
Finished Sep 04 02:00:01 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329727466 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.2329727466
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.4150122741
Short name T198
Test name
Test status
Simulation time 54298073 ps
CPU time 1.25 seconds
Started Sep 04 01:59:57 AM UTC 24
Finished Sep 04 01:59:59 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150122741 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.4150122741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.142956399
Short name T191
Test name
Test status
Simulation time 21959400 ps
CPU time 1.02 seconds
Started Sep 04 01:59:55 AM UTC 24
Finished Sep 04 01:59:57 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142956399 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.142956399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.1144052983
Short name T197
Test name
Test status
Simulation time 15125652 ps
CPU time 1.09 seconds
Started Sep 04 01:59:57 AM UTC 24
Finished Sep 04 01:59:59 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144052983 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.1144052983
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.274282712
Short name T264
Test name
Test status
Simulation time 78651985 ps
CPU time 1.61 seconds
Started Sep 04 01:59:54 AM UTC 24
Finished Sep 04 01:59:56 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274282712 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.274282712
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.258469745
Short name T301
Test name
Test status
Simulation time 1761344955 ps
CPU time 26.5 seconds
Started Sep 04 01:59:54 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 210680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258469745 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.258469745
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.3545799062
Short name T288
Test name
Test status
Simulation time 2416378950 ps
CPU time 19.9 seconds
Started Sep 04 01:59:54 AM UTC 24
Finished Sep 04 02:00:15 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545799062 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.3545799062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.3317802364
Short name T194
Test name
Test status
Simulation time 31822878 ps
CPU time 1.44 seconds
Started Sep 04 01:59:56 AM UTC 24
Finished Sep 04 01:59:58 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317802364 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.3317802364
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1405225747
Short name T196
Test name
Test status
Simulation time 19827439 ps
CPU time 1.15 seconds
Started Sep 04 01:59:57 AM UTC 24
Finished Sep 04 01:59:59 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405225747
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.1405225747
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2078263345
Short name T192
Test name
Test status
Simulation time 15831849 ps
CPU time 1.09 seconds
Started Sep 04 01:59:56 AM UTC 24
Finished Sep 04 01:59:58 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078263345
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.2078263345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.2446242384
Short name T262
Test name
Test status
Simulation time 44573908 ps
CPU time 1.21 seconds
Started Sep 04 01:59:54 AM UTC 24
Finished Sep 04 01:59:56 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446242384 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2446242384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.937312072
Short name T259
Test name
Test status
Simulation time 58636760 ps
CPU time 1.42 seconds
Started Sep 04 01:59:52 AM UTC 24
Finished Sep 04 01:59:55 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937312072 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.937312072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.3207539206
Short name T360
Test name
Test status
Simulation time 5770457768 ps
CPU time 46.35 seconds
Started Sep 04 01:59:57 AM UTC 24
Finished Sep 04 02:00:45 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207539206 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.3207539206
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.544664768
Short name T423
Test name
Test status
Simulation time 3348619930 ps
CPU time 66.24 seconds
Started Sep 04 01:59:57 AM UTC 24
Finished Sep 04 02:01:05 AM UTC 24
Peak memory 220520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544664768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.544664768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.3019611065
Short name T263
Test name
Test status
Simulation time 29564640 ps
CPU time 1.42 seconds
Started Sep 04 01:59:54 AM UTC 24
Finished Sep 04 01:59:56 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019611065 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3019611065
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.1890991714
Short name T278
Test name
Test status
Simulation time 33811260 ps
CPU time 1.14 seconds
Started Sep 04 02:00:07 AM UTC 24
Finished Sep 04 02:00:09 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890991714 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.1890991714
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.315806828
Short name T276
Test name
Test status
Simulation time 129998123 ps
CPU time 1.75 seconds
Started Sep 04 02:00:02 AM UTC 24
Finished Sep 04 02:00:08 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315806828 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.315806828
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.278112498
Short name T204
Test name
Test status
Simulation time 14938726 ps
CPU time 1.08 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:02 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278112498 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.278112498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.2794435996
Short name T277
Test name
Test status
Simulation time 16500330 ps
CPU time 1.17 seconds
Started Sep 04 02:00:06 AM UTC 24
Finished Sep 04 02:00:09 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794435996 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.2794435996
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.2554619
Short name T267
Test name
Test status
Simulation time 11769700 ps
CPU time 1.02 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:02 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554619 -assert nopostproc +UVM_TESTNAME=clkmg
r_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2554619
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.34064566
Short name T274
Test name
Test status
Simulation time 994503048 ps
CPU time 6.03 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:07 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34064566 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.34064566
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.1313866694
Short name T269
Test name
Test status
Simulation time 20658360 ps
CPU time 1.21 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:02 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313866694 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.1313866694
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.431425623
Short name T275
Test name
Test status
Simulation time 22590129 ps
CPU time 1.27 seconds
Started Sep 04 02:00:02 AM UTC 24
Finished Sep 04 02:00:07 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431425623 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.431425623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2203273570
Short name T273
Test name
Test status
Simulation time 56080166 ps
CPU time 1.31 seconds
Started Sep 04 02:00:01 AM UTC 24
Finished Sep 04 02:00:07 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203273570
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.2203273570
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.393446827
Short name T268
Test name
Test status
Simulation time 44376761 ps
CPU time 1.28 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:02 AM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393446827 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.393446827
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.442767514
Short name T296
Test name
Test status
Simulation time 1112841687 ps
CPU time 10.9 seconds
Started Sep 04 02:00:07 AM UTC 24
Finished Sep 04 02:00:19 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442767514 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.442767514
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.1295466047
Short name T265
Test name
Test status
Simulation time 30556281 ps
CPU time 0.99 seconds
Started Sep 04 01:59:59 AM UTC 24
Finished Sep 04 02:00:01 AM UTC 24
Peak memory 209908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295466047 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1295466047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.110059893
Short name T370
Test name
Test status
Simulation time 6318247750 ps
CPU time 38.29 seconds
Started Sep 04 02:00:07 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110059893 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.110059893
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.1258749210
Short name T93
Test name
Test status
Simulation time 1832827586 ps
CPU time 33.94 seconds
Started Sep 04 02:00:07 AM UTC 24
Finished Sep 04 02:00:42 AM UTC 24
Peak memory 227212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258749210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.1258749210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.2959470284
Short name T270
Test name
Test status
Simulation time 179717842 ps
CPU time 2.31 seconds
Started Sep 04 02:00:00 AM UTC 24
Finished Sep 04 02:00:03 AM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959470284 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2959470284
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.1754106397
Short name T289
Test name
Test status
Simulation time 18095638 ps
CPU time 1.19 seconds
Started Sep 04 02:00:13 AM UTC 24
Finished Sep 04 02:00:15 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754106397 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.1754106397
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2941813789
Short name T286
Test name
Test status
Simulation time 34258511 ps
CPU time 0.95 seconds
Started Sep 04 02:00:10 AM UTC 24
Finished Sep 04 02:00:12 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941813789 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.2941813789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.3602659964
Short name T281
Test name
Test status
Simulation time 15573903 ps
CPU time 1.05 seconds
Started Sep 04 02:00:08 AM UTC 24
Finished Sep 04 02:00:10 AM UTC 24
Peak memory 208644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602659964 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3602659964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.1471882343
Short name T287
Test name
Test status
Simulation time 21715592 ps
CPU time 1.26 seconds
Started Sep 04 02:00:10 AM UTC 24
Finished Sep 04 02:00:13 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471882343 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1471882343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.2531753164
Short name T279
Test name
Test status
Simulation time 58977348 ps
CPU time 1.39 seconds
Started Sep 04 02:00:07 AM UTC 24
Finished Sep 04 02:00:09 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531753164 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2531753164
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.3810972748
Short name T61
Test name
Test status
Simulation time 1526616802 ps
CPU time 9.75 seconds
Started Sep 04 02:00:08 AM UTC 24
Finished Sep 04 02:00:19 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810972748 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3810972748
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.872264462
Short name T293
Test name
Test status
Simulation time 1618064127 ps
CPU time 8.76 seconds
Started Sep 04 02:00:08 AM UTC 24
Finished Sep 04 02:00:18 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872264462 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.872264462
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.1096358507
Short name T285
Test name
Test status
Simulation time 81093137 ps
CPU time 1.66 seconds
Started Sep 04 02:00:09 AM UTC 24
Finished Sep 04 02:00:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096358507 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.1096358507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2047463150
Short name T284
Test name
Test status
Simulation time 34465871 ps
CPU time 1.32 seconds
Started Sep 04 02:00:09 AM UTC 24
Finished Sep 04 02:00:12 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047463150
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.2047463150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1065947281
Short name T283
Test name
Test status
Simulation time 24812863 ps
CPU time 1.28 seconds
Started Sep 04 02:00:09 AM UTC 24
Finished Sep 04 02:00:11 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065947281
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.1065947281
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.3971564359
Short name T282
Test name
Test status
Simulation time 68253201 ps
CPU time 1.37 seconds
Started Sep 04 02:00:08 AM UTC 24
Finished Sep 04 02:00:10 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971564359 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.3971564359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.3111835610
Short name T174
Test name
Test status
Simulation time 1043853247 ps
CPU time 9.92 seconds
Started Sep 04 02:00:10 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111835610 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3111835610
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.3459225219
Short name T169
Test name
Test status
Simulation time 23027901 ps
CPU time 1.28 seconds
Started Sep 04 02:00:07 AM UTC 24
Finished Sep 04 02:00:09 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459225219 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.3459225219
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.4135789793
Short name T160
Test name
Test status
Simulation time 13046652647 ps
CPU time 70.43 seconds
Started Sep 04 02:00:12 AM UTC 24
Finished Sep 04 02:01:24 AM UTC 24
Peak memory 210996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135789793 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.4135789793
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.3526063109
Short name T436
Test name
Test status
Simulation time 8764984012 ps
CPU time 56.57 seconds
Started Sep 04 02:00:11 AM UTC 24
Finished Sep 04 02:01:09 AM UTC 24
Peak memory 224360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526063109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.3526063109
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.2159689884
Short name T280
Test name
Test status
Simulation time 23738399 ps
CPU time 1.02 seconds
Started Sep 04 02:00:08 AM UTC 24
Finished Sep 04 02:00:10 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159689884 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2159689884
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.960414617
Short name T303
Test name
Test status
Simulation time 15986073 ps
CPU time 1.1 seconds
Started Sep 04 02:00:20 AM UTC 24
Finished Sep 04 02:00:22 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960414617 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.960414617
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3959375352
Short name T118
Test name
Test status
Simulation time 83015947 ps
CPU time 1.66 seconds
Started Sep 04 02:00:18 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959375352 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3959375352
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.271992572
Short name T295
Test name
Test status
Simulation time 39650388 ps
CPU time 1.17 seconds
Started Sep 04 02:00:16 AM UTC 24
Finished Sep 04 02:00:18 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271992572 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.271992572
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.3461006529
Short name T302
Test name
Test status
Simulation time 18412821 ps
CPU time 1.08 seconds
Started Sep 04 02:00:20 AM UTC 24
Finished Sep 04 02:00:22 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461006529 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.3461006529
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.3111937383
Short name T290
Test name
Test status
Simulation time 28699279 ps
CPU time 1.32 seconds
Started Sep 04 02:00:13 AM UTC 24
Finished Sep 04 02:00:15 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111937383 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3111937383
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.99072225
Short name T310
Test name
Test status
Simulation time 1890504009 ps
CPU time 11.17 seconds
Started Sep 04 02:00:13 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99072225 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.99072225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.2709951099
Short name T292
Test name
Test status
Simulation time 136669440 ps
CPU time 2.62 seconds
Started Sep 04 02:00:14 AM UTC 24
Finished Sep 04 02:00:18 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709951099 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.2709951099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.370975785
Short name T297
Test name
Test status
Simulation time 90638519 ps
CPU time 1.8 seconds
Started Sep 04 02:00:16 AM UTC 24
Finished Sep 04 02:00:19 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370975785 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.370975785
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2490525573
Short name T300
Test name
Test status
Simulation time 32928449 ps
CPU time 1.23 seconds
Started Sep 04 02:00:18 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490525573
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.2490525573
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.4093695461
Short name T299
Test name
Test status
Simulation time 20196351 ps
CPU time 0.99 seconds
Started Sep 04 02:00:18 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093695461
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.4093695461
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.2029950668
Short name T291
Test name
Test status
Simulation time 20520539 ps
CPU time 1.09 seconds
Started Sep 04 02:00:15 AM UTC 24
Finished Sep 04 02:00:17 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029950668 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2029950668
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.3339467896
Short name T175
Test name
Test status
Simulation time 394015558 ps
CPU time 3.02 seconds
Started Sep 04 02:00:20 AM UTC 24
Finished Sep 04 02:00:24 AM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339467896 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3339467896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.3405372859
Short name T158
Test name
Test status
Simulation time 71571974 ps
CPU time 1.53 seconds
Started Sep 04 02:00:13 AM UTC 24
Finished Sep 04 02:00:15 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405372859 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.3405372859
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.1016795339
Short name T305
Test name
Test status
Simulation time 331256014 ps
CPU time 3.21 seconds
Started Sep 04 02:00:20 AM UTC 24
Finished Sep 04 02:00:24 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016795339 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.1016795339
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.1428273848
Short name T189
Test name
Test status
Simulation time 20189324235 ps
CPU time 147.24 seconds
Started Sep 04 02:00:20 AM UTC 24
Finished Sep 04 02:02:49 AM UTC 24
Peak memory 226636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428273848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.1428273848
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.3583900156
Short name T294
Test name
Test status
Simulation time 40234161 ps
CPU time 1.32 seconds
Started Sep 04 02:00:16 AM UTC 24
Finished Sep 04 02:00:18 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583900156 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.3583900156
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.4160870736
Short name T313
Test name
Test status
Simulation time 32717844 ps
CPU time 1.24 seconds
Started Sep 04 02:00:25 AM UTC 24
Finished Sep 04 02:00:27 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160870736 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.4160870736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1480949107
Short name T119
Test name
Test status
Simulation time 59451748 ps
CPU time 1.41 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480949107 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.1480949107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.1078159408
Short name T308
Test name
Test status
Simulation time 177828296 ps
CPU time 1.55 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078159408 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1078159408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.4002678357
Short name T315
Test name
Test status
Simulation time 159375385 ps
CPU time 2.09 seconds
Started Sep 04 02:00:23 AM UTC 24
Finished Sep 04 02:00:26 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002678357 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.4002678357
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.2473741662
Short name T304
Test name
Test status
Simulation time 15185510 ps
CPU time 1.09 seconds
Started Sep 04 02:00:21 AM UTC 24
Finished Sep 04 02:00:23 AM UTC 24
Peak memory 210052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473741662 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2473741662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.3673195124
Short name T325
Test name
Test status
Simulation time 1170096540 ps
CPU time 7.92 seconds
Started Sep 04 02:00:21 AM UTC 24
Finished Sep 04 02:00:30 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673195124 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3673195124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.1786791051
Short name T335
Test name
Test status
Simulation time 1459076527 ps
CPU time 11.26 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:35 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786791051 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.1786791051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.782990700
Short name T309
Test name
Test status
Simulation time 87676017 ps
CPU time 1.54 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782990700 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.782990700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2587211028
Short name T312
Test name
Test status
Simulation time 146682158 ps
CPU time 1.88 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587211028
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.2587211028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2963897405
Short name T307
Test name
Test status
Simulation time 20675171 ps
CPU time 1.13 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963897405
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.2963897405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.3103115216
Short name T306
Test name
Test status
Simulation time 47032554 ps
CPU time 1.26 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103115216 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3103115216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.4044817175
Short name T339
Test name
Test status
Simulation time 1168845889 ps
CPU time 12.37 seconds
Started Sep 04 02:00:23 AM UTC 24
Finished Sep 04 02:00:36 AM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044817175 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.4044817175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.2783232608
Short name T170
Test name
Test status
Simulation time 23658502 ps
CPU time 1.04 seconds
Started Sep 04 02:00:20 AM UTC 24
Finished Sep 04 02:00:22 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783232608 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.2783232608
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.2224110851
Short name T365
Test name
Test status
Simulation time 3874886133 ps
CPU time 20.36 seconds
Started Sep 04 02:00:24 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224110851 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.2224110851
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.3854396648
Short name T368
Test name
Test status
Simulation time 1214005120 ps
CPU time 20.81 seconds
Started Sep 04 02:00:24 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 220392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854396648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3854396648
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.1620713738
Short name T311
Test name
Test status
Simulation time 130731576 ps
CPU time 1.81 seconds
Started Sep 04 02:00:22 AM UTC 24
Finished Sep 04 02:00:25 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620713738 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1620713738
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.1799185845
Short name T328
Test name
Test status
Simulation time 56463930 ps
CPU time 1.3 seconds
Started Sep 04 02:00:30 AM UTC 24
Finished Sep 04 02:00:32 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799185845 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.1799185845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3803631389
Short name T324
Test name
Test status
Simulation time 27498497 ps
CPU time 1.34 seconds
Started Sep 04 02:00:27 AM UTC 24
Finished Sep 04 02:00:30 AM UTC 24
Peak memory 210224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803631389 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.3803631389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.1482572513
Short name T318
Test name
Test status
Simulation time 18679475 ps
CPU time 1.1 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:29 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482572513 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1482572513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.2702905430
Short name T326
Test name
Test status
Simulation time 14468424 ps
CPU time 0.87 seconds
Started Sep 04 02:00:29 AM UTC 24
Finished Sep 04 02:00:31 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702905430 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.2702905430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.3850611687
Short name T316
Test name
Test status
Simulation time 16062638 ps
CPU time 1.08 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:28 AM UTC 24
Peak memory 210528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850611687 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.3850611687
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.1144695986
Short name T358
Test name
Test status
Simulation time 1634638626 ps
CPU time 16.66 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:44 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144695986 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1144695986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.64579606
Short name T323
Test name
Test status
Simulation time 142257975 ps
CPU time 2.6 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:30 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64579606 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.64579606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.3079405122
Short name T320
Test name
Test status
Simulation time 58607400 ps
CPU time 1.39 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:29 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3079405122 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.3079405122
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.2797944986
Short name T322
Test name
Test status
Simulation time 17329400 ps
CPU time 1.2 seconds
Started Sep 04 02:00:27 AM UTC 24
Finished Sep 04 02:00:30 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797944986
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.2797944986
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3768658180
Short name T319
Test name
Test status
Simulation time 32815964 ps
CPU time 1.26 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:29 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768658180
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.3768658180
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.3336513282
Short name T317
Test name
Test status
Simulation time 14664248 ps
CPU time 1.1 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:28 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336513282 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3336513282
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.1466474061
Short name T176
Test name
Test status
Simulation time 572838074 ps
CPU time 5.18 seconds
Started Sep 04 02:00:29 AM UTC 24
Finished Sep 04 02:00:35 AM UTC 24
Peak memory 210752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466474061 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1466474061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.1360803606
Short name T314
Test name
Test status
Simulation time 50388420 ps
CPU time 1.36 seconds
Started Sep 04 02:00:25 AM UTC 24
Finished Sep 04 02:00:27 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360803606 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.1360803606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.2899038269
Short name T350
Test name
Test status
Simulation time 2365038500 ps
CPU time 11.95 seconds
Started Sep 04 02:00:29 AM UTC 24
Finished Sep 04 02:00:42 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899038269 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.2899038269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.2744660084
Short name T519
Test name
Test status
Simulation time 3955933424 ps
CPU time 69.09 seconds
Started Sep 04 02:00:29 AM UTC 24
Finished Sep 04 02:01:40 AM UTC 24
Peak memory 220308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744660084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2744660084
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.3874201888
Short name T321
Test name
Test status
Simulation time 99484451 ps
CPU time 1.75 seconds
Started Sep 04 02:00:26 AM UTC 24
Finished Sep 04 02:00:29 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874201888 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3874201888
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.224899488
Short name T342
Test name
Test status
Simulation time 31520190 ps
CPU time 1.21 seconds
Started Sep 04 02:00:36 AM UTC 24
Finished Sep 04 02:00:38 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224899488 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.224899488
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2211890593
Short name T338
Test name
Test status
Simulation time 47879138 ps
CPU time 1.29 seconds
Started Sep 04 02:00:33 AM UTC 24
Finished Sep 04 02:00:36 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211890593 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.2211890593
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.494539961
Short name T331
Test name
Test status
Simulation time 31496074 ps
CPU time 1.1 seconds
Started Sep 04 02:00:31 AM UTC 24
Finished Sep 04 02:00:33 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494539961 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.494539961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.1715287229
Short name T340
Test name
Test status
Simulation time 140802961 ps
CPU time 1.73 seconds
Started Sep 04 02:00:35 AM UTC 24
Finished Sep 04 02:00:38 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715287229 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.1715287229
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.1534102212
Short name T329
Test name
Test status
Simulation time 43869949 ps
CPU time 1.32 seconds
Started Sep 04 02:00:30 AM UTC 24
Finished Sep 04 02:00:32 AM UTC 24
Peak memory 209844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534102212 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1534102212
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.4074926121
Short name T344
Test name
Test status
Simulation time 556335224 ps
CPU time 8.58 seconds
Started Sep 04 02:00:30 AM UTC 24
Finished Sep 04 02:00:40 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074926121 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.4074926121
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.1622402306
Short name T359
Test name
Test status
Simulation time 1096592884 ps
CPU time 12.07 seconds
Started Sep 04 02:00:31 AM UTC 24
Finished Sep 04 02:00:44 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622402306 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.1622402306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.739308033
Short name T333
Test name
Test status
Simulation time 159760882 ps
CPU time 2.1 seconds
Started Sep 04 02:00:31 AM UTC 24
Finished Sep 04 02:00:35 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739308033 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.739308033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.385039504
Short name T337
Test name
Test status
Simulation time 52434104 ps
CPU time 1.36 seconds
Started Sep 04 02:00:33 AM UTC 24
Finished Sep 04 02:00:36 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385039504 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.385039504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2387530216
Short name T334
Test name
Test status
Simulation time 23460691 ps
CPU time 1.3 seconds
Started Sep 04 02:00:32 AM UTC 24
Finished Sep 04 02:00:35 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387530216
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.2387530216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.70088528
Short name T330
Test name
Test status
Simulation time 16873469 ps
CPU time 1.12 seconds
Started Sep 04 02:00:31 AM UTC 24
Finished Sep 04 02:00:33 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70088528 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0
3/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.70088528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.2744430044
Short name T346
Test name
Test status
Simulation time 492777474 ps
CPU time 3.94 seconds
Started Sep 04 02:00:35 AM UTC 24
Finished Sep 04 02:00:40 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744430044 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2744430044
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.2239293902
Short name T327
Test name
Test status
Simulation time 16860966 ps
CPU time 1.2 seconds
Started Sep 04 02:00:30 AM UTC 24
Finished Sep 04 02:00:32 AM UTC 24
Peak memory 209836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239293902 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2239293902
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.2646819464
Short name T496
Test name
Test status
Simulation time 6222714242 ps
CPU time 53.2 seconds
Started Sep 04 02:00:35 AM UTC 24
Finished Sep 04 02:01:30 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646819464 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.2646819464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.1448507515
Short name T208
Test name
Test status
Simulation time 19919974091 ps
CPU time 122.39 seconds
Started Sep 04 02:00:35 AM UTC 24
Finished Sep 04 02:02:40 AM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448507515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1448507515
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.1251421028
Short name T332
Test name
Test status
Simulation time 85047461 ps
CPU time 1.78 seconds
Started Sep 04 02:00:31 AM UTC 24
Finished Sep 04 02:00:34 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251421028 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1251421028
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.1602783539
Short name T355
Test name
Test status
Simulation time 51092648 ps
CPU time 1.29 seconds
Started Sep 04 02:00:41 AM UTC 24
Finished Sep 04 02:00:43 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602783539 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.1602783539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3864785069
Short name T352
Test name
Test status
Simulation time 18397699 ps
CPU time 1.15 seconds
Started Sep 04 02:00:40 AM UTC 24
Finished Sep 04 02:00:42 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864785069 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.3864785069
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.491573532
Short name T348
Test name
Test status
Simulation time 17023678 ps
CPU time 1.08 seconds
Started Sep 04 02:00:38 AM UTC 24
Finished Sep 04 02:00:41 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491573532 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.491573532
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.860846830
Short name T351
Test name
Test status
Simulation time 12430771 ps
CPU time 1.07 seconds
Started Sep 04 02:00:40 AM UTC 24
Finished Sep 04 02:00:42 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860846830 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.860846830
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.2278761734
Short name T341
Test name
Test status
Simulation time 15649600 ps
CPU time 1.12 seconds
Started Sep 04 02:00:36 AM UTC 24
Finished Sep 04 02:00:38 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278761734 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2278761734
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.812359216
Short name T349
Test name
Test status
Simulation time 201213414 ps
CPU time 3.75 seconds
Started Sep 04 02:00:36 AM UTC 24
Finished Sep 04 02:00:41 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812359216 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.812359216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.2453996535
Short name T377
Test name
Test status
Simulation time 1491982151 ps
CPU time 9.72 seconds
Started Sep 04 02:00:37 AM UTC 24
Finished Sep 04 02:00:48 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453996535 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.2453996535
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.3188377054
Short name T357
Test name
Test status
Simulation time 325255037 ps
CPU time 2.86 seconds
Started Sep 04 02:00:39 AM UTC 24
Finished Sep 04 02:00:44 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188377054 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.3188377054
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2301011767
Short name T353
Test name
Test status
Simulation time 51928822 ps
CPU time 1.33 seconds
Started Sep 04 02:00:40 AM UTC 24
Finished Sep 04 02:00:42 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301011767
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.2301011767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.1182581898
Short name T354
Test name
Test status
Simulation time 86959354 ps
CPU time 1.46 seconds
Started Sep 04 02:00:39 AM UTC 24
Finished Sep 04 02:00:42 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182581898
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.1182581898
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.2023576482
Short name T345
Test name
Test status
Simulation time 41567764 ps
CPU time 1.21 seconds
Started Sep 04 02:00:37 AM UTC 24
Finished Sep 04 02:00:40 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023576482 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2023576482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.80025695
Short name T374
Test name
Test status
Simulation time 1092689850 ps
CPU time 6.04 seconds
Started Sep 04 02:00:40 AM UTC 24
Finished Sep 04 02:00:47 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80025695 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.80025695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.3185998838
Short name T343
Test name
Test status
Simulation time 33505572 ps
CPU time 1.31 seconds
Started Sep 04 02:00:36 AM UTC 24
Finished Sep 04 02:00:39 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185998838 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3185998838
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.95861015
Short name T439
Test name
Test status
Simulation time 4638967212 ps
CPU time 37.44 seconds
Started Sep 04 02:00:41 AM UTC 24
Finished Sep 04 02:01:20 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95861015 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.95861015
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.2096012780
Short name T450
Test name
Test status
Simulation time 2599023468 ps
CPU time 30.63 seconds
Started Sep 04 02:00:41 AM UTC 24
Finished Sep 04 02:01:13 AM UTC 24
Peak memory 220428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096012780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.2096012780
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.1305971048
Short name T347
Test name
Test status
Simulation time 44571420 ps
CPU time 1.4 seconds
Started Sep 04 02:00:37 AM UTC 24
Finished Sep 04 02:00:40 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305971048 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1305971048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.1801034707
Short name T375
Test name
Test status
Simulation time 73914073 ps
CPU time 1.03 seconds
Started Sep 04 02:00:46 AM UTC 24
Finished Sep 04 02:00:48 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801034707 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.1801034707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2573791092
Short name T372
Test name
Test status
Simulation time 68452029 ps
CPU time 1.17 seconds
Started Sep 04 02:00:44 AM UTC 24
Finished Sep 04 02:00:47 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573791092 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.2573791092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.54441670
Short name T362
Test name
Test status
Simulation time 16993338 ps
CPU time 0.93 seconds
Started Sep 04 02:00:43 AM UTC 24
Finished Sep 04 02:00:45 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54441670 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.54441670
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.2798571167
Short name T373
Test name
Test status
Simulation time 81518563 ps
CPU time 1.49 seconds
Started Sep 04 02:00:44 AM UTC 24
Finished Sep 04 02:00:47 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798571167 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.2798571167
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.1127260239
Short name T361
Test name
Test status
Simulation time 193334265 ps
CPU time 2.31 seconds
Started Sep 04 02:00:42 AM UTC 24
Finished Sep 04 02:00:45 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127260239 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1127260239
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.3252688161
Short name T417
Test name
Test status
Simulation time 2125143531 ps
CPU time 19.62 seconds
Started Sep 04 02:00:42 AM UTC 24
Finished Sep 04 02:01:03 AM UTC 24
Peak memory 210836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252688161 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3252688161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.99392705
Short name T336
Test name
Test status
Simulation time 1997533973 ps
CPU time 6.55 seconds
Started Sep 04 02:00:43 AM UTC 24
Finished Sep 04 02:00:51 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99392705 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.99392705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.2704629860
Short name T366
Test name
Test status
Simulation time 66658914 ps
CPU time 1.42 seconds
Started Sep 04 02:00:43 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704629860 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.2704629860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2008949689
Short name T371
Test name
Test status
Simulation time 20556477 ps
CPU time 1.09 seconds
Started Sep 04 02:00:44 AM UTC 24
Finished Sep 04 02:00:47 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008949689
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.2008949689
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.453171519
Short name T364
Test name
Test status
Simulation time 32601771 ps
CPU time 1.12 seconds
Started Sep 04 02:00:43 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453171519 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.453171519
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.3286141236
Short name T363
Test name
Test status
Simulation time 34374279 ps
CPU time 1.14 seconds
Started Sep 04 02:00:43 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286141236 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3286141236
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.1258642812
Short name T378
Test name
Test status
Simulation time 457968013 ps
CPU time 3.03 seconds
Started Sep 04 02:00:45 AM UTC 24
Finished Sep 04 02:00:49 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258642812 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1258642812
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.40595236
Short name T356
Test name
Test status
Simulation time 64446142 ps
CPU time 1.5 seconds
Started Sep 04 02:00:41 AM UTC 24
Finished Sep 04 02:00:44 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40595236 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.40595236
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.2989500350
Short name T410
Test name
Test status
Simulation time 2667721205 ps
CPU time 13.01 seconds
Started Sep 04 02:00:46 AM UTC 24
Finished Sep 04 02:01:00 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989500350 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.2989500350
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.788247612
Short name T187
Test name
Test status
Simulation time 6318938661 ps
CPU time 76.85 seconds
Started Sep 04 02:00:45 AM UTC 24
Finished Sep 04 02:02:03 AM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788247612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.788247612
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.2002434910
Short name T367
Test name
Test status
Simulation time 166589548 ps
CPU time 1.63 seconds
Started Sep 04 02:00:43 AM UTC 24
Finished Sep 04 02:00:46 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002434910 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2002434910
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.4056021266
Short name T21
Test name
Test status
Simulation time 70922232 ps
CPU time 1.33 seconds
Started Sep 04 01:59:07 AM UTC 24
Finished Sep 04 01:59:09 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4056021266 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.4056021266
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.1170109061
Short name T64
Test name
Test status
Simulation time 214145499 ps
CPU time 2.06 seconds
Started Sep 04 01:59:04 AM UTC 24
Finished Sep 04 01:59:07 AM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170109061 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1170109061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.3438533059
Short name T171
Test name
Test status
Simulation time 22841561 ps
CPU time 1.21 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 01:59:08 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438533059 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.3438533059
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.498125678
Short name T75
Test name
Test status
Simulation time 24450707 ps
CPU time 1.31 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:05 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498125678 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.498125678
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.773787886
Short name T9
Test name
Test status
Simulation time 571683589 ps
CPU time 4.95 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:09 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773787886 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.773787886
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3867803662
Short name T206
Test name
Test status
Simulation time 62240378 ps
CPU time 1.42 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 01:59:08 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867803662
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.3867803662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.135225257
Short name T210
Test name
Test status
Simulation time 131685012 ps
CPU time 1.95 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 01:59:09 AM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135225257 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.135225257
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.2852686199
Short name T74
Test name
Test status
Simulation time 38159409 ps
CPU time 0.89 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:05 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852686199 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2852686199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.1432461296
Short name T66
Test name
Test status
Simulation time 281713999 ps
CPU time 1.9 seconds
Started Sep 04 01:59:03 AM UTC 24
Finished Sep 04 01:59:06 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432461296 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.1432461296
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.3087348007
Short name T40
Test name
Test status
Simulation time 5988689662 ps
CPU time 40.49 seconds
Started Sep 04 01:59:07 AM UTC 24
Finished Sep 04 01:59:49 AM UTC 24
Peak memory 210728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087348007 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.3087348007
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.1893173582
Short name T92
Test name
Test status
Simulation time 11967004680 ps
CPU time 90.72 seconds
Started Sep 04 01:59:06 AM UTC 24
Finished Sep 04 02:00:38 AM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893173582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.1893173582
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.1984265353
Short name T76
Test name
Test status
Simulation time 37041448 ps
CPU time 1.08 seconds
Started Sep 04 01:59:04 AM UTC 24
Finished Sep 04 01:59:06 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984265353 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1984265353
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.1526437523
Short name T380
Test name
Test status
Simulation time 18016615 ps
CPU time 0.93 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:00:52 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526437523 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.1526437523
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3634147327
Short name T386
Test name
Test status
Simulation time 35375523 ps
CPU time 1.29 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:50 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3634147327 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3634147327
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.4067686867
Short name T379
Test name
Test status
Simulation time 46112742 ps
CPU time 0.98 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:49 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067686867 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.4067686867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.2516606094
Short name T388
Test name
Test status
Simulation time 44963941 ps
CPU time 1.28 seconds
Started Sep 04 02:00:49 AM UTC 24
Finished Sep 04 02:00:51 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516606094 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.2516606094
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.1047593368
Short name T382
Test name
Test status
Simulation time 38370992 ps
CPU time 1.29 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:49 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1047593368 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1047593368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.712028510
Short name T402
Test name
Test status
Simulation time 555806338 ps
CPU time 8.84 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:57 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712028510 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.712028510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.3788028023
Short name T401
Test name
Test status
Simulation time 1463060079 ps
CPU time 8.8 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:57 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788028023 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.3788028023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.266412507
Short name T387
Test name
Test status
Simulation time 89405609 ps
CPU time 1.61 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:50 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266412507 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.266412507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1502821590
Short name T385
Test name
Test status
Simulation time 22894386 ps
CPU time 1.23 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:50 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502821590
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.1502821590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3849694661
Short name T384
Test name
Test status
Simulation time 47257625 ps
CPU time 1.22 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:50 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849694661
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.3849694661
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.3213944389
Short name T383
Test name
Test status
Simulation time 38927321 ps
CPU time 1.18 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:49 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213944389 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3213944389
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.1259603224
Short name T392
Test name
Test status
Simulation time 267562609 ps
CPU time 3.57 seconds
Started Sep 04 02:00:49 AM UTC 24
Finished Sep 04 02:00:53 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259603224 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1259603224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.1243699203
Short name T376
Test name
Test status
Simulation time 50891945 ps
CPU time 1.4 seconds
Started Sep 04 02:00:46 AM UTC 24
Finished Sep 04 02:00:48 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243699203 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.1243699203
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.2913820592
Short name T445
Test name
Test status
Simulation time 1723251705 ps
CPU time 21.98 seconds
Started Sep 04 02:00:49 AM UTC 24
Finished Sep 04 02:01:12 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913820592 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.2913820592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.1167120031
Short name T661
Test name
Test status
Simulation time 10463150402 ps
CPU time 100.91 seconds
Started Sep 04 02:00:49 AM UTC 24
Finished Sep 04 02:02:32 AM UTC 24
Peak memory 220460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167120031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.1167120031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.3511848269
Short name T381
Test name
Test status
Simulation time 37098365 ps
CPU time 1.16 seconds
Started Sep 04 02:00:47 AM UTC 24
Finished Sep 04 02:00:49 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511848269 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.3511848269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.3565838528
Short name T399
Test name
Test status
Simulation time 16884947 ps
CPU time 1.07 seconds
Started Sep 04 02:00:54 AM UTC 24
Finished Sep 04 02:00:56 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565838528 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.3565838528
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.909621154
Short name T398
Test name
Test status
Simulation time 50131089 ps
CPU time 1.36 seconds
Started Sep 04 02:00:53 AM UTC 24
Finished Sep 04 02:00:55 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909621154 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.909621154
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.3169163292
Short name T393
Test name
Test status
Simulation time 43572374 ps
CPU time 1.14 seconds
Started Sep 04 02:00:51 AM UTC 24
Finished Sep 04 02:00:53 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169163292 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.3169163292
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.4038428008
Short name T396
Test name
Test status
Simulation time 18924974 ps
CPU time 1.07 seconds
Started Sep 04 02:00:53 AM UTC 24
Finished Sep 04 02:00:55 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038428008 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.4038428008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.3128806860
Short name T390
Test name
Test status
Simulation time 29719895 ps
CPU time 1.12 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:00:52 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128806860 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3128806860
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.4121694038
Short name T463
Test name
Test status
Simulation time 2480923268 ps
CPU time 26.48 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:01:18 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121694038 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.4121694038
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.1951701963
Short name T424
Test name
Test status
Simulation time 2067448187 ps
CPU time 14.39 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:01:06 AM UTC 24
Peak memory 210672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951701963 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.1951701963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.2160542269
Short name T394
Test name
Test status
Simulation time 20063430 ps
CPU time 1.18 seconds
Started Sep 04 02:00:51 AM UTC 24
Finished Sep 04 02:00:53 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160542269 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.2160542269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3281049085
Short name T397
Test name
Test status
Simulation time 184536380 ps
CPU time 2.15 seconds
Started Sep 04 02:00:51 AM UTC 24
Finished Sep 04 02:00:55 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281049085
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.3281049085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1243895411
Short name T395
Test name
Test status
Simulation time 57462136 ps
CPU time 1.41 seconds
Started Sep 04 02:00:51 AM UTC 24
Finished Sep 04 02:00:54 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243895411
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.1243895411
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.3625198000
Short name T369
Test name
Test status
Simulation time 47660056 ps
CPU time 0.94 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:00:52 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625198000 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3625198000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.3867657976
Short name T413
Test name
Test status
Simulation time 1070997623 ps
CPU time 7.05 seconds
Started Sep 04 02:00:53 AM UTC 24
Finished Sep 04 02:01:01 AM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867657976 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3867657976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.4125123963
Short name T389
Test name
Test status
Simulation time 24842136 ps
CPU time 1.21 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:00:52 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125123963 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.4125123963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.841004046
Short name T510
Test name
Test status
Simulation time 11793394041 ps
CPU time 41.36 seconds
Started Sep 04 02:00:53 AM UTC 24
Finished Sep 04 02:01:36 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841004046 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.841004046
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.355405988
Short name T161
Test name
Test status
Simulation time 2971503324 ps
CPU time 40.14 seconds
Started Sep 04 02:00:53 AM UTC 24
Finished Sep 04 02:01:34 AM UTC 24
Peak memory 224616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355405988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.355405988
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.472100737
Short name T391
Test name
Test status
Simulation time 14227066 ps
CPU time 1.08 seconds
Started Sep 04 02:00:50 AM UTC 24
Finished Sep 04 02:00:52 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472100737 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.472100737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.1271203922
Short name T415
Test name
Test status
Simulation time 36252152 ps
CPU time 1.27 seconds
Started Sep 04 02:01:00 AM UTC 24
Finished Sep 04 02:01:02 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271203922 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.1271203922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.626348840
Short name T409
Test name
Test status
Simulation time 21013105 ps
CPU time 1.25 seconds
Started Sep 04 02:00:58 AM UTC 24
Finished Sep 04 02:01:00 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626348840 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.626348840
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.1251215655
Short name T406
Test name
Test status
Simulation time 29193452 ps
CPU time 1.09 seconds
Started Sep 04 02:00:56 AM UTC 24
Finished Sep 04 02:00:58 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251215655 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1251215655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.324695482
Short name T414
Test name
Test status
Simulation time 26271993 ps
CPU time 1.31 seconds
Started Sep 04 02:00:59 AM UTC 24
Finished Sep 04 02:01:01 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324695482 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.324695482
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2482840343
Short name T400
Test name
Test status
Simulation time 33028011 ps
CPU time 1.24 seconds
Started Sep 04 02:00:54 AM UTC 24
Finished Sep 04 02:00:56 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482840343 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2482840343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.1238282760
Short name T416
Test name
Test status
Simulation time 560802839 ps
CPU time 7.24 seconds
Started Sep 04 02:00:54 AM UTC 24
Finished Sep 04 02:01:02 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238282760 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1238282760
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.1064891236
Short name T435
Test name
Test status
Simulation time 1469382417 ps
CPU time 12.39 seconds
Started Sep 04 02:00:55 AM UTC 24
Finished Sep 04 02:01:09 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064891236 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.1064891236
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.1173199000
Short name T407
Test name
Test status
Simulation time 78569282 ps
CPU time 1.55 seconds
Started Sep 04 02:00:56 AM UTC 24
Finished Sep 04 02:00:59 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173199000 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.1173199000
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3359436291
Short name T411
Test name
Test status
Simulation time 23945962 ps
CPU time 1.3 seconds
Started Sep 04 02:00:58 AM UTC 24
Finished Sep 04 02:01:00 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359436291
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.3359436291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.4061275072
Short name T412
Test name
Test status
Simulation time 35958849 ps
CPU time 1.31 seconds
Started Sep 04 02:00:58 AM UTC 24
Finished Sep 04 02:01:00 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061275072
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.4061275072
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.2896998936
Short name T403
Test name
Test status
Simulation time 23890026 ps
CPU time 1.14 seconds
Started Sep 04 02:00:55 AM UTC 24
Finished Sep 04 02:00:57 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896998936 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.2896998936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.909662055
Short name T419
Test name
Test status
Simulation time 430985184 ps
CPU time 3.72 seconds
Started Sep 04 02:00:59 AM UTC 24
Finished Sep 04 02:01:03 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909662055 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.909662055
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.972325958
Short name T405
Test name
Test status
Simulation time 294193151 ps
CPU time 2.72 seconds
Started Sep 04 02:00:54 AM UTC 24
Finished Sep 04 02:00:58 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972325958 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.972325958
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.2426509047
Short name T473
Test name
Test status
Simulation time 5106383194 ps
CPU time 21.45 seconds
Started Sep 04 02:00:59 AM UTC 24
Finished Sep 04 02:01:22 AM UTC 24
Peak memory 210992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426509047 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2426509047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.1117728472
Short name T185
Test name
Test status
Simulation time 3800301645 ps
CPU time 49.61 seconds
Started Sep 04 02:00:59 AM UTC 24
Finished Sep 04 02:01:50 AM UTC 24
Peak memory 220296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117728472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1117728472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.3188866325
Short name T404
Test name
Test status
Simulation time 55704147 ps
CPU time 1.32 seconds
Started Sep 04 02:00:55 AM UTC 24
Finished Sep 04 02:00:58 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188866325 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3188866325
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.1130858354
Short name T430
Test name
Test status
Simulation time 15334249 ps
CPU time 1.14 seconds
Started Sep 04 02:01:05 AM UTC 24
Finished Sep 04 02:01:07 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130858354 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.1130858354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1973668887
Short name T428
Test name
Test status
Simulation time 20391223 ps
CPU time 1.24 seconds
Started Sep 04 02:01:04 AM UTC 24
Finished Sep 04 02:01:06 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973668887 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1973668887
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.3839640458
Short name T422
Test name
Test status
Simulation time 30668494 ps
CPU time 1.1 seconds
Started Sep 04 02:01:03 AM UTC 24
Finished Sep 04 02:01:05 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839640458 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3839640458
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.3998074750
Short name T429
Test name
Test status
Simulation time 23869102 ps
CPU time 1.27 seconds
Started Sep 04 02:01:04 AM UTC 24
Finished Sep 04 02:01:06 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998074750 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.3998074750
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.419513017
Short name T418
Test name
Test status
Simulation time 13412801 ps
CPU time 1.11 seconds
Started Sep 04 02:01:01 AM UTC 24
Finished Sep 04 02:01:03 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419513017 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.419513017
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.654458116
Short name T431
Test name
Test status
Simulation time 722468849 ps
CPU time 5.77 seconds
Started Sep 04 02:01:01 AM UTC 24
Finished Sep 04 02:01:08 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654458116 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.654458116
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.4082189800
Short name T449
Test name
Test status
Simulation time 1590404100 ps
CPU time 10.44 seconds
Started Sep 04 02:01:01 AM UTC 24
Finished Sep 04 02:01:13 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082189800 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.4082189800
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.4236855210
Short name T425
Test name
Test status
Simulation time 162900948 ps
CPU time 2.2 seconds
Started Sep 04 02:01:03 AM UTC 24
Finished Sep 04 02:01:06 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236855210 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.4236855210
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1582657215
Short name T426
Test name
Test status
Simulation time 20007181 ps
CPU time 1.18 seconds
Started Sep 04 02:01:04 AM UTC 24
Finished Sep 04 02:01:06 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582657215
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.1582657215
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1241684216
Short name T427
Test name
Test status
Simulation time 54566190 ps
CPU time 1.19 seconds
Started Sep 04 02:01:04 AM UTC 24
Finished Sep 04 02:01:06 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241684216
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.1241684216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.3748461265
Short name T420
Test name
Test status
Simulation time 17864696 ps
CPU time 1.15 seconds
Started Sep 04 02:01:01 AM UTC 24
Finished Sep 04 02:01:04 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748461265 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3748461265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.981469746
Short name T447
Test name
Test status
Simulation time 570914375 ps
CPU time 6.37 seconds
Started Sep 04 02:01:05 AM UTC 24
Finished Sep 04 02:01:12 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981469746 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.981469746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.3459056032
Short name T159
Test name
Test status
Simulation time 22328634 ps
CPU time 1.26 seconds
Started Sep 04 02:01:00 AM UTC 24
Finished Sep 04 02:01:02 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459056032 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.3459056032
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.287029119
Short name T565
Test name
Test status
Simulation time 9533557746 ps
CPU time 49.21 seconds
Started Sep 04 02:01:05 AM UTC 24
Finished Sep 04 02:01:56 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287029119 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.287029119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.511555459
Short name T605
Test name
Test status
Simulation time 4214907028 ps
CPU time 65.65 seconds
Started Sep 04 02:01:05 AM UTC 24
Finished Sep 04 02:02:12 AM UTC 24
Peak memory 219912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=511555459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.511555459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.489304269
Short name T421
Test name
Test status
Simulation time 19811049 ps
CPU time 1.19 seconds
Started Sep 04 02:01:01 AM UTC 24
Finished Sep 04 02:01:04 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489304269 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.489304269
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.3852357376
Short name T448
Test name
Test status
Simulation time 49953806 ps
CPU time 1.33 seconds
Started Sep 04 02:01:10 AM UTC 24
Finished Sep 04 02:01:13 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852357376 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.3852357376
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.204708822
Short name T442
Test name
Test status
Simulation time 28551385 ps
CPU time 1.22 seconds
Started Sep 04 02:01:09 AM UTC 24
Finished Sep 04 02:01:11 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204708822 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.204708822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.1483981110
Short name T437
Test name
Test status
Simulation time 18418995 ps
CPU time 1.04 seconds
Started Sep 04 02:01:08 AM UTC 24
Finished Sep 04 02:01:10 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483981110 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.1483981110
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.3727343765
Short name T446
Test name
Test status
Simulation time 47084792 ps
CPU time 1.3 seconds
Started Sep 04 02:01:10 AM UTC 24
Finished Sep 04 02:01:12 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727343765 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.3727343765
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.340785100
Short name T432
Test name
Test status
Simulation time 13142334 ps
CPU time 1.1 seconds
Started Sep 04 02:01:06 AM UTC 24
Finished Sep 04 02:01:08 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340785100 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.340785100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.1239147867
Short name T443
Test name
Test status
Simulation time 457594527 ps
CPU time 3.86 seconds
Started Sep 04 02:01:06 AM UTC 24
Finished Sep 04 02:01:11 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239147867 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1239147867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.3342977811
Short name T480
Test name
Test status
Simulation time 1708015163 ps
CPU time 16.85 seconds
Started Sep 04 02:01:06 AM UTC 24
Finished Sep 04 02:01:24 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342977811 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.3342977811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.1331969039
Short name T440
Test name
Test status
Simulation time 106086084 ps
CPU time 1.95 seconds
Started Sep 04 02:01:08 AM UTC 24
Finished Sep 04 02:01:11 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331969039 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.1331969039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2514553012
Short name T444
Test name
Test status
Simulation time 124765567 ps
CPU time 1.86 seconds
Started Sep 04 02:01:09 AM UTC 24
Finished Sep 04 02:01:12 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514553012
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.2514553012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3607962650
Short name T441
Test name
Test status
Simulation time 20769619 ps
CPU time 1.11 seconds
Started Sep 04 02:01:09 AM UTC 24
Finished Sep 04 02:01:11 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607962650
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.3607962650
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.111545783
Short name T434
Test name
Test status
Simulation time 39905660 ps
CPU time 1.21 seconds
Started Sep 04 02:01:06 AM UTC 24
Finished Sep 04 02:01:09 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111545783 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.111545783
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.4064936757
Short name T452
Test name
Test status
Simulation time 225439590 ps
CPU time 2.58 seconds
Started Sep 04 02:01:10 AM UTC 24
Finished Sep 04 02:01:14 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064936757 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.4064936757
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.2238675749
Short name T433
Test name
Test status
Simulation time 14836806 ps
CPU time 1.17 seconds
Started Sep 04 02:01:06 AM UTC 24
Finished Sep 04 02:01:08 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238675749 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2238675749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.3403930064
Short name T538
Test name
Test status
Simulation time 6317348913 ps
CPU time 33.34 seconds
Started Sep 04 02:01:10 AM UTC 24
Finished Sep 04 02:01:45 AM UTC 24
Peak memory 210888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403930064 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.3403930064
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.2835156033
Short name T814
Test name
Test status
Simulation time 13185907114 ps
CPU time 116.42 seconds
Started Sep 04 02:01:10 AM UTC 24
Finished Sep 04 02:03:09 AM UTC 24
Peak memory 226472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835156033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2835156033
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.4090606151
Short name T438
Test name
Test status
Simulation time 64824685 ps
CPU time 1.54 seconds
Started Sep 04 02:01:08 AM UTC 24
Finished Sep 04 02:01:10 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090606151 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.4090606151
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.1250978251
Short name T462
Test name
Test status
Simulation time 35333054 ps
CPU time 1.18 seconds
Started Sep 04 02:01:15 AM UTC 24
Finished Sep 04 02:01:17 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250978251 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.1250978251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2014982013
Short name T461
Test name
Test status
Simulation time 67494847 ps
CPU time 1.52 seconds
Started Sep 04 02:01:14 AM UTC 24
Finished Sep 04 02:01:16 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014982013 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.2014982013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.1812658713
Short name T455
Test name
Test status
Simulation time 58270394 ps
CPU time 1.24 seconds
Started Sep 04 02:01:13 AM UTC 24
Finished Sep 04 02:01:15 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812658713 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1812658713
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.1741978385
Short name T459
Test name
Test status
Simulation time 18298693 ps
CPU time 1.16 seconds
Started Sep 04 02:01:14 AM UTC 24
Finished Sep 04 02:01:16 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741978385 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.1741978385
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.3128627354
Short name T453
Test name
Test status
Simulation time 98102644 ps
CPU time 1.56 seconds
Started Sep 04 02:01:11 AM UTC 24
Finished Sep 04 02:01:14 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128627354 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3128627354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.474577824
Short name T497
Test name
Test status
Simulation time 1516224129 ps
CPU time 17.34 seconds
Started Sep 04 02:01:11 AM UTC 24
Finished Sep 04 02:01:30 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474577824 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.474577824
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.104647597
Short name T465
Test name
Test status
Simulation time 662368028 ps
CPU time 5.77 seconds
Started Sep 04 02:01:13 AM UTC 24
Finished Sep 04 02:01:19 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104647597 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.104647597
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.1164744360
Short name T460
Test name
Test status
Simulation time 41946770 ps
CPU time 1.41 seconds
Started Sep 04 02:01:14 AM UTC 24
Finished Sep 04 02:01:16 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164744360 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1164744360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.383755254
Short name T457
Test name
Test status
Simulation time 19127618 ps
CPU time 1.21 seconds
Started Sep 04 02:01:14 AM UTC 24
Finished Sep 04 02:01:16 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383755254 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.383755254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3852428850
Short name T458
Test name
Test status
Simulation time 23191176 ps
CPU time 1.15 seconds
Started Sep 04 02:01:14 AM UTC 24
Finished Sep 04 02:01:16 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852428850
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.3852428850
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.2159982929
Short name T454
Test name
Test status
Simulation time 43794897 ps
CPU time 1.23 seconds
Started Sep 04 02:01:13 AM UTC 24
Finished Sep 04 02:01:15 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159982929 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2159982929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.1247145401
Short name T177
Test name
Test status
Simulation time 672859563 ps
CPU time 6.32 seconds
Started Sep 04 02:01:14 AM UTC 24
Finished Sep 04 02:01:21 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1247145401 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.1247145401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.943792894
Short name T451
Test name
Test status
Simulation time 69138060 ps
CPU time 1.18 seconds
Started Sep 04 02:01:11 AM UTC 24
Finished Sep 04 02:01:13 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943792894 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.943792894
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.2211697895
Short name T674
Test name
Test status
Simulation time 9483068571 ps
CPU time 77.05 seconds
Started Sep 04 02:01:15 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211697895 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2211697895
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.2436790375
Short name T839
Test name
Test status
Simulation time 15155625796 ps
CPU time 119.61 seconds
Started Sep 04 02:01:15 AM UTC 24
Finished Sep 04 02:03:17 AM UTC 24
Peak memory 220292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436790375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.2436790375
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.1135890092
Short name T456
Test name
Test status
Simulation time 125623378 ps
CPU time 1.95 seconds
Started Sep 04 02:01:13 AM UTC 24
Finished Sep 04 02:01:16 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135890092 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1135890092
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.3442117027
Short name T477
Test name
Test status
Simulation time 12393899 ps
CPU time 1.07 seconds
Started Sep 04 02:01:21 AM UTC 24
Finished Sep 04 02:01:23 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442117027 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.3442117027
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2523458429
Short name T474
Test name
Test status
Simulation time 23344225 ps
CPU time 1.26 seconds
Started Sep 04 02:01:20 AM UTC 24
Finished Sep 04 02:01:22 AM UTC 24
Peak memory 210044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523458429 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.2523458429
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.1182150220
Short name T467
Test name
Test status
Simulation time 16859784 ps
CPU time 1.09 seconds
Started Sep 04 02:01:18 AM UTC 24
Finished Sep 04 02:01:20 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182150220 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1182150220
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.2764871118
Short name T475
Test name
Test status
Simulation time 26141816 ps
CPU time 1.18 seconds
Started Sep 04 02:01:20 AM UTC 24
Finished Sep 04 02:01:22 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764871118 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.2764871118
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.605244205
Short name T466
Test name
Test status
Simulation time 238700649 ps
CPU time 2.48 seconds
Started Sep 04 02:01:16 AM UTC 24
Finished Sep 04 02:01:20 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605244205 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.605244205
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.67441147
Short name T468
Test name
Test status
Simulation time 350936132 ps
CPU time 2.41 seconds
Started Sep 04 02:01:16 AM UTC 24
Finished Sep 04 02:01:20 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67441147 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.67441147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.3959781076
Short name T501
Test name
Test status
Simulation time 2070418800 ps
CPU time 13.16 seconds
Started Sep 04 02:01:18 AM UTC 24
Finished Sep 04 02:01:32 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959781076 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.3959781076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.1159786935
Short name T472
Test name
Test status
Simulation time 161517276 ps
CPU time 1.38 seconds
Started Sep 04 02:01:19 AM UTC 24
Finished Sep 04 02:01:21 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159786935 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.1159786935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3240928740
Short name T476
Test name
Test status
Simulation time 190750840 ps
CPU time 2.13 seconds
Started Sep 04 02:01:20 AM UTC 24
Finished Sep 04 02:01:23 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240928740
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.3240928740
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2009433286
Short name T471
Test name
Test status
Simulation time 57052121 ps
CPU time 1.34 seconds
Started Sep 04 02:01:19 AM UTC 24
Finished Sep 04 02:01:21 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009433286
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.2009433286
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.1214833929
Short name T469
Test name
Test status
Simulation time 74372635 ps
CPU time 1.39 seconds
Started Sep 04 02:01:18 AM UTC 24
Finished Sep 04 02:01:20 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214833929 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1214833929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.1007532944
Short name T487
Test name
Test status
Simulation time 495395991 ps
CPU time 3.91 seconds
Started Sep 04 02:01:21 AM UTC 24
Finished Sep 04 02:01:26 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007532944 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1007532944
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.1708647440
Short name T464
Test name
Test status
Simulation time 39602194 ps
CPU time 1.36 seconds
Started Sep 04 02:01:16 AM UTC 24
Finished Sep 04 02:01:19 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708647440 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.1708647440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.4174166322
Short name T753
Test name
Test status
Simulation time 10640551750 ps
CPU time 91.64 seconds
Started Sep 04 02:01:21 AM UTC 24
Finished Sep 04 02:02:55 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174166322 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.4174166322
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.3346675006
Short name T186
Test name
Test status
Simulation time 1952864827 ps
CPU time 32.56 seconds
Started Sep 04 02:01:21 AM UTC 24
Finished Sep 04 02:01:55 AM UTC 24
Peak memory 222408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346675006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.3346675006
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.425801086
Short name T470
Test name
Test status
Simulation time 66260720 ps
CPU time 1.48 seconds
Started Sep 04 02:01:18 AM UTC 24
Finished Sep 04 02:01:20 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425801086 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.425801086
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.735073979
Short name T492
Test name
Test status
Simulation time 16302750 ps
CPU time 1.13 seconds
Started Sep 04 02:01:26 AM UTC 24
Finished Sep 04 02:01:29 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735073979 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.735073979
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.2364620973
Short name T490
Test name
Test status
Simulation time 18092763 ps
CPU time 1.23 seconds
Started Sep 04 02:01:25 AM UTC 24
Finished Sep 04 02:01:27 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364620973 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.2364620973
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.1856441158
Short name T481
Test name
Test status
Simulation time 15111447 ps
CPU time 1.05 seconds
Started Sep 04 02:01:23 AM UTC 24
Finished Sep 04 02:01:25 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856441158 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1856441158
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.1976091935
Short name T491
Test name
Test status
Simulation time 39831218 ps
CPU time 1.38 seconds
Started Sep 04 02:01:25 AM UTC 24
Finished Sep 04 02:01:28 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976091935 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.1976091935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.827803181
Short name T478
Test name
Test status
Simulation time 27956200 ps
CPU time 1.33 seconds
Started Sep 04 02:01:21 AM UTC 24
Finished Sep 04 02:01:24 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827803181 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.827803181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.2642343733
Short name T522
Test name
Test status
Simulation time 1527975281 ps
CPU time 16.93 seconds
Started Sep 04 02:01:23 AM UTC 24
Finished Sep 04 02:01:41 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642343733 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.2642343733
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.1544530930
Short name T486
Test name
Test status
Simulation time 158933922 ps
CPU time 2.08 seconds
Started Sep 04 02:01:23 AM UTC 24
Finished Sep 04 02:01:26 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544530930 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.1544530930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.2130668974
Short name T484
Test name
Test status
Simulation time 32110508 ps
CPU time 1.45 seconds
Started Sep 04 02:01:23 AM UTC 24
Finished Sep 04 02:01:25 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130668974 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.2130668974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1469386267
Short name T489
Test name
Test status
Simulation time 35687625 ps
CPU time 1.3 seconds
Started Sep 04 02:01:24 AM UTC 24
Finished Sep 04 02:01:26 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469386267
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.1469386267
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1838716433
Short name T488
Test name
Test status
Simulation time 20622929 ps
CPU time 1.24 seconds
Started Sep 04 02:01:24 AM UTC 24
Finished Sep 04 02:01:26 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838716433
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.1838716433
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.2092968730
Short name T482
Test name
Test status
Simulation time 68720246 ps
CPU time 1.34 seconds
Started Sep 04 02:01:23 AM UTC 24
Finished Sep 04 02:01:25 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092968730 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2092968730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.1238345138
Short name T506
Test name
Test status
Simulation time 892438342 ps
CPU time 6.83 seconds
Started Sep 04 02:01:25 AM UTC 24
Finished Sep 04 02:01:33 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238345138 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1238345138
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.4184711650
Short name T479
Test name
Test status
Simulation time 61284105 ps
CPU time 1.52 seconds
Started Sep 04 02:01:21 AM UTC 24
Finished Sep 04 02:01:24 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184711650 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.4184711650
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.3193471351
Short name T680
Test name
Test status
Simulation time 7780585908 ps
CPU time 69.33 seconds
Started Sep 04 02:01:25 AM UTC 24
Finished Sep 04 02:02:36 AM UTC 24
Peak memory 210996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3193471351 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.3193471351
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.2691581127
Short name T188
Test name
Test status
Simulation time 3282169828 ps
CPU time 62.18 seconds
Started Sep 04 02:01:25 AM UTC 24
Finished Sep 04 02:02:29 AM UTC 24
Peak memory 220224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691581127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2691581127
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.1025473534
Short name T483
Test name
Test status
Simulation time 34288050 ps
CPU time 1.34 seconds
Started Sep 04 02:01:23 AM UTC 24
Finished Sep 04 02:01:25 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025473534 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1025473534
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.1654323035
Short name T507
Test name
Test status
Simulation time 15492638 ps
CPU time 1.12 seconds
Started Sep 04 02:01:32 AM UTC 24
Finished Sep 04 02:01:34 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654323035 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.1654323035
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3109463974
Short name T503
Test name
Test status
Simulation time 29428629 ps
CPU time 1.14 seconds
Started Sep 04 02:01:30 AM UTC 24
Finished Sep 04 02:01:33 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109463974 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.3109463974
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.2452277456
Short name T498
Test name
Test status
Simulation time 14574498 ps
CPU time 1.02 seconds
Started Sep 04 02:01:28 AM UTC 24
Finished Sep 04 02:01:30 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452277456 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2452277456
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.1891634662
Short name T505
Test name
Test status
Simulation time 65047035 ps
CPU time 1.42 seconds
Started Sep 04 02:01:30 AM UTC 24
Finished Sep 04 02:01:33 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891634662 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.1891634662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.2470313232
Short name T493
Test name
Test status
Simulation time 14172520 ps
CPU time 1.12 seconds
Started Sep 04 02:01:27 AM UTC 24
Finished Sep 04 02:01:29 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470313232 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.2470313232
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.2829290855
Short name T514
Test name
Test status
Simulation time 1219176063 ps
CPU time 9.05 seconds
Started Sep 04 02:01:27 AM UTC 24
Finished Sep 04 02:01:37 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829290855 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2829290855
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.1463361237
Short name T525
Test name
Test status
Simulation time 1576916698 ps
CPU time 13.39 seconds
Started Sep 04 02:01:27 AM UTC 24
Finished Sep 04 02:01:41 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463361237 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.1463361237
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.2778882076
Short name T500
Test name
Test status
Simulation time 43123608 ps
CPU time 1.4 seconds
Started Sep 04 02:01:29 AM UTC 24
Finished Sep 04 02:01:31 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778882076 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.2778882076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2897984845
Short name T502
Test name
Test status
Simulation time 18924603 ps
CPU time 1.22 seconds
Started Sep 04 02:01:30 AM UTC 24
Finished Sep 04 02:01:32 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897984845
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.2897984845
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1621919079
Short name T504
Test name
Test status
Simulation time 50904424 ps
CPU time 1.4 seconds
Started Sep 04 02:01:30 AM UTC 24
Finished Sep 04 02:01:33 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621919079
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.1621919079
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.3550692343
Short name T495
Test name
Test status
Simulation time 41778486 ps
CPU time 1.22 seconds
Started Sep 04 02:01:27 AM UTC 24
Finished Sep 04 02:01:29 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550692343 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3550692343
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.2685067181
Short name T178
Test name
Test status
Simulation time 684261905 ps
CPU time 6.03 seconds
Started Sep 04 02:01:30 AM UTC 24
Finished Sep 04 02:01:38 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685067181 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2685067181
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.905326984
Short name T494
Test name
Test status
Simulation time 19655415 ps
CPU time 1.19 seconds
Started Sep 04 02:01:27 AM UTC 24
Finished Sep 04 02:01:29 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905326984 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.905326984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.1429172891
Short name T572
Test name
Test status
Simulation time 5184684755 ps
CPU time 25.39 seconds
Started Sep 04 02:01:32 AM UTC 24
Finished Sep 04 02:01:58 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429172891 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.1429172891
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.514139465
Short name T626
Test name
Test status
Simulation time 2737952423 ps
CPU time 48.04 seconds
Started Sep 04 02:01:30 AM UTC 24
Finished Sep 04 02:02:20 AM UTC 24
Peak memory 224392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514139465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.514139465
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.3754132561
Short name T499
Test name
Test status
Simulation time 50331963 ps
CPU time 1.44 seconds
Started Sep 04 02:01:28 AM UTC 24
Finished Sep 04 02:01:30 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754132561 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3754132561
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.2129749120
Short name T520
Test name
Test status
Simulation time 21117962 ps
CPU time 1.26 seconds
Started Sep 04 02:01:38 AM UTC 24
Finished Sep 04 02:01:40 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129749120 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.2129749120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2601468153
Short name T517
Test name
Test status
Simulation time 22815939 ps
CPU time 1.27 seconds
Started Sep 04 02:01:36 AM UTC 24
Finished Sep 04 02:01:39 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601468153 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.2601468153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.2233953189
Short name T511
Test name
Test status
Simulation time 24808200 ps
CPU time 0.92 seconds
Started Sep 04 02:01:34 AM UTC 24
Finished Sep 04 02:01:36 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233953189 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2233953189
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.4219108147
Short name T518
Test name
Test status
Simulation time 90326410 ps
CPU time 1.7 seconds
Started Sep 04 02:01:36 AM UTC 24
Finished Sep 04 02:01:39 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219108147 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.4219108147
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.2807995445
Short name T509
Test name
Test status
Simulation time 50182062 ps
CPU time 1.36 seconds
Started Sep 04 02:01:33 AM UTC 24
Finished Sep 04 02:01:35 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807995445 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.2807995445
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.4176209929
Short name T549
Test name
Test status
Simulation time 1155121290 ps
CPU time 13.95 seconds
Started Sep 04 02:01:34 AM UTC 24
Finished Sep 04 02:01:49 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176209929 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.4176209929
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.63605388
Short name T528
Test name
Test status
Simulation time 1218117784 ps
CPU time 7.55 seconds
Started Sep 04 02:01:34 AM UTC 24
Finished Sep 04 02:01:43 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63605388 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.63605388
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.2123299673
Short name T521
Test name
Test status
Simulation time 449456158 ps
CPU time 3.47 seconds
Started Sep 04 02:01:35 AM UTC 24
Finished Sep 04 02:01:40 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123299673 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.2123299673
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.3996483558
Short name T516
Test name
Test status
Simulation time 43448040 ps
CPU time 1.25 seconds
Started Sep 04 02:01:35 AM UTC 24
Finished Sep 04 02:01:38 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996483558
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.3996483558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1121070039
Short name T515
Test name
Test status
Simulation time 55035489 ps
CPU time 1.36 seconds
Started Sep 04 02:01:35 AM UTC 24
Finished Sep 04 02:01:38 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121070039
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.1121070039
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.4191076417
Short name T512
Test name
Test status
Simulation time 18263503 ps
CPU time 1.11 seconds
Started Sep 04 02:01:34 AM UTC 24
Finished Sep 04 02:01:36 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191076417 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.4191076417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.2930420313
Short name T540
Test name
Test status
Simulation time 713661226 ps
CPU time 7.97 seconds
Started Sep 04 02:01:36 AM UTC 24
Finished Sep 04 02:01:45 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930420313 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2930420313
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.1540611832
Short name T508
Test name
Test status
Simulation time 23314191 ps
CPU time 1.02 seconds
Started Sep 04 02:01:33 AM UTC 24
Finished Sep 04 02:01:35 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540611832 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1540611832
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.3856932846
Short name T530
Test name
Test status
Simulation time 480183318 ps
CPU time 4.24 seconds
Started Sep 04 02:01:38 AM UTC 24
Finished Sep 04 02:01:43 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856932846 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.3856932846
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.2484676378
Short name T663
Test name
Test status
Simulation time 7247779366 ps
CPU time 53.33 seconds
Started Sep 04 02:01:38 AM UTC 24
Finished Sep 04 02:02:32 AM UTC 24
Peak memory 220296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484676378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.2484676378
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.537475660
Short name T513
Test name
Test status
Simulation time 16212270 ps
CPU time 1.04 seconds
Started Sep 04 02:01:34 AM UTC 24
Finished Sep 04 02:01:36 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537475660 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.537475660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.3303229424
Short name T47
Test name
Test status
Simulation time 28937588 ps
CPU time 1.18 seconds
Started Sep 04 01:59:11 AM UTC 24
Finished Sep 04 01:59:13 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303229424 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.3303229424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1546705955
Short name T37
Test name
Test status
Simulation time 18021395 ps
CPU time 1.21 seconds
Started Sep 04 01:59:10 AM UTC 24
Finished Sep 04 01:59:12 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546705955 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.1546705955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.836642100
Short name T23
Test name
Test status
Simulation time 35185291 ps
CPU time 0.86 seconds
Started Sep 04 01:59:08 AM UTC 24
Finished Sep 04 01:59:10 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836642100 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.836642100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.108548610
Short name T25
Test name
Test status
Simulation time 26351223 ps
CPU time 1.04 seconds
Started Sep 04 01:59:10 AM UTC 24
Finished Sep 04 01:59:11 AM UTC 24
Peak memory 209132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108548610 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.108548610
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.2379150291
Short name T209
Test name
Test status
Simulation time 17774812 ps
CPU time 1.02 seconds
Started Sep 04 01:59:07 AM UTC 24
Finished Sep 04 01:59:09 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379150291 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.2379150291
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.743425735
Short name T13
Test name
Test status
Simulation time 1329885915 ps
CPU time 7.55 seconds
Started Sep 04 01:59:08 AM UTC 24
Finished Sep 04 01:59:17 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743425735 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.743425735
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.1926792726
Short name T58
Test name
Test status
Simulation time 1963238857 ps
CPU time 11.93 seconds
Started Sep 04 01:59:08 AM UTC 24
Finished Sep 04 01:59:21 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926792726 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.1926792726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.4200178136
Short name T45
Test name
Test status
Simulation time 39016188 ps
CPU time 1.34 seconds
Started Sep 04 01:59:09 AM UTC 24
Finished Sep 04 01:59:12 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200178136 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.4200178136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.552345795
Short name T26
Test name
Test status
Simulation time 23370027 ps
CPU time 1.26 seconds
Started Sep 04 01:59:09 AM UTC 24
Finished Sep 04 01:59:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552345795 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.552345795
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.216107112
Short name T44
Test name
Test status
Simulation time 85203505 ps
CPU time 1.31 seconds
Started Sep 04 01:59:09 AM UTC 24
Finished Sep 04 01:59:12 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216107112 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.216107112
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.4230282603
Short name T22
Test name
Test status
Simulation time 35884003 ps
CPU time 0.86 seconds
Started Sep 04 01:59:08 AM UTC 24
Finished Sep 04 01:59:10 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230282603 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.4230282603
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.1750067584
Short name T50
Test name
Test status
Simulation time 1304622015 ps
CPU time 4.91 seconds
Started Sep 04 01:59:11 AM UTC 24
Finished Sep 04 01:59:17 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750067584 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.1750067584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.4060712972
Short name T62
Test name
Test status
Simulation time 640986728 ps
CPU time 6.3 seconds
Started Sep 04 01:59:11 AM UTC 24
Finished Sep 04 01:59:18 AM UTC 24
Peak memory 242916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060712972 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.4060712972
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.3937766289
Short name T20
Test name
Test status
Simulation time 21264942 ps
CPU time 1.26 seconds
Started Sep 04 01:59:07 AM UTC 24
Finished Sep 04 01:59:09 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937766289 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.3937766289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.3869777146
Short name T59
Test name
Test status
Simulation time 14702576163 ps
CPU time 55.15 seconds
Started Sep 04 01:59:11 AM UTC 24
Finished Sep 04 02:00:08 AM UTC 24
Peak memory 211056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869777146 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.3869777146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.70910965
Short name T24
Test name
Test status
Simulation time 60457658 ps
CPU time 1.16 seconds
Started Sep 04 01:59:08 AM UTC 24
Finished Sep 04 01:59:10 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70910965 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.70910965
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.1827838831
Short name T541
Test name
Test status
Simulation time 28900332 ps
CPU time 1.18 seconds
Started Sep 04 02:01:44 AM UTC 24
Finished Sep 04 02:01:46 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827838831 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.1827838831
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1357152119
Short name T536
Test name
Test status
Simulation time 24263899 ps
CPU time 1.28 seconds
Started Sep 04 02:01:42 AM UTC 24
Finished Sep 04 02:01:45 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357152119 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1357152119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.553257441
Short name T531
Test name
Test status
Simulation time 15613642 ps
CPU time 1.08 seconds
Started Sep 04 02:01:41 AM UTC 24
Finished Sep 04 02:01:43 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553257441 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.553257441
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.3507483061
Short name T537
Test name
Test status
Simulation time 23868245 ps
CPU time 1.27 seconds
Started Sep 04 02:01:42 AM UTC 24
Finished Sep 04 02:01:45 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507483061 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.3507483061
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.2900936192
Short name T523
Test name
Test status
Simulation time 13887814 ps
CPU time 1.12 seconds
Started Sep 04 02:01:39 AM UTC 24
Finished Sep 04 02:01:41 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900936192 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2900936192
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.771846749
Short name T557
Test name
Test status
Simulation time 1681272594 ps
CPU time 13.08 seconds
Started Sep 04 02:01:39 AM UTC 24
Finished Sep 04 02:01:53 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771846749 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.771846749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.2943597539
Short name T485
Test name
Test status
Simulation time 1118761347 ps
CPU time 7.12 seconds
Started Sep 04 02:01:40 AM UTC 24
Finished Sep 04 02:01:48 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943597539 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.2943597539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.2941339324
Short name T532
Test name
Test status
Simulation time 30477113 ps
CPU time 1.4 seconds
Started Sep 04 02:01:41 AM UTC 24
Finished Sep 04 02:01:43 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941339324 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.2941339324
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.647809260
Short name T534
Test name
Test status
Simulation time 162232547 ps
CPU time 2 seconds
Started Sep 04 02:01:41 AM UTC 24
Finished Sep 04 02:01:44 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647809260 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.647809260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.2798944101
Short name T533
Test name
Test status
Simulation time 26066808 ps
CPU time 1.3 seconds
Started Sep 04 02:01:41 AM UTC 24
Finished Sep 04 02:01:43 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798944101
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.2798944101
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.2767208332
Short name T526
Test name
Test status
Simulation time 12199265 ps
CPU time 1.08 seconds
Started Sep 04 02:01:40 AM UTC 24
Finished Sep 04 02:01:42 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767208332 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2767208332
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.267364142
Short name T539
Test name
Test status
Simulation time 148623061 ps
CPU time 1.71 seconds
Started Sep 04 02:01:42 AM UTC 24
Finished Sep 04 02:01:45 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267364142 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.267364142
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.4265906202
Short name T524
Test name
Test status
Simulation time 42531851 ps
CPU time 1.3 seconds
Started Sep 04 02:01:39 AM UTC 24
Finished Sep 04 02:01:41 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265906202 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.4265906202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.2650020197
Short name T728
Test name
Test status
Simulation time 7063499523 ps
CPU time 63.3 seconds
Started Sep 04 02:01:44 AM UTC 24
Finished Sep 04 02:02:48 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650020197 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.2650020197
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.1560221707
Short name T845
Test name
Test status
Simulation time 14460485733 ps
CPU time 103.66 seconds
Started Sep 04 02:01:44 AM UTC 24
Finished Sep 04 02:03:29 AM UTC 24
Peak memory 226432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560221707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.1560221707
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.1434065213
Short name T527
Test name
Test status
Simulation time 25523837 ps
CPU time 1.3 seconds
Started Sep 04 02:01:40 AM UTC 24
Finished Sep 04 02:01:42 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434065213 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1434065213
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.971010936
Short name T552
Test name
Test status
Simulation time 12904481 ps
CPU time 1.1 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:01:52 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971010936 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.971010936
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.499505539
Short name T548
Test name
Test status
Simulation time 33807367 ps
CPU time 1.3 seconds
Started Sep 04 02:01:46 AM UTC 24
Finished Sep 04 02:01:49 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499505539 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.499505539
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.2936128064
Short name T529
Test name
Test status
Simulation time 45429434 ps
CPU time 1.17 seconds
Started Sep 04 02:01:46 AM UTC 24
Finished Sep 04 02:01:48 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936128064 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2936128064
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.1526056483
Short name T551
Test name
Test status
Simulation time 29575683 ps
CPU time 1.17 seconds
Started Sep 04 02:01:47 AM UTC 24
Finished Sep 04 02:01:50 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526056483 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.1526056483
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.1758992248
Short name T544
Test name
Test status
Simulation time 300997064 ps
CPU time 2.51 seconds
Started Sep 04 02:01:45 AM UTC 24
Finished Sep 04 02:01:48 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758992248 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.1758992248
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.1268455644
Short name T576
Test name
Test status
Simulation time 1282498185 ps
CPU time 13.78 seconds
Started Sep 04 02:01:45 AM UTC 24
Finished Sep 04 02:02:00 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268455644 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1268455644
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.1246834051
Short name T558
Test name
Test status
Simulation time 1108218311 ps
CPU time 7.25 seconds
Started Sep 04 02:01:45 AM UTC 24
Finished Sep 04 02:01:53 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246834051 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.1246834051
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.808630643
Short name T546
Test name
Test status
Simulation time 35188781 ps
CPU time 1.28 seconds
Started Sep 04 02:01:46 AM UTC 24
Finished Sep 04 02:01:48 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808630643 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.808630643
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2697451216
Short name T545
Test name
Test status
Simulation time 21853840 ps
CPU time 1.14 seconds
Started Sep 04 02:01:46 AM UTC 24
Finished Sep 04 02:01:48 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697451216
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.2697451216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1655647417
Short name T547
Test name
Test status
Simulation time 24869481 ps
CPU time 1.36 seconds
Started Sep 04 02:01:46 AM UTC 24
Finished Sep 04 02:01:49 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655647417
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.1655647417
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.423162662
Short name T543
Test name
Test status
Simulation time 33258423 ps
CPU time 1.13 seconds
Started Sep 04 02:01:45 AM UTC 24
Finished Sep 04 02:01:47 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423162662 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.423162662
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.289450749
Short name T574
Test name
Test status
Simulation time 936930175 ps
CPU time 9.97 seconds
Started Sep 04 02:01:47 AM UTC 24
Finished Sep 04 02:01:59 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289450749 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.289450749
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.3291833864
Short name T542
Test name
Test status
Simulation time 93599947 ps
CPU time 1.66 seconds
Started Sep 04 02:01:44 AM UTC 24
Finished Sep 04 02:01:46 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291833864 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3291833864
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.2565266985
Short name T652
Test name
Test status
Simulation time 4838439081 ps
CPU time 37.75 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:02:29 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565266985 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.2565266985
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.3171483922
Short name T190
Test name
Test status
Simulation time 7533473295 ps
CPU time 73.73 seconds
Started Sep 04 02:01:49 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171483922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3171483922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.2338747722
Short name T550
Test name
Test status
Simulation time 139091181 ps
CPU time 2.18 seconds
Started Sep 04 02:01:46 AM UTC 24
Finished Sep 04 02:01:49 AM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338747722 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.2338747722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.3020400085
Short name T567
Test name
Test status
Simulation time 15887859 ps
CPU time 1.12 seconds
Started Sep 04 02:01:55 AM UTC 24
Finished Sep 04 02:01:57 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020400085 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.3020400085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.906617700
Short name T563
Test name
Test status
Simulation time 18627775 ps
CPU time 1.18 seconds
Started Sep 04 02:01:54 AM UTC 24
Finished Sep 04 02:01:56 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906617700 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.906617700
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.2310964360
Short name T559
Test name
Test status
Simulation time 25406329 ps
CPU time 1.1 seconds
Started Sep 04 02:01:51 AM UTC 24
Finished Sep 04 02:01:53 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310964360 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.2310964360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.3737763172
Short name T564
Test name
Test status
Simulation time 26611897 ps
CPU time 1.1 seconds
Started Sep 04 02:01:54 AM UTC 24
Finished Sep 04 02:01:56 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737763172 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.3737763172
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.56788558
Short name T555
Test name
Test status
Simulation time 23070902 ps
CPU time 1.29 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:01:52 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56788558 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.56788558
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.1848025905
Short name T610
Test name
Test status
Simulation time 2478482277 ps
CPU time 23.48 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:02:15 AM UTC 24
Peak memory 210904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848025905 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1848025905
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.2763571436
Short name T566
Test name
Test status
Simulation time 954964105 ps
CPU time 5.8 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:01:57 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763571436 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.2763571436
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.2422669606
Short name T560
Test name
Test status
Simulation time 89692512 ps
CPU time 1.22 seconds
Started Sep 04 02:01:51 AM UTC 24
Finished Sep 04 02:01:53 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422669606 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.2422669606
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1442577794
Short name T562
Test name
Test status
Simulation time 63587151 ps
CPU time 1.45 seconds
Started Sep 04 02:01:52 AM UTC 24
Finished Sep 04 02:01:55 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442577794
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.1442577794
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2157336318
Short name T561
Test name
Test status
Simulation time 39431535 ps
CPU time 1.23 seconds
Started Sep 04 02:01:52 AM UTC 24
Finished Sep 04 02:01:55 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157336318
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.2157336318
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.443755634
Short name T554
Test name
Test status
Simulation time 29630218 ps
CPU time 1.15 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:01:52 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443755634 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.443755634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.3353282070
Short name T569
Test name
Test status
Simulation time 595084216 ps
CPU time 2.96 seconds
Started Sep 04 02:01:54 AM UTC 24
Finished Sep 04 02:01:58 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353282070 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3353282070
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.3742690360
Short name T553
Test name
Test status
Simulation time 16350929 ps
CPU time 1.19 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:01:52 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742690360 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3742690360
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.950031358
Short name T644
Test name
Test status
Simulation time 5244489966 ps
CPU time 31.34 seconds
Started Sep 04 02:01:55 AM UTC 24
Finished Sep 04 02:02:27 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950031358 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.950031358
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.1846902618
Short name T838
Test name
Test status
Simulation time 12826497698 ps
CPU time 81.24 seconds
Started Sep 04 02:01:54 AM UTC 24
Finished Sep 04 02:03:17 AM UTC 24
Peak memory 220456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846902618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.1846902618
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.1905473264
Short name T556
Test name
Test status
Simulation time 19184194 ps
CPU time 1.18 seconds
Started Sep 04 02:01:50 AM UTC 24
Finished Sep 04 02:01:52 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905473264 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1905473264
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.3621356031
Short name T582
Test name
Test status
Simulation time 16547712 ps
CPU time 1.03 seconds
Started Sep 04 02:02:00 AM UTC 24
Finished Sep 04 02:02:02 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621356031 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.3621356031
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.1706048868
Short name T581
Test name
Test status
Simulation time 38643141 ps
CPU time 1.25 seconds
Started Sep 04 02:01:59 AM UTC 24
Finished Sep 04 02:02:01 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1706048868 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.1706048868
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.2618473275
Short name T575
Test name
Test status
Simulation time 15625467 ps
CPU time 1.08 seconds
Started Sep 04 02:01:57 AM UTC 24
Finished Sep 04 02:01:59 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618473275 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2618473275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.3520818048
Short name T580
Test name
Test status
Simulation time 18973069 ps
CPU time 1.12 seconds
Started Sep 04 02:01:59 AM UTC 24
Finished Sep 04 02:02:01 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520818048 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.3520818048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.399399857
Short name T571
Test name
Test status
Simulation time 17531662 ps
CPU time 1.19 seconds
Started Sep 04 02:01:56 AM UTC 24
Finished Sep 04 02:01:58 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399399857 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.399399857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.327580761
Short name T596
Test name
Test status
Simulation time 1778579478 ps
CPU time 11.81 seconds
Started Sep 04 02:01:56 AM UTC 24
Finished Sep 04 02:02:09 AM UTC 24
Peak memory 210680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327580761 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.327580761
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.1882335867
Short name T595
Test name
Test status
Simulation time 1094616541 ps
CPU time 11.23 seconds
Started Sep 04 02:01:56 AM UTC 24
Finished Sep 04 02:02:08 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1882335867 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.1882335867
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.2862576131
Short name T577
Test name
Test status
Simulation time 30701710 ps
CPU time 1.45 seconds
Started Sep 04 02:01:57 AM UTC 24
Finished Sep 04 02:02:00 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862576131 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.2862576131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.679992261
Short name T579
Test name
Test status
Simulation time 23734499 ps
CPU time 1.17 seconds
Started Sep 04 02:01:59 AM UTC 24
Finished Sep 04 02:02:01 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679992261 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.679992261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3329334434
Short name T578
Test name
Test status
Simulation time 87409603 ps
CPU time 1.69 seconds
Started Sep 04 02:01:57 AM UTC 24
Finished Sep 04 02:02:00 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329334434
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.3329334434
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.708358135
Short name T570
Test name
Test status
Simulation time 12734238 ps
CPU time 1.06 seconds
Started Sep 04 02:01:56 AM UTC 24
Finished Sep 04 02:01:58 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708358135 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.708358135
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.40330275
Short name T587
Test name
Test status
Simulation time 336983762 ps
CPU time 4.09 seconds
Started Sep 04 02:01:59 AM UTC 24
Finished Sep 04 02:02:04 AM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40330275 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.40330275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.818744337
Short name T568
Test name
Test status
Simulation time 22036719 ps
CPU time 1.24 seconds
Started Sep 04 02:01:55 AM UTC 24
Finished Sep 04 02:01:57 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818744337 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.818744337
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.829067504
Short name T678
Test name
Test status
Simulation time 4509482494 ps
CPU time 33.9 seconds
Started Sep 04 02:02:00 AM UTC 24
Finished Sep 04 02:02:35 AM UTC 24
Peak memory 210724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829067504 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.829067504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.1628215922
Short name T207
Test name
Test status
Simulation time 2158510082 ps
CPU time 29.44 seconds
Started Sep 04 02:02:00 AM UTC 24
Finished Sep 04 02:02:31 AM UTC 24
Peak memory 227224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628215922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.1628215922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.1491438660
Short name T573
Test name
Test status
Simulation time 32935413 ps
CPU time 1.26 seconds
Started Sep 04 02:01:56 AM UTC 24
Finished Sep 04 02:01:58 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491438660 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1491438660
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.563824463
Short name T593
Test name
Test status
Simulation time 19380690 ps
CPU time 0.97 seconds
Started Sep 04 02:02:05 AM UTC 24
Finished Sep 04 02:02:07 AM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563824463 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.563824463
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.4271620470
Short name T592
Test name
Test status
Simulation time 23032387 ps
CPU time 1.25 seconds
Started Sep 04 02:02:05 AM UTC 24
Finished Sep 04 02:02:07 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271620470 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.4271620470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.4005492919
Short name T588
Test name
Test status
Simulation time 17970464 ps
CPU time 1.12 seconds
Started Sep 04 02:02:02 AM UTC 24
Finished Sep 04 02:02:05 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005492919 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.4005492919
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.1273796949
Short name T594
Test name
Test status
Simulation time 64902714 ps
CPU time 1.46 seconds
Started Sep 04 02:02:05 AM UTC 24
Finished Sep 04 02:02:08 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273796949 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.1273796949
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.3521414720
Short name T586
Test name
Test status
Simulation time 84190482 ps
CPU time 1.68 seconds
Started Sep 04 02:02:01 AM UTC 24
Finished Sep 04 02:02:04 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521414720 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3521414720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.4154670494
Short name T602
Test name
Test status
Simulation time 807533515 ps
CPU time 8.85 seconds
Started Sep 04 02:02:01 AM UTC 24
Finished Sep 04 02:02:11 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154670494 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.4154670494
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.3407090583
Short name T612
Test name
Test status
Simulation time 2426212856 ps
CPU time 13.03 seconds
Started Sep 04 02:02:01 AM UTC 24
Finished Sep 04 02:02:15 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407090583 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.3407090583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.2200904706
Short name T589
Test name
Test status
Simulation time 28824370 ps
CPU time 1.2 seconds
Started Sep 04 02:02:03 AM UTC 24
Finished Sep 04 02:02:06 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200904706 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.2200904706
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.3253544630
Short name T591
Test name
Test status
Simulation time 57805772 ps
CPU time 1.4 seconds
Started Sep 04 02:02:04 AM UTC 24
Finished Sep 04 02:02:06 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253544630
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.3253544630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.146292854
Short name T590
Test name
Test status
Simulation time 36501415 ps
CPU time 1.21 seconds
Started Sep 04 02:02:03 AM UTC 24
Finished Sep 04 02:02:06 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146292854 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.146292854
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.2600738510
Short name T584
Test name
Test status
Simulation time 44363167 ps
CPU time 1.3 seconds
Started Sep 04 02:02:01 AM UTC 24
Finished Sep 04 02:02:04 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600738510 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2600738510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.3168702524
Short name T615
Test name
Test status
Simulation time 1341847376 ps
CPU time 10.86 seconds
Started Sep 04 02:02:05 AM UTC 24
Finished Sep 04 02:02:17 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168702524 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.3168702524
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.4211821684
Short name T583
Test name
Test status
Simulation time 41809469 ps
CPU time 1.32 seconds
Started Sep 04 02:02:00 AM UTC 24
Finished Sep 04 02:02:02 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211821684 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.4211821684
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.3864630500
Short name T727
Test name
Test status
Simulation time 9884654460 ps
CPU time 41.6 seconds
Started Sep 04 02:02:05 AM UTC 24
Finished Sep 04 02:02:48 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864630500 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.3864630500
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.1742237440
Short name T833
Test name
Test status
Simulation time 7077737373 ps
CPU time 67.41 seconds
Started Sep 04 02:02:05 AM UTC 24
Finished Sep 04 02:03:14 AM UTC 24
Peak memory 220288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742237440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1742237440
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.1739386672
Short name T585
Test name
Test status
Simulation time 22977285 ps
CPU time 1.29 seconds
Started Sep 04 02:02:01 AM UTC 24
Finished Sep 04 02:02:04 AM UTC 24
Peak memory 210028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739386672 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1739386672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.753162251
Short name T614
Test name
Test status
Simulation time 67829400 ps
CPU time 1.43 seconds
Started Sep 04 02:02:13 AM UTC 24
Finished Sep 04 02:02:16 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753162251 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.753162251
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3260591393
Short name T607
Test name
Test status
Simulation time 37344192 ps
CPU time 1.32 seconds
Started Sep 04 02:02:11 AM UTC 24
Finished Sep 04 02:02:13 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260591393 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.3260591393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.3990887401
Short name T599
Test name
Test status
Simulation time 17464972 ps
CPU time 1.02 seconds
Started Sep 04 02:02:08 AM UTC 24
Finished Sep 04 02:02:10 AM UTC 24
Peak memory 209932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990887401 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3990887401
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.3392343368
Short name T608
Test name
Test status
Simulation time 27796555 ps
CPU time 1.18 seconds
Started Sep 04 02:02:12 AM UTC 24
Finished Sep 04 02:02:14 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392343368 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.3392343368
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.3128343737
Short name T598
Test name
Test status
Simulation time 156182718 ps
CPU time 2.13 seconds
Started Sep 04 02:02:07 AM UTC 24
Finished Sep 04 02:02:10 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128343737 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3128343737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.398003511
Short name T609
Test name
Test status
Simulation time 947320764 ps
CPU time 6.17 seconds
Started Sep 04 02:02:07 AM UTC 24
Finished Sep 04 02:02:14 AM UTC 24
Peak memory 210344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398003511 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.398003511
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.1333240938
Short name T618
Test name
Test status
Simulation time 1102512944 ps
CPU time 9.08 seconds
Started Sep 04 02:02:07 AM UTC 24
Finished Sep 04 02:02:17 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333240938 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.1333240938
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.32931896
Short name T604
Test name
Test status
Simulation time 40455629 ps
CPU time 1.19 seconds
Started Sep 04 02:02:09 AM UTC 24
Finished Sep 04 02:02:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32931896 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.32931896
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.89408047
Short name T606
Test name
Test status
Simulation time 159271360 ps
CPU time 1.89 seconds
Started Sep 04 02:02:10 AM UTC 24
Finished Sep 04 02:02:13 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89408047 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.89408047
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3089448131
Short name T603
Test name
Test status
Simulation time 15871018 ps
CPU time 1.12 seconds
Started Sep 04 02:02:10 AM UTC 24
Finished Sep 04 02:02:12 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089448131
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.3089448131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.752432811
Short name T600
Test name
Test status
Simulation time 15498631 ps
CPU time 1.1 seconds
Started Sep 04 02:02:08 AM UTC 24
Finished Sep 04 02:02:11 AM UTC 24
Peak memory 209924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752432811 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.752432811
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.1606100431
Short name T620
Test name
Test status
Simulation time 1197826284 ps
CPU time 4.83 seconds
Started Sep 04 02:02:12 AM UTC 24
Finished Sep 04 02:02:18 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606100431 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1606100431
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.1355307364
Short name T597
Test name
Test status
Simulation time 85286015 ps
CPU time 1.65 seconds
Started Sep 04 02:02:06 AM UTC 24
Finished Sep 04 02:02:09 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1355307364 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1355307364
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.4107634136
Short name T639
Test name
Test status
Simulation time 1467144438 ps
CPU time 11.79 seconds
Started Sep 04 02:02:12 AM UTC 24
Finished Sep 04 02:02:25 AM UTC 24
Peak memory 210548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107634136 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.4107634136
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.2274846833
Short name T695
Test name
Test status
Simulation time 2164350181 ps
CPU time 26.07 seconds
Started Sep 04 02:02:12 AM UTC 24
Finished Sep 04 02:02:39 AM UTC 24
Peak memory 227504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274846833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2274846833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.1112947970
Short name T601
Test name
Test status
Simulation time 37989106 ps
CPU time 1.22 seconds
Started Sep 04 02:02:08 AM UTC 24
Finished Sep 04 02:02:11 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112947970 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1112947970
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.2746250103
Short name T628
Test name
Test status
Simulation time 39554243 ps
CPU time 1.15 seconds
Started Sep 04 02:02:18 AM UTC 24
Finished Sep 04 02:02:20 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746250103 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.2746250103
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.2559911592
Short name T622
Test name
Test status
Simulation time 23504138 ps
CPU time 1.14 seconds
Started Sep 04 02:02:17 AM UTC 24
Finished Sep 04 02:02:19 AM UTC 24
Peak memory 210540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559911592 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.2559911592
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.1647224584
Short name T619
Test name
Test status
Simulation time 46443503 ps
CPU time 1.01 seconds
Started Sep 04 02:02:15 AM UTC 24
Finished Sep 04 02:02:17 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647224584 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1647224584
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.2554947847
Short name T629
Test name
Test status
Simulation time 216515196 ps
CPU time 2.4 seconds
Started Sep 04 02:02:18 AM UTC 24
Finished Sep 04 02:02:22 AM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554947847 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.2554947847
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.3718791085
Short name T613
Test name
Test status
Simulation time 24835438 ps
CPU time 1.31 seconds
Started Sep 04 02:02:13 AM UTC 24
Finished Sep 04 02:02:16 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718791085 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3718791085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.4050436347
Short name T646
Test name
Test status
Simulation time 2128230856 ps
CPU time 13.26 seconds
Started Sep 04 02:02:13 AM UTC 24
Finished Sep 04 02:02:28 AM UTC 24
Peak memory 210836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050436347 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.4050436347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.1450367025
Short name T623
Test name
Test status
Simulation time 977610954 ps
CPU time 3.63 seconds
Started Sep 04 02:02:14 AM UTC 24
Finished Sep 04 02:02:19 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450367025 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.1450367025
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.571061833
Short name T621
Test name
Test status
Simulation time 21461443 ps
CPU time 1.11 seconds
Started Sep 04 02:02:17 AM UTC 24
Finished Sep 04 02:02:19 AM UTC 24
Peak memory 208572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571061833 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.571061833
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.965071476
Short name T624
Test name
Test status
Simulation time 29590304 ps
CPU time 1.38 seconds
Started Sep 04 02:02:17 AM UTC 24
Finished Sep 04 02:02:19 AM UTC 24
Peak memory 210048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965071476 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.965071476
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.2300450774
Short name T625
Test name
Test status
Simulation time 158522196 ps
CPU time 1.88 seconds
Started Sep 04 02:02:17 AM UTC 24
Finished Sep 04 02:02:20 AM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300450774
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.2300450774
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.496183149
Short name T617
Test name
Test status
Simulation time 22836919 ps
CPU time 1.06 seconds
Started Sep 04 02:02:15 AM UTC 24
Finished Sep 04 02:02:17 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496183149 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.496183149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.226190537
Short name T634
Test name
Test status
Simulation time 823277865 ps
CPU time 4.17 seconds
Started Sep 04 02:02:18 AM UTC 24
Finished Sep 04 02:02:23 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226190537 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.226190537
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.1635204739
Short name T611
Test name
Test status
Simulation time 18186936 ps
CPU time 1.2 seconds
Started Sep 04 02:02:13 AM UTC 24
Finished Sep 04 02:02:15 AM UTC 24
Peak memory 209784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635204739 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1635204739
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.2891291916
Short name T722
Test name
Test status
Simulation time 3263743078 ps
CPU time 27.13 seconds
Started Sep 04 02:02:18 AM UTC 24
Finished Sep 04 02:02:47 AM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891291916 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.2891291916
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.1106179201
Short name T851
Test name
Test status
Simulation time 11436502472 ps
CPU time 82.18 seconds
Started Sep 04 02:02:18 AM UTC 24
Finished Sep 04 02:03:42 AM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106179201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.1106179201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.444181307
Short name T616
Test name
Test status
Simulation time 16806561 ps
CPU time 0.91 seconds
Started Sep 04 02:02:15 AM UTC 24
Finished Sep 04 02:02:17 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444181307 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.444181307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.519919636
Short name T642
Test name
Test status
Simulation time 20336361 ps
CPU time 1.05 seconds
Started Sep 04 02:02:24 AM UTC 24
Finished Sep 04 02:02:26 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519919636 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.519919636
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.4042585153
Short name T640
Test name
Test status
Simulation time 22526716 ps
CPU time 1.11 seconds
Started Sep 04 02:02:23 AM UTC 24
Finished Sep 04 02:02:25 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042585153 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.4042585153
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.577567384
Short name T632
Test name
Test status
Simulation time 16113312 ps
CPU time 1.05 seconds
Started Sep 04 02:02:21 AM UTC 24
Finished Sep 04 02:02:23 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577567384 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.577567384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.466906359
Short name T641
Test name
Test status
Simulation time 47365233 ps
CPU time 1.29 seconds
Started Sep 04 02:02:23 AM UTC 24
Finished Sep 04 02:02:25 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466906359 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.466906359
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.3895551068
Short name T630
Test name
Test status
Simulation time 48871408 ps
CPU time 1.38 seconds
Started Sep 04 02:02:19 AM UTC 24
Finished Sep 04 02:02:22 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895551068 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3895551068
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.1203613720
Short name T666
Test name
Test status
Simulation time 2231878908 ps
CPU time 11.23 seconds
Started Sep 04 02:02:20 AM UTC 24
Finished Sep 04 02:02:33 AM UTC 24
Peak memory 210904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203613720 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1203613720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.569884568
Short name T658
Test name
Test status
Simulation time 1589720191 ps
CPU time 9.44 seconds
Started Sep 04 02:02:20 AM UTC 24
Finished Sep 04 02:02:31 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569884568 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.569884568
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.3449791920
Short name T638
Test name
Test status
Simulation time 62171842 ps
CPU time 1.48 seconds
Started Sep 04 02:02:22 AM UTC 24
Finished Sep 04 02:02:24 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449791920 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.3449791920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.703460557
Short name T637
Test name
Test status
Simulation time 33276179 ps
CPU time 1.28 seconds
Started Sep 04 02:02:22 AM UTC 24
Finished Sep 04 02:02:24 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703460557 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.703460557
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2897979124
Short name T636
Test name
Test status
Simulation time 12796375 ps
CPU time 1.05 seconds
Started Sep 04 02:02:22 AM UTC 24
Finished Sep 04 02:02:24 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897979124
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.2897979124
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.4221145052
Short name T631
Test name
Test status
Simulation time 15004404 ps
CPU time 1.14 seconds
Started Sep 04 02:02:20 AM UTC 24
Finished Sep 04 02:02:23 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221145052 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.4221145052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.2019225024
Short name T647
Test name
Test status
Simulation time 377361127 ps
CPU time 2.7 seconds
Started Sep 04 02:02:24 AM UTC 24
Finished Sep 04 02:02:28 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019225024 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.2019225024
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.2253278768
Short name T627
Test name
Test status
Simulation time 19959072 ps
CPU time 0.99 seconds
Started Sep 04 02:02:18 AM UTC 24
Finished Sep 04 02:02:20 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253278768 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2253278768
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.285298499
Short name T688
Test name
Test status
Simulation time 1506480279 ps
CPU time 12.51 seconds
Started Sep 04 02:02:24 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285298499 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.285298499
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.733807655
Short name T843
Test name
Test status
Simulation time 8725867771 ps
CPU time 59.19 seconds
Started Sep 04 02:02:24 AM UTC 24
Finished Sep 04 02:03:25 AM UTC 24
Peak memory 220336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733807655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.733807655
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.4182648726
Short name T633
Test name
Test status
Simulation time 35702521 ps
CPU time 1.5 seconds
Started Sep 04 02:02:21 AM UTC 24
Finished Sep 04 02:02:23 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182648726 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.4182648726
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.1233483634
Short name T660
Test name
Test status
Simulation time 50445921 ps
CPU time 1.25 seconds
Started Sep 04 02:02:29 AM UTC 24
Finished Sep 04 02:02:31 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233483634 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.1233483634
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1765687199
Short name T659
Test name
Test status
Simulation time 43589837 ps
CPU time 1.4 seconds
Started Sep 04 02:02:29 AM UTC 24
Finished Sep 04 02:02:31 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765687199 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.1765687199
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.3382082752
Short name T650
Test name
Test status
Simulation time 16695769 ps
CPU time 1.07 seconds
Started Sep 04 02:02:27 AM UTC 24
Finished Sep 04 02:02:29 AM UTC 24
Peak memory 208996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382082752 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3382082752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.3208477460
Short name T657
Test name
Test status
Simulation time 34177950 ps
CPU time 1.03 seconds
Started Sep 04 02:02:29 AM UTC 24
Finished Sep 04 02:02:31 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208477460 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.3208477460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.3854340123
Short name T648
Test name
Test status
Simulation time 125927052 ps
CPU time 1.68 seconds
Started Sep 04 02:02:25 AM UTC 24
Finished Sep 04 02:02:28 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854340123 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3854340123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.3198497913
Short name T649
Test name
Test status
Simulation time 232814290 ps
CPU time 2.25 seconds
Started Sep 04 02:02:25 AM UTC 24
Finished Sep 04 02:02:29 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198497913 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.3198497913
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.272111491
Short name T656
Test name
Test status
Simulation time 375008343 ps
CPU time 3.64 seconds
Started Sep 04 02:02:25 AM UTC 24
Finished Sep 04 02:02:30 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272111491 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.272111491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.1249290631
Short name T651
Test name
Test status
Simulation time 72154977 ps
CPU time 1.19 seconds
Started Sep 04 02:02:27 AM UTC 24
Finished Sep 04 02:02:29 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249290631 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.1249290631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1253104398
Short name T654
Test name
Test status
Simulation time 29645784 ps
CPU time 0.97 seconds
Started Sep 04 02:02:28 AM UTC 24
Finished Sep 04 02:02:30 AM UTC 24
Peak memory 209924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253104398
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.1253104398
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.287850161
Short name T655
Test name
Test status
Simulation time 81392345 ps
CPU time 1.4 seconds
Started Sep 04 02:02:28 AM UTC 24
Finished Sep 04 02:02:30 AM UTC 24
Peak memory 208884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287850161 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.287850161
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.2365522082
Short name T645
Test name
Test status
Simulation time 12040869 ps
CPU time 1.08 seconds
Started Sep 04 02:02:26 AM UTC 24
Finished Sep 04 02:02:28 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365522082 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2365522082
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.2307810448
Short name T665
Test name
Test status
Simulation time 379758327 ps
CPU time 2.43 seconds
Started Sep 04 02:02:29 AM UTC 24
Finished Sep 04 02:02:32 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307810448 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2307810448
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.1238912920
Short name T643
Test name
Test status
Simulation time 18665888 ps
CPU time 1.18 seconds
Started Sep 04 02:02:24 AM UTC 24
Finished Sep 04 02:02:26 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238912920 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1238912920
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.1099068999
Short name T711
Test name
Test status
Simulation time 2605791604 ps
CPU time 13.61 seconds
Started Sep 04 02:02:29 AM UTC 24
Finished Sep 04 02:02:44 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099068999 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.1099068999
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.334202259
Short name T765
Test name
Test status
Simulation time 2494890690 ps
CPU time 27.65 seconds
Started Sep 04 02:02:29 AM UTC 24
Finished Sep 04 02:02:58 AM UTC 24
Peak memory 220520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334202259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.334202259
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.85647446
Short name T653
Test name
Test status
Simulation time 55467284 ps
CPU time 1.55 seconds
Started Sep 04 02:02:27 AM UTC 24
Finished Sep 04 02:02:29 AM UTC 24
Peak memory 209728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85647446 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.85647446
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.587436175
Short name T677
Test name
Test status
Simulation time 39791479 ps
CPU time 1.17 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:02:35 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587436175 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.587436175
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.877792491
Short name T675
Test name
Test status
Simulation time 36303304 ps
CPU time 1.21 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:02:35 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=877792491 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.877792491
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.1754572779
Short name T669
Test name
Test status
Simulation time 15558388 ps
CPU time 1.12 seconds
Started Sep 04 02:02:32 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754572779 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1754572779
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.99652311
Short name T681
Test name
Test status
Simulation time 227426492 ps
CPU time 2.5 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:02:36 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99652311 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.99652311
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.3611240100
Short name T667
Test name
Test status
Simulation time 133143087 ps
CPU time 1.88 seconds
Started Sep 04 02:02:30 AM UTC 24
Finished Sep 04 02:02:33 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611240100 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3611240100
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.2661650516
Short name T672
Test name
Test status
Simulation time 274107323 ps
CPU time 2.63 seconds
Started Sep 04 02:02:30 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661650516 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2661650516
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.1258001624
Short name T715
Test name
Test status
Simulation time 2183856138 ps
CPU time 12.93 seconds
Started Sep 04 02:02:30 AM UTC 24
Finished Sep 04 02:02:44 AM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258001624 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.1258001624
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.733250093
Short name T671
Test name
Test status
Simulation time 24829392 ps
CPU time 1.3 seconds
Started Sep 04 02:02:32 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733250093 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.733250093
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1033725709
Short name T668
Test name
Test status
Simulation time 31143328 ps
CPU time 0.81 seconds
Started Sep 04 02:02:32 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033725709
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.1033725709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.437166225
Short name T673
Test name
Test status
Simulation time 25562478 ps
CPU time 1.3 seconds
Started Sep 04 02:02:32 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437166225 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.437166225
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.3260115211
Short name T664
Test name
Test status
Simulation time 16553338 ps
CPU time 1.03 seconds
Started Sep 04 02:02:30 AM UTC 24
Finished Sep 04 02:02:32 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260115211 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3260115211
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.3865662275
Short name T696
Test name
Test status
Simulation time 945266634 ps
CPU time 5.89 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:02:40 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865662275 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.3865662275
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.652434922
Short name T662
Test name
Test status
Simulation time 47540765 ps
CPU time 1.1 seconds
Started Sep 04 02:02:30 AM UTC 24
Finished Sep 04 02:02:32 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652434922 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.652434922
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.2965607485
Short name T846
Test name
Test status
Simulation time 7234485980 ps
CPU time 55.87 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:03:30 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965607485 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.2965607485
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.2967356278
Short name T854
Test name
Test status
Simulation time 18506795490 ps
CPU time 115.42 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:04:31 AM UTC 24
Peak memory 220296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967356278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.2967356278
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.1070181062
Short name T670
Test name
Test status
Simulation time 53234670 ps
CPU time 1.28 seconds
Started Sep 04 02:02:32 AM UTC 24
Finished Sep 04 02:02:34 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070181062 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1070181062
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.3785157730
Short name T213
Test name
Test status
Simulation time 51131950 ps
CPU time 1.28 seconds
Started Sep 04 01:59:16 AM UTC 24
Finished Sep 04 01:59:18 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785157730 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.3785157730
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.2160905454
Short name T114
Test name
Test status
Simulation time 46902115 ps
CPU time 1.32 seconds
Started Sep 04 01:59:14 AM UTC 24
Finished Sep 04 01:59:16 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160905454 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.2160905454
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.3984220085
Short name T180
Test name
Test status
Simulation time 31258999 ps
CPU time 1.13 seconds
Started Sep 04 01:59:12 AM UTC 24
Finished Sep 04 01:59:14 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984220085 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3984220085
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.1620365725
Short name T212
Test name
Test status
Simulation time 25362219 ps
CPU time 1.2 seconds
Started Sep 04 01:59:14 AM UTC 24
Finished Sep 04 01:59:16 AM UTC 24
Peak memory 209060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620365725 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.1620365725
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.1176941224
Short name T179
Test name
Test status
Simulation time 14982829 ps
CPU time 1.09 seconds
Started Sep 04 01:59:12 AM UTC 24
Finished Sep 04 01:59:14 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176941224 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1176941224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.1189781200
Short name T14
Test name
Test status
Simulation time 2372222323 ps
CPU time 11.12 seconds
Started Sep 04 01:59:12 AM UTC 24
Finished Sep 04 01:59:24 AM UTC 24
Peak memory 210680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189781200 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1189781200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.3130560403
Short name T102
Test name
Test status
Simulation time 1455737767 ps
CPU time 15.09 seconds
Started Sep 04 01:59:12 AM UTC 24
Finished Sep 04 01:59:28 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130560403 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.3130560403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.2305456513
Short name T184
Test name
Test status
Simulation time 21547845 ps
CPU time 1.22 seconds
Started Sep 04 01:59:13 AM UTC 24
Finished Sep 04 01:59:16 AM UTC 24
Peak memory 208892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305456513 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.2305456513
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.4257179810
Short name T211
Test name
Test status
Simulation time 60268059 ps
CPU time 1.25 seconds
Started Sep 04 01:59:14 AM UTC 24
Finished Sep 04 01:59:16 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257179810
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.4257179810
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.4222203170
Short name T183
Test name
Test status
Simulation time 16229370 ps
CPU time 1.1 seconds
Started Sep 04 01:59:13 AM UTC 24
Finished Sep 04 01:59:15 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222203170
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.4222203170
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.2053051472
Short name T181
Test name
Test status
Simulation time 33077655 ps
CPU time 1.22 seconds
Started Sep 04 01:59:12 AM UTC 24
Finished Sep 04 01:59:14 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053051472 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.2053051472
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.1628759583
Short name T73
Test name
Test status
Simulation time 408003479 ps
CPU time 3.34 seconds
Started Sep 04 01:59:15 AM UTC 24
Finished Sep 04 01:59:19 AM UTC 24
Peak memory 242876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628759583 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.1628759583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.1899815048
Short name T49
Test name
Test status
Simulation time 47613833 ps
CPU time 1.25 seconds
Started Sep 04 01:59:11 AM UTC 24
Finished Sep 04 01:59:13 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899815048 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1899815048
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.987320016
Short name T15
Test name
Test status
Simulation time 2108747863 ps
CPU time 12.4 seconds
Started Sep 04 01:59:16 AM UTC 24
Finished Sep 04 01:59:29 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987320016 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.987320016
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.3583229536
Short name T88
Test name
Test status
Simulation time 3497527434 ps
CPU time 64.9 seconds
Started Sep 04 01:59:15 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 220268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583229536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.3583229536
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.4181406630
Short name T182
Test name
Test status
Simulation time 127323316 ps
CPU time 1.92 seconds
Started Sep 04 01:59:12 AM UTC 24
Finished Sep 04 01:59:15 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181406630 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.4181406630
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.3166233675
Short name T693
Test name
Test status
Simulation time 29530223 ps
CPU time 1.19 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:02:39 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166233675 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.3166233675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1420219149
Short name T686
Test name
Test status
Simulation time 13524959 ps
CPU time 0.81 seconds
Started Sep 04 02:02:36 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 210224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420219149 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.1420219149
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.1067638560
Short name T682
Test name
Test status
Simulation time 41854955 ps
CPU time 1.04 seconds
Started Sep 04 02:02:34 AM UTC 24
Finished Sep 04 02:02:36 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067638560 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1067638560
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.968631789
Short name T690
Test name
Test status
Simulation time 52953893 ps
CPU time 1.21 seconds
Started Sep 04 02:02:36 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968631789 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.968631789
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.1572882319
Short name T683
Test name
Test status
Simulation time 68959287 ps
CPU time 1.4 seconds
Started Sep 04 02:02:34 AM UTC 24
Finished Sep 04 02:02:37 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572882319 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1572882319
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.1277442265
Short name T742
Test name
Test status
Simulation time 2237730874 ps
CPU time 17.26 seconds
Started Sep 04 02:02:34 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277442265 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1277442265
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.2100402105
Short name T684
Test name
Test status
Simulation time 396839283 ps
CPU time 2.22 seconds
Started Sep 04 02:02:34 AM UTC 24
Finished Sep 04 02:02:37 AM UTC 24
Peak memory 210652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100402105 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.2100402105
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.3915506171
Short name T687
Test name
Test status
Simulation time 33705696 ps
CPU time 1.12 seconds
Started Sep 04 02:02:35 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915506171 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3915506171
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.331595882
Short name T685
Test name
Test status
Simulation time 19380497 ps
CPU time 0.82 seconds
Started Sep 04 02:02:36 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331595882 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.331595882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2194805405
Short name T691
Test name
Test status
Simulation time 87378073 ps
CPU time 1.56 seconds
Started Sep 04 02:02:35 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194805405
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.2194805405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.3171537413
Short name T679
Test name
Test status
Simulation time 17312496 ps
CPU time 1.07 seconds
Started Sep 04 02:02:34 AM UTC 24
Finished Sep 04 02:02:36 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171537413 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.3171537413
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.3925450542
Short name T718
Test name
Test status
Simulation time 699615195 ps
CPU time 7.57 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:02:45 AM UTC 24
Peak memory 210640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925450542 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3925450542
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.2739561623
Short name T676
Test name
Test status
Simulation time 18352141 ps
CPU time 1.1 seconds
Started Sep 04 02:02:33 AM UTC 24
Finished Sep 04 02:02:35 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2739561623 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2739561623
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.460730506
Short name T700
Test name
Test status
Simulation time 386171227 ps
CPU time 2.67 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:02:40 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460730506 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.460730506
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.2112878722
Short name T842
Test name
Test status
Simulation time 2832919164 ps
CPU time 46.69 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:03:25 AM UTC 24
Peak memory 220332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112878722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.2112878722
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.2761900330
Short name T689
Test name
Test status
Simulation time 292957009 ps
CPU time 2.61 seconds
Started Sep 04 02:02:34 AM UTC 24
Finished Sep 04 02:02:38 AM UTC 24
Peak memory 210288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761900330 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2761900330
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.847721989
Short name T706
Test name
Test status
Simulation time 12998104 ps
CPU time 1.07 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:43 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847721989 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.847721989
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2105055882
Short name T703
Test name
Test status
Simulation time 22371292 ps
CPU time 1.19 seconds
Started Sep 04 02:02:40 AM UTC 24
Finished Sep 04 02:02:42 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105055882 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.2105055882
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.3063370409
Short name T699
Test name
Test status
Simulation time 49055215 ps
CPU time 1.15 seconds
Started Sep 04 02:02:38 AM UTC 24
Finished Sep 04 02:02:40 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063370409 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3063370409
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.3740134366
Short name T704
Test name
Test status
Simulation time 21142793 ps
CPU time 1.23 seconds
Started Sep 04 02:02:40 AM UTC 24
Finished Sep 04 02:02:42 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740134366 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.3740134366
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.568229464
Short name T692
Test name
Test status
Simulation time 78135002 ps
CPU time 1.09 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:02:39 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568229464 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.568229464
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.1752659430
Short name T767
Test name
Test status
Simulation time 2120858031 ps
CPU time 20.23 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:02:58 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752659430 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1752659430
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.256204290
Short name T741
Test name
Test status
Simulation time 1696493595 ps
CPU time 12.67 seconds
Started Sep 04 02:02:38 AM UTC 24
Finished Sep 04 02:02:52 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256204290 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.256204290
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.1641883909
Short name T698
Test name
Test status
Simulation time 21275242 ps
CPU time 1.05 seconds
Started Sep 04 02:02:38 AM UTC 24
Finished Sep 04 02:02:40 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641883909 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.1641883909
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3758471202
Short name T702
Test name
Test status
Simulation time 17329535 ps
CPU time 1.14 seconds
Started Sep 04 02:02:40 AM UTC 24
Finished Sep 04 02:02:42 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758471202
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.3758471202
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2305872531
Short name T705
Test name
Test status
Simulation time 177036365 ps
CPU time 2.06 seconds
Started Sep 04 02:02:39 AM UTC 24
Finished Sep 04 02:02:43 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305872531
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.2305872531
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.2624295844
Short name T697
Test name
Test status
Simulation time 41809311 ps
CPU time 0.96 seconds
Started Sep 04 02:02:38 AM UTC 24
Finished Sep 04 02:02:40 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624295844 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2624295844
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.1553048347
Short name T733
Test name
Test status
Simulation time 1018899951 ps
CPU time 8.79 seconds
Started Sep 04 02:02:40 AM UTC 24
Finished Sep 04 02:02:49 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553048347 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1553048347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.4188338822
Short name T694
Test name
Test status
Simulation time 72172629 ps
CPU time 1.26 seconds
Started Sep 04 02:02:37 AM UTC 24
Finished Sep 04 02:02:39 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188338822 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.4188338822
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.4181658446
Short name T799
Test name
Test status
Simulation time 4773474391 ps
CPU time 24.73 seconds
Started Sep 04 02:02:40 AM UTC 24
Finished Sep 04 02:03:06 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181658446 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.4181658446
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.1741826123
Short name T758
Test name
Test status
Simulation time 981885579 ps
CPU time 15.09 seconds
Started Sep 04 02:02:40 AM UTC 24
Finished Sep 04 02:02:56 AM UTC 24
Peak memory 222120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741826123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.1741826123
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.2692893647
Short name T701
Test name
Test status
Simulation time 124852650 ps
CPU time 1.42 seconds
Started Sep 04 02:02:38 AM UTC 24
Finished Sep 04 02:02:41 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692893647 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2692893647
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.4270079176
Short name T723
Test name
Test status
Simulation time 15254908 ps
CPU time 1.12 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:02:47 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270079176 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.4270079176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1590456947
Short name T719
Test name
Test status
Simulation time 44783988 ps
CPU time 1.21 seconds
Started Sep 04 02:02:44 AM UTC 24
Finished Sep 04 02:02:46 AM UTC 24
Peak memory 210224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590456947 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.1590456947
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.2875273984
Short name T709
Test name
Test status
Simulation time 41525517 ps
CPU time 1.17 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:43 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875273984 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2875273984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.488378685
Short name T720
Test name
Test status
Simulation time 31465215 ps
CPU time 1.3 seconds
Started Sep 04 02:02:44 AM UTC 24
Finished Sep 04 02:02:46 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488378685 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.488378685
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.2886257892
Short name T708
Test name
Test status
Simulation time 41812834 ps
CPU time 1.12 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:43 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886257892 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2886257892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.783601460
Short name T800
Test name
Test status
Simulation time 2363021929 ps
CPU time 23.74 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:03:06 AM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783601460 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.783601460
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.1658830139
Short name T713
Test name
Test status
Simulation time 212626429 ps
CPU time 2.13 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:44 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658830139 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.1658830139
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.98985163
Short name T717
Test name
Test status
Simulation time 128071417 ps
CPU time 1.91 seconds
Started Sep 04 02:02:42 AM UTC 24
Finished Sep 04 02:02:45 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98985163 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.98985163
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.2337049510
Short name T716
Test name
Test status
Simulation time 70050449 ps
CPU time 1.31 seconds
Started Sep 04 02:02:43 AM UTC 24
Finished Sep 04 02:02:45 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337049510
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.2337049510
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.35817099
Short name T714
Test name
Test status
Simulation time 15989803 ps
CPU time 0.92 seconds
Started Sep 04 02:02:42 AM UTC 24
Finished Sep 04 02:02:44 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35817099 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.35817099
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.177369967
Short name T707
Test name
Test status
Simulation time 22540913 ps
CPU time 1.04 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:43 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177369967 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.177369967
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.2020092590
Short name T735
Test name
Test status
Simulation time 857284191 ps
CPU time 4.97 seconds
Started Sep 04 02:02:44 AM UTC 24
Finished Sep 04 02:02:50 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020092590 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2020092590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.3371127405
Short name T710
Test name
Test status
Simulation time 97467169 ps
CPU time 1.66 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:44 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371127405 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3371127405
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.212855150
Short name T774
Test name
Test status
Simulation time 1575202234 ps
CPU time 14.24 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:03:00 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212855150 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.212855150
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.1013623819
Short name T808
Test name
Test status
Simulation time 1708308493 ps
CPU time 22.74 seconds
Started Sep 04 02:02:44 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 220396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013623819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.1013623819
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.3168057607
Short name T712
Test name
Test status
Simulation time 178574204 ps
CPU time 1.86 seconds
Started Sep 04 02:02:41 AM UTC 24
Finished Sep 04 02:02:44 AM UTC 24
Peak memory 208992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168057607 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3168057607
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.1272694187
Short name T739
Test name
Test status
Simulation time 26119619 ps
CPU time 1.16 seconds
Started Sep 04 02:02:49 AM UTC 24
Finished Sep 04 02:02:51 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272694187 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.1272694187
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3102563115
Short name T736
Test name
Test status
Simulation time 28194681 ps
CPU time 1.2 seconds
Started Sep 04 02:02:48 AM UTC 24
Finished Sep 04 02:02:50 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102563115 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.3102563115
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.2198125372
Short name T729
Test name
Test status
Simulation time 13107809 ps
CPU time 1.06 seconds
Started Sep 04 02:02:46 AM UTC 24
Finished Sep 04 02:02:48 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198125372 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.2198125372
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.484087381
Short name T737
Test name
Test status
Simulation time 54030617 ps
CPU time 1.17 seconds
Started Sep 04 02:02:48 AM UTC 24
Finished Sep 04 02:02:50 AM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484087381 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.484087381
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.1100937345
Short name T725
Test name
Test status
Simulation time 49001998 ps
CPU time 1.41 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:02:47 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100937345 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1100937345
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.904245326
Short name T752
Test name
Test status
Simulation time 681593254 ps
CPU time 7.41 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:02:54 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904245326 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.904245326
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.1272497250
Short name T769
Test name
Test status
Simulation time 2185491161 ps
CPU time 12.72 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:02:59 AM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272497250 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.1272497250
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.796279963
Short name T734
Test name
Test status
Simulation time 184728493 ps
CPU time 2.06 seconds
Started Sep 04 02:02:46 AM UTC 24
Finished Sep 04 02:02:50 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796279963 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.796279963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.1544862692
Short name T732
Test name
Test status
Simulation time 30457445 ps
CPU time 1.25 seconds
Started Sep 04 02:02:47 AM UTC 24
Finished Sep 04 02:02:49 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544862692
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.1544862692
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.570432336
Short name T731
Test name
Test status
Simulation time 33355017 ps
CPU time 1.3 seconds
Started Sep 04 02:02:47 AM UTC 24
Finished Sep 04 02:02:49 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570432336 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.570432336
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.3399141451
Short name T724
Test name
Test status
Simulation time 17004220 ps
CPU time 1.16 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:02:47 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399141451 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3399141451
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.2031100179
Short name T744
Test name
Test status
Simulation time 849660204 ps
CPU time 3.89 seconds
Started Sep 04 02:02:48 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031100179 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.2031100179
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.3159738481
Short name T726
Test name
Test status
Simulation time 153431699 ps
CPU time 1.92 seconds
Started Sep 04 02:02:45 AM UTC 24
Finished Sep 04 02:02:48 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159738481 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3159738481
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.3559598552
Short name T835
Test name
Test status
Simulation time 6052910235 ps
CPU time 25.38 seconds
Started Sep 04 02:02:49 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559598552 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.3559598552
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.1963986834
Short name T855
Test name
Test status
Simulation time 15800236766 ps
CPU time 99.64 seconds
Started Sep 04 02:02:49 AM UTC 24
Finished Sep 04 02:04:31 AM UTC 24
Peak memory 224584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963986834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1963986834
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.1403467120
Short name T730
Test name
Test status
Simulation time 54976340 ps
CPU time 1.38 seconds
Started Sep 04 02:02:46 AM UTC 24
Finished Sep 04 02:02:49 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403467120 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1403467120
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.3296313901
Short name T754
Test name
Test status
Simulation time 28974969 ps
CPU time 1.15 seconds
Started Sep 04 02:02:53 AM UTC 24
Finished Sep 04 02:02:55 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296313901 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.3296313901
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1120390857
Short name T749
Test name
Test status
Simulation time 85049430 ps
CPU time 1.2 seconds
Started Sep 04 02:02:51 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120390857 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.1120390857
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.2279728935
Short name T746
Test name
Test status
Simulation time 64794998 ps
CPU time 1.25 seconds
Started Sep 04 02:02:51 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279728935 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2279728935
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.1945662002
Short name T757
Test name
Test status
Simulation time 267096364 ps
CPU time 2.81 seconds
Started Sep 04 02:02:52 AM UTC 24
Finished Sep 04 02:02:56 AM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945662002 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.1945662002
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.955652305
Short name T740
Test name
Test status
Simulation time 57477705 ps
CPU time 1.4 seconds
Started Sep 04 02:02:49 AM UTC 24
Finished Sep 04 02:02:51 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955652305 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.955652305
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.3845173023
Short name T786
Test name
Test status
Simulation time 1282137830 ps
CPU time 12.02 seconds
Started Sep 04 02:02:50 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845173023 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3845173023
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.1945810963
Short name T751
Test name
Test status
Simulation time 154695094 ps
CPU time 1.73 seconds
Started Sep 04 02:02:50 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945810963 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.1945810963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.1861990826
Short name T743
Test name
Test status
Simulation time 14437659 ps
CPU time 1.1 seconds
Started Sep 04 02:02:51 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861990826 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.1861990826
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1912376261
Short name T748
Test name
Test status
Simulation time 21629877 ps
CPU time 1.2 seconds
Started Sep 04 02:02:51 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912376261
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.1912376261
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1926928070
Short name T745
Test name
Test status
Simulation time 30813299 ps
CPU time 1.14 seconds
Started Sep 04 02:02:51 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926928070
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.1926928070
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.3969786201
Short name T750
Test name
Test status
Simulation time 87623258 ps
CPU time 1.54 seconds
Started Sep 04 02:02:50 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969786201 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3969786201
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.187913184
Short name T770
Test name
Test status
Simulation time 957810763 ps
CPU time 6.11 seconds
Started Sep 04 02:02:52 AM UTC 24
Finished Sep 04 02:02:59 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187913184 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.187913184
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.3516732254
Short name T738
Test name
Test status
Simulation time 19672538 ps
CPU time 1.02 seconds
Started Sep 04 02:02:49 AM UTC 24
Finished Sep 04 02:02:51 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516732254 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3516732254
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.344032955
Short name T836
Test name
Test status
Simulation time 3305417482 ps
CPU time 21.38 seconds
Started Sep 04 02:02:53 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344032955 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.344032955
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.4264435849
Short name T849
Test name
Test status
Simulation time 3359110782 ps
CPU time 41.55 seconds
Started Sep 04 02:02:52 AM UTC 24
Finished Sep 04 02:03:35 AM UTC 24
Peak memory 227596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264435849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.4264435849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.3462022426
Short name T747
Test name
Test status
Simulation time 24714508 ps
CPU time 1.31 seconds
Started Sep 04 02:02:51 AM UTC 24
Finished Sep 04 02:02:53 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462022426 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3462022426
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.2032094580
Short name T771
Test name
Test status
Simulation time 14368685 ps
CPU time 1.02 seconds
Started Sep 04 02:02:57 AM UTC 24
Finished Sep 04 02:02:59 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032094580 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.2032094580
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1832535842
Short name T766
Test name
Test status
Simulation time 15617703 ps
CPU time 1.11 seconds
Started Sep 04 02:02:56 AM UTC 24
Finished Sep 04 02:02:58 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832535842 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.1832535842
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.1754520993
Short name T759
Test name
Test status
Simulation time 13100217 ps
CPU time 1.06 seconds
Started Sep 04 02:02:55 AM UTC 24
Finished Sep 04 02:02:57 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754520993 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1754520993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.3313698403
Short name T768
Test name
Test status
Simulation time 81059619 ps
CPU time 1.57 seconds
Started Sep 04 02:02:56 AM UTC 24
Finished Sep 04 02:02:58 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313698403 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.3313698403
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.2078725912
Short name T755
Test name
Test status
Simulation time 24549384 ps
CPU time 1.14 seconds
Started Sep 04 02:02:53 AM UTC 24
Finished Sep 04 02:02:55 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078725912 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2078725912
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.3609880590
Short name T778
Test name
Test status
Simulation time 1030754179 ps
CPU time 6.83 seconds
Started Sep 04 02:02:53 AM UTC 24
Finished Sep 04 02:03:01 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609880590 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3609880590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.2722288719
Short name T790
Test name
Test status
Simulation time 1780655209 ps
CPU time 8.32 seconds
Started Sep 04 02:02:54 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722288719 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.2722288719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.2024503308
Short name T762
Test name
Test status
Simulation time 30766680 ps
CPU time 1.48 seconds
Started Sep 04 02:02:55 AM UTC 24
Finished Sep 04 02:02:57 AM UTC 24
Peak memory 209004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024503308 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.2024503308
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3558007583
Short name T764
Test name
Test status
Simulation time 45356056 ps
CPU time 1.42 seconds
Started Sep 04 02:02:55 AM UTC 24
Finished Sep 04 02:02:57 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558007583
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.3558007583
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3114543374
Short name T761
Test name
Test status
Simulation time 24096189 ps
CPU time 1.33 seconds
Started Sep 04 02:02:55 AM UTC 24
Finished Sep 04 02:02:57 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114543374
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.3114543374
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.2372536498
Short name T763
Test name
Test status
Simulation time 138793027 ps
CPU time 1.73 seconds
Started Sep 04 02:02:54 AM UTC 24
Finished Sep 04 02:02:57 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372536498 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2372536498
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.4161378107
Short name T779
Test name
Test status
Simulation time 813637016 ps
CPU time 4.72 seconds
Started Sep 04 02:02:56 AM UTC 24
Finished Sep 04 02:03:02 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161378107 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.4161378107
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.3447947881
Short name T756
Test name
Test status
Simulation time 38103037 ps
CPU time 1.37 seconds
Started Sep 04 02:02:53 AM UTC 24
Finished Sep 04 02:02:55 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447947881 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3447947881
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.1942086455
Short name T847
Test name
Test status
Simulation time 5427118400 ps
CPU time 32.58 seconds
Started Sep 04 02:02:57 AM UTC 24
Finished Sep 04 02:03:31 AM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942086455 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.1942086455
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.3161148131
Short name T848
Test name
Test status
Simulation time 2061059740 ps
CPU time 37.04 seconds
Started Sep 04 02:02:56 AM UTC 24
Finished Sep 04 02:03:34 AM UTC 24
Peak memory 220168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161148131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3161148131
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.3762748307
Short name T760
Test name
Test status
Simulation time 18728194 ps
CPU time 1.17 seconds
Started Sep 04 02:02:55 AM UTC 24
Finished Sep 04 02:02:57 AM UTC 24
Peak memory 208876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762748307 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3762748307
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.3218569963
Short name T785
Test name
Test status
Simulation time 15102406 ps
CPU time 1.14 seconds
Started Sep 04 02:03:01 AM UTC 24
Finished Sep 04 02:03:03 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218569963 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.3218569963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2671160675
Short name T782
Test name
Test status
Simulation time 15552893 ps
CPU time 1.16 seconds
Started Sep 04 02:03:00 AM UTC 24
Finished Sep 04 02:03:02 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671160675 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.2671160675
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.3501491695
Short name T776
Test name
Test status
Simulation time 40582011 ps
CPU time 1.04 seconds
Started Sep 04 02:02:59 AM UTC 24
Finished Sep 04 02:03:01 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3501491695 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3501491695
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.2852712013
Short name T783
Test name
Test status
Simulation time 53816539 ps
CPU time 1.25 seconds
Started Sep 04 02:03:00 AM UTC 24
Finished Sep 04 02:03:02 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852712013 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.2852712013
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.1758493705
Short name T772
Test name
Test status
Simulation time 25227122 ps
CPU time 1.27 seconds
Started Sep 04 02:02:57 AM UTC 24
Finished Sep 04 02:03:00 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758493705 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1758493705
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.736166298
Short name T791
Test name
Test status
Simulation time 481764709 ps
CPU time 4.21 seconds
Started Sep 04 02:02:59 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736166298 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.736166298
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.275187849
Short name T784
Test name
Test status
Simulation time 542569293 ps
CPU time 3.19 seconds
Started Sep 04 02:02:59 AM UTC 24
Finished Sep 04 02:03:03 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275187849 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.275187849
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.3655964903
Short name T775
Test name
Test status
Simulation time 27467874 ps
CPU time 0.9 seconds
Started Sep 04 02:02:59 AM UTC 24
Finished Sep 04 02:03:01 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655964903 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.3655964903
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3451416064
Short name T780
Test name
Test status
Simulation time 56447381 ps
CPU time 1.03 seconds
Started Sep 04 02:03:00 AM UTC 24
Finished Sep 04 02:03:02 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451416064
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.3451416064
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2095416550
Short name T781
Test name
Test status
Simulation time 20733887 ps
CPU time 1.2 seconds
Started Sep 04 02:03:00 AM UTC 24
Finished Sep 04 02:03:02 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095416550
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.2095416550
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.1143239767
Short name T721
Test name
Test status
Simulation time 14496626 ps
CPU time 1.08 seconds
Started Sep 04 02:02:59 AM UTC 24
Finished Sep 04 02:03:01 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143239767 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1143239767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.3925924543
Short name T773
Test name
Test status
Simulation time 53220615 ps
CPU time 1.4 seconds
Started Sep 04 02:02:57 AM UTC 24
Finished Sep 04 02:03:00 AM UTC 24
Peak memory 210024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925924543 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3925924543
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1333699478
Short name T837
Test name
Test status
Simulation time 2658703061 ps
CPU time 13.83 seconds
Started Sep 04 02:03:01 AM UTC 24
Finished Sep 04 02:03:16 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333699478 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1333699478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.1582477067
Short name T853
Test name
Test status
Simulation time 16150732926 ps
CPU time 88.05 seconds
Started Sep 04 02:03:00 AM UTC 24
Finished Sep 04 02:04:30 AM UTC 24
Peak memory 220524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582477067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.1582477067
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.3116466159
Short name T777
Test name
Test status
Simulation time 90331251 ps
CPU time 1.41 seconds
Started Sep 04 02:02:59 AM UTC 24
Finished Sep 04 02:03:01 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116466159 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3116466159
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.3145334273
Short name T803
Test name
Test status
Simulation time 35008463 ps
CPU time 1.19 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:06 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145334273 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.3145334273
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3952637984
Short name T797
Test name
Test status
Simulation time 21358458 ps
CPU time 1.27 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952637984 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.3952637984
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.2702645966
Short name T796
Test name
Test status
Simulation time 49908067 ps
CPU time 1.28 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 208356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2702645966 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2702645966
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.2548153354
Short name T793
Test name
Test status
Simulation time 12318258 ps
CPU time 1.06 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548153354 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.2548153354
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.4092141926
Short name T787
Test name
Test status
Simulation time 17495304 ps
CPU time 1.14 seconds
Started Sep 04 02:03:01 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092141926 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.4092141926
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.3136889993
Short name T834
Test name
Test status
Simulation time 2614306625 ps
CPU time 12 seconds
Started Sep 04 02:03:01 AM UTC 24
Finished Sep 04 02:03:15 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136889993 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3136889993
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.413090226
Short name T832
Test name
Test status
Simulation time 2060569386 ps
CPU time 11.66 seconds
Started Sep 04 02:03:02 AM UTC 24
Finished Sep 04 02:03:14 AM UTC 24
Peak memory 210672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413090226 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.413090226
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.2473241719
Short name T794
Test name
Test status
Simulation time 24534944 ps
CPU time 1.3 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473241719 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.2473241719
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2092560588
Short name T792
Test name
Test status
Simulation time 62221227 ps
CPU time 1.04 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092560588
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.2092560588
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.247328676
Short name T798
Test name
Test status
Simulation time 81636788 ps
CPU time 1.57 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247328676 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.247328676
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.3264343384
Short name T788
Test name
Test status
Simulation time 46545843 ps
CPU time 1.07 seconds
Started Sep 04 02:03:02 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264343384 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.3264343384
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.1401080989
Short name T828
Test name
Test status
Simulation time 752529043 ps
CPU time 7.01 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:12 AM UTC 24
Peak memory 210836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401080989 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1401080989
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.2509558631
Short name T789
Test name
Test status
Simulation time 26985708 ps
CPU time 1.35 seconds
Started Sep 04 02:03:01 AM UTC 24
Finished Sep 04 02:03:04 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509558631 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2509558631
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.4206425963
Short name T856
Test name
Test status
Simulation time 10699107596 ps
CPU time 84.83 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:04:31 AM UTC 24
Peak memory 210772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206425963 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.4206425963
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.164260146
Short name T857
Test name
Test status
Simulation time 18698070824 ps
CPU time 97.55 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:04:44 AM UTC 24
Peak memory 220520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164260146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.164260146
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.1749618304
Short name T795
Test name
Test status
Simulation time 52442495 ps
CPU time 1.27 seconds
Started Sep 04 02:03:03 AM UTC 24
Finished Sep 04 02:03:05 AM UTC 24
Peak memory 209300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749618304 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1749618304
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.3295275394
Short name T816
Test name
Test status
Simulation time 34171533 ps
CPU time 1.28 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:10 AM UTC 24
Peak memory 209844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295275394 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.3295275394
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3761897645
Short name T810
Test name
Test status
Simulation time 24049082 ps
CPU time 1.25 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 210520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761897645 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.3761897645
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.4055834090
Short name T813
Test name
Test status
Simulation time 123079203 ps
CPU time 1.54 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055834090 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.4055834090
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.3038828469
Short name T812
Test name
Test status
Simulation time 44201700 ps
CPU time 1.23 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038828469 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.3038828469
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.1618128904
Short name T804
Test name
Test status
Simulation time 47083395 ps
CPU time 1.27 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:06 AM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618128904 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.1618128904
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.1681969073
Short name T805
Test name
Test status
Simulation time 356730905 ps
CPU time 2.22 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681969073 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1681969073
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.620294165
Short name T829
Test name
Test status
Simulation time 1479919385 ps
CPU time 7.08 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:13 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620294165 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.620294165
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.585969709
Short name T806
Test name
Test status
Simulation time 18825317 ps
CPU time 1.15 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585969709 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.585969709
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.436296807
Short name T811
Test name
Test status
Simulation time 39523169 ps
CPU time 1.24 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436296807 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.436296807
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1880643222
Short name T807
Test name
Test status
Simulation time 28742263 ps
CPU time 1.18 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880643222
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.1880643222
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.3023250574
Short name T801
Test name
Test status
Simulation time 21022048 ps
CPU time 0.97 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:06 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023250574 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3023250574
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.2465537052
Short name T824
Test name
Test status
Simulation time 387345902 ps
CPU time 2.81 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465537052 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2465537052
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.3593830906
Short name T802
Test name
Test status
Simulation time 27074124 ps
CPU time 1.19 seconds
Started Sep 04 02:03:04 AM UTC 24
Finished Sep 04 02:03:06 AM UTC 24
Peak memory 209932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593830906 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3593830906
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3493173736
Short name T817
Test name
Test status
Simulation time 180052042 ps
CPU time 1.65 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:10 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493173736 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3493173736
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.1647915900
Short name T850
Test name
Test status
Simulation time 2043701362 ps
CPU time 31.11 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:39 AM UTC 24
Peak memory 227164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647915900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.1647915900
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.1275637771
Short name T809
Test name
Test status
Simulation time 46133981 ps
CPU time 1.27 seconds
Started Sep 04 02:03:06 AM UTC 24
Finished Sep 04 02:03:08 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275637771 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.1275637771
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.2266802555
Short name T831
Test name
Test status
Simulation time 18442364 ps
CPU time 1.13 seconds
Started Sep 04 02:03:11 AM UTC 24
Finished Sep 04 02:03:13 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266802555 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.2266802555
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.184880157
Short name T825
Test name
Test status
Simulation time 21163711 ps
CPU time 1.08 seconds
Started Sep 04 02:03:09 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184880157 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.184880157
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.2986624263
Short name T822
Test name
Test status
Simulation time 18000436 ps
CPU time 1.11 seconds
Started Sep 04 02:03:09 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 208732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986624263 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2986624263
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.1966345769
Short name T827
Test name
Test status
Simulation time 35418782 ps
CPU time 1.08 seconds
Started Sep 04 02:03:09 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966345769 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.1966345769
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.437509961
Short name T818
Test name
Test status
Simulation time 105201806 ps
CPU time 1.72 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:10 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437509961 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.437509961
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.3121863865
Short name T830
Test name
Test status
Simulation time 815389256 ps
CPU time 4.98 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:13 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121863865 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3121863865
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.279046704
Short name T844
Test name
Test status
Simulation time 2417911189 ps
CPU time 17.86 seconds
Started Sep 04 02:03:08 AM UTC 24
Finished Sep 04 02:03:28 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279046704 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.279046704
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.85514943
Short name T821
Test name
Test status
Simulation time 24762119 ps
CPU time 1 seconds
Started Sep 04 02:03:09 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85514943 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.85514943
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3119159741
Short name T826
Test name
Test status
Simulation time 21809208 ps
CPU time 1.14 seconds
Started Sep 04 02:03:09 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119159741
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.3119159741
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.1450395933
Short name T820
Test name
Test status
Simulation time 60010723 ps
CPU time 0.99 seconds
Started Sep 04 02:03:09 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 209064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450395933
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.1450395933
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.3142159478
Short name T819
Test name
Test status
Simulation time 12251326 ps
CPU time 1.07 seconds
Started Sep 04 02:03:08 AM UTC 24
Finished Sep 04 02:03:10 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142159478 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3142159478
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.136605690
Short name T840
Test name
Test status
Simulation time 1519984396 ps
CPU time 6.85 seconds
Started Sep 04 02:03:10 AM UTC 24
Finished Sep 04 02:03:18 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136605690 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.136605690
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.78504915
Short name T815
Test name
Test status
Simulation time 20897835 ps
CPU time 1.25 seconds
Started Sep 04 02:03:07 AM UTC 24
Finished Sep 04 02:03:09 AM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78504915 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.78504915
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.2636962771
Short name T841
Test name
Test status
Simulation time 2788907197 ps
CPU time 9.04 seconds
Started Sep 04 02:03:10 AM UTC 24
Finished Sep 04 02:03:20 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636962771 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.2636962771
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.1410665964
Short name T852
Test name
Test status
Simulation time 8762221517 ps
CPU time 75.42 seconds
Started Sep 04 02:03:10 AM UTC 24
Finished Sep 04 02:04:27 AM UTC 24
Peak memory 220516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410665964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.1410665964
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.1445293708
Short name T823
Test name
Test status
Simulation time 27345518 ps
CPU time 1.32 seconds
Started Sep 04 02:03:08 AM UTC 24
Finished Sep 04 02:03:11 AM UTC 24
Peak memory 209860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445293708 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1445293708
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.1912358217
Short name T216
Test name
Test status
Simulation time 51236162 ps
CPU time 1.24 seconds
Started Sep 04 01:59:21 AM UTC 24
Finished Sep 04 01:59:23 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912358217 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.1912358217
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1507447507
Short name T166
Test name
Test status
Simulation time 29030689 ps
CPU time 1.13 seconds
Started Sep 04 01:59:19 AM UTC 24
Finished Sep 04 01:59:21 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507447507 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.1507447507
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.37648559
Short name T164
Test name
Test status
Simulation time 58856711 ps
CPU time 1.26 seconds
Started Sep 04 01:59:17 AM UTC 24
Finished Sep 04 01:59:20 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37648559 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.37648559
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.3138343767
Short name T215
Test name
Test status
Simulation time 52916350 ps
CPU time 1.19 seconds
Started Sep 04 01:59:20 AM UTC 24
Finished Sep 04 01:59:22 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138343767 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.3138343767
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.2348739459
Short name T172
Test name
Test status
Simulation time 25046158 ps
CPU time 1.01 seconds
Started Sep 04 01:59:16 AM UTC 24
Finished Sep 04 01:59:18 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348739459 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2348739459
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.1938651957
Short name T18
Test name
Test status
Simulation time 2367187234 ps
CPU time 23.71 seconds
Started Sep 04 01:59:17 AM UTC 24
Finished Sep 04 01:59:42 AM UTC 24
Peak memory 210764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938651957 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1938651957
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.1761189692
Short name T68
Test name
Test status
Simulation time 437292460 ps
CPU time 2.3 seconds
Started Sep 04 01:59:17 AM UTC 24
Finished Sep 04 01:59:21 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761189692 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.1761189692
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.3254028224
Short name T167
Test name
Test status
Simulation time 42478590 ps
CPU time 1.22 seconds
Started Sep 04 01:59:18 AM UTC 24
Finished Sep 04 01:59:21 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254028224 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.3254028224
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2000091883
Short name T165
Test name
Test status
Simulation time 33361052 ps
CPU time 1.11 seconds
Started Sep 04 01:59:19 AM UTC 24
Finished Sep 04 01:59:21 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000091883
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.2000091883
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.4026593329
Short name T214
Test name
Test status
Simulation time 23066781 ps
CPU time 1.26 seconds
Started Sep 04 01:59:19 AM UTC 24
Finished Sep 04 01:59:21 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026593329
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.4026593329
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.3381326720
Short name T163
Test name
Test status
Simulation time 38428548 ps
CPU time 1.23 seconds
Started Sep 04 01:59:17 AM UTC 24
Finished Sep 04 01:59:19 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381326720 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3381326720
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.2933990735
Short name T100
Test name
Test status
Simulation time 1602947988 ps
CPU time 5.59 seconds
Started Sep 04 01:59:20 AM UTC 24
Finished Sep 04 01:59:26 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933990735 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2933990735
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.3744024453
Short name T157
Test name
Test status
Simulation time 319540235 ps
CPU time 2.05 seconds
Started Sep 04 01:59:16 AM UTC 24
Finished Sep 04 01:59:19 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744024453 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3744024453
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.1207165672
Short name T60
Test name
Test status
Simulation time 9103872366 ps
CPU time 56.78 seconds
Started Sep 04 01:59:20 AM UTC 24
Finished Sep 04 02:00:18 AM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207165672 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.1207165672
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.4257742976
Short name T89
Test name
Test status
Simulation time 4303282862 ps
CPU time 60.1 seconds
Started Sep 04 01:59:20 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 220496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257742976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.4257742976
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.1388277928
Short name T162
Test name
Test status
Simulation time 16708980 ps
CPU time 1.15 seconds
Started Sep 04 01:59:17 AM UTC 24
Finished Sep 04 01:59:19 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388277928 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1388277928
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.3286515766
Short name T222
Test name
Test status
Simulation time 13782765 ps
CPU time 1.07 seconds
Started Sep 04 01:59:26 AM UTC 24
Finished Sep 04 01:59:28 AM UTC 24
Peak memory 210040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286515766 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.3286515766
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.4192029076
Short name T101
Test name
Test status
Simulation time 41542442 ps
CPU time 1.3 seconds
Started Sep 04 01:59:25 AM UTC 24
Finished Sep 04 01:59:27 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192029076 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.4192029076
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.662480601
Short name T199
Test name
Test status
Simulation time 23333663 ps
CPU time 1.04 seconds
Started Sep 04 01:59:22 AM UTC 24
Finished Sep 04 01:59:24 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662480601 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.662480601
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.899213930
Short name T221
Test name
Test status
Simulation time 16523006 ps
CPU time 1.17 seconds
Started Sep 04 01:59:25 AM UTC 24
Finished Sep 04 01:59:27 AM UTC 24
Peak memory 209132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899213930 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.899213930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.2239560425
Short name T217
Test name
Test status
Simulation time 97432191 ps
CPU time 1.46 seconds
Started Sep 04 01:59:21 AM UTC 24
Finished Sep 04 01:59:23 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239560425 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2239560425
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.2153853245
Short name T16
Test name
Test status
Simulation time 1394248998 ps
CPU time 16.78 seconds
Started Sep 04 01:59:21 AM UTC 24
Finished Sep 04 01:59:39 AM UTC 24
Peak memory 210460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153853245 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2153853245
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.620221289
Short name T99
Test name
Test status
Simulation time 1947316815 ps
CPU time 16.16 seconds
Started Sep 04 01:59:21 AM UTC 24
Finished Sep 04 01:59:38 AM UTC 24
Peak memory 210652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620221289 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.620221289
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.1332893408
Short name T218
Test name
Test status
Simulation time 22919128 ps
CPU time 0.94 seconds
Started Sep 04 01:59:22 AM UTC 24
Finished Sep 04 01:59:24 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332893408 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.1332893408
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2944176176
Short name T173
Test name
Test status
Simulation time 21148572 ps
CPU time 1.22 seconds
Started Sep 04 01:59:24 AM UTC 24
Finished Sep 04 01:59:26 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944176176
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.2944176176
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.416096404
Short name T205
Test name
Test status
Simulation time 23467350 ps
CPU time 1.32 seconds
Started Sep 04 01:59:24 AM UTC 24
Finished Sep 04 01:59:26 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416096404 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.416096404
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.4264307335
Short name T219
Test name
Test status
Simulation time 16026703 ps
CPU time 1.12 seconds
Started Sep 04 01:59:22 AM UTC 24
Finished Sep 04 01:59:24 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264307335 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.4264307335
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.1787226200
Short name T137
Test name
Test status
Simulation time 819096285 ps
CPU time 5.69 seconds
Started Sep 04 01:59:25 AM UTC 24
Finished Sep 04 01:59:32 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787226200 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.1787226200
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.2707196396
Short name T168
Test name
Test status
Simulation time 39666998 ps
CPU time 0.99 seconds
Started Sep 04 01:59:21 AM UTC 24
Finished Sep 04 01:59:23 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707196396 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.2707196396
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.972166495
Short name T71
Test name
Test status
Simulation time 11563612861 ps
CPU time 54.55 seconds
Started Sep 04 01:59:25 AM UTC 24
Finished Sep 04 02:00:21 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972166495 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.972166495
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.3399680892
Short name T90
Test name
Test status
Simulation time 4570633564 ps
CPU time 67.11 seconds
Started Sep 04 01:59:25 AM UTC 24
Finished Sep 04 02:00:34 AM UTC 24
Peak memory 224424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399680892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.3399680892
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.838187575
Short name T220
Test name
Test status
Simulation time 49700259 ps
CPU time 1.5 seconds
Started Sep 04 01:59:22 AM UTC 24
Finished Sep 04 01:59:25 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838187575 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.838187575
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.3279918467
Short name T96
Test name
Test status
Simulation time 72638371 ps
CPU time 1.53 seconds
Started Sep 04 01:59:34 AM UTC 24
Finished Sep 04 01:59:37 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279918467 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.3279918467
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.4013070941
Short name T115
Test name
Test status
Simulation time 88633046 ps
CPU time 1.68 seconds
Started Sep 04 01:59:31 AM UTC 24
Finished Sep 04 01:59:33 AM UTC 24
Peak memory 210520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013070941 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.4013070941
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.3788276823
Short name T200
Test name
Test status
Simulation time 12776926 ps
CPU time 0.91 seconds
Started Sep 04 01:59:30 AM UTC 24
Finished Sep 04 01:59:31 AM UTC 24
Peak memory 209128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788276823 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.3788276823
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.1761419787
Short name T230
Test name
Test status
Simulation time 16537448 ps
CPU time 1.13 seconds
Started Sep 04 01:59:32 AM UTC 24
Finished Sep 04 01:59:34 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761419787 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.1761419787
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.1849488306
Short name T224
Test name
Test status
Simulation time 42476073 ps
CPU time 1.27 seconds
Started Sep 04 01:59:27 AM UTC 24
Finished Sep 04 01:59:29 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849488306 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1849488306
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.1003926260
Short name T19
Test name
Test status
Simulation time 2115078247 ps
CPU time 17.12 seconds
Started Sep 04 01:59:27 AM UTC 24
Finished Sep 04 01:59:45 AM UTC 24
Peak memory 210672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003926260 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1003926260
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.778090829
Short name T97
Test name
Test status
Simulation time 995179343 ps
CPU time 8.16 seconds
Started Sep 04 01:59:28 AM UTC 24
Finished Sep 04 01:59:38 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=778090829 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.778090829
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.591772544
Short name T229
Test name
Test status
Simulation time 341413118 ps
CPU time 3.36 seconds
Started Sep 04 01:59:30 AM UTC 24
Finished Sep 04 01:59:34 AM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591772544 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.591772544
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1643353978
Short name T227
Test name
Test status
Simulation time 15448629 ps
CPU time 1.12 seconds
Started Sep 04 01:59:31 AM UTC 24
Finished Sep 04 01:59:33 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643353978
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.1643353978
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.4027641362
Short name T228
Test name
Test status
Simulation time 142437106 ps
CPU time 2.07 seconds
Started Sep 04 01:59:31 AM UTC 24
Finished Sep 04 01:59:34 AM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027641362
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.4027641362
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.532307931
Short name T225
Test name
Test status
Simulation time 15438896 ps
CPU time 1.12 seconds
Started Sep 04 01:59:28 AM UTC 24
Finished Sep 04 01:59:30 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532307931 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.532307931
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.978442652
Short name T7
Test name
Test status
Simulation time 416101552 ps
CPU time 5 seconds
Started Sep 04 01:59:32 AM UTC 24
Finished Sep 04 01:59:38 AM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978442652 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.978442652
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.3516680746
Short name T223
Test name
Test status
Simulation time 33229902 ps
CPU time 1.16 seconds
Started Sep 04 01:59:27 AM UTC 24
Finished Sep 04 01:59:29 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516680746 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3516680746
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.1743184014
Short name T535
Test name
Test status
Simulation time 13159286672 ps
CPU time 129.04 seconds
Started Sep 04 01:59:33 AM UTC 24
Finished Sep 04 02:01:44 AM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743184014 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1743184014
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.3020484008
Short name T34
Test name
Test status
Simulation time 1190276598 ps
CPU time 21.82 seconds
Started Sep 04 01:59:32 AM UTC 24
Finished Sep 04 01:59:55 AM UTC 24
Peak memory 224260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020484008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.3020484008
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.489973866
Short name T226
Test name
Test status
Simulation time 150296229 ps
CPU time 2.18 seconds
Started Sep 04 01:59:29 AM UTC 24
Finished Sep 04 01:59:33 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489973866 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.489973866
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.1778668930
Short name T240
Test name
Test status
Simulation time 41231653 ps
CPU time 1.2 seconds
Started Sep 04 01:59:41 AM UTC 24
Finished Sep 04 01:59:44 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778668930 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.1778668930
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2728825975
Short name T236
Test name
Test status
Simulation time 65818428 ps
CPU time 1.48 seconds
Started Sep 04 01:59:39 AM UTC 24
Finished Sep 04 01:59:41 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728825975 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.2728825975
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.1049994508
Short name T201
Test name
Test status
Simulation time 69513911 ps
CPU time 1.34 seconds
Started Sep 04 01:59:38 AM UTC 24
Finished Sep 04 01:59:40 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049994508 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1049994508
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.1939594012
Short name T234
Test name
Test status
Simulation time 15241585 ps
CPU time 1.12 seconds
Started Sep 04 01:59:39 AM UTC 24
Finished Sep 04 01:59:41 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939594012 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.1939594012
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.4263640835
Short name T95
Test name
Test status
Simulation time 52742020 ps
CPU time 1.36 seconds
Started Sep 04 01:59:34 AM UTC 24
Finished Sep 04 01:59:37 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263640835 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.4263640835
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.2856809728
Short name T17
Test name
Test status
Simulation time 213444571 ps
CPU time 2.63 seconds
Started Sep 04 01:59:35 AM UTC 24
Finished Sep 04 01:59:39 AM UTC 24
Peak memory 210360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856809728 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2856809728
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.1683137470
Short name T249
Test name
Test status
Simulation time 1110455816 ps
CPU time 11.69 seconds
Started Sep 04 01:59:36 AM UTC 24
Finished Sep 04 01:59:48 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683137470 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.1683137470
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.584157399
Short name T232
Test name
Test status
Simulation time 40969800 ps
CPU time 1.58 seconds
Started Sep 04 01:59:38 AM UTC 24
Finished Sep 04 01:59:40 AM UTC 24
Peak memory 209008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584157399 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.584157399
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.952266776
Short name T233
Test name
Test status
Simulation time 16290868 ps
CPU time 1.13 seconds
Started Sep 04 01:59:39 AM UTC 24
Finished Sep 04 01:59:41 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952266776 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.952266776
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1429277642
Short name T235
Test name
Test status
Simulation time 49293341 ps
CPU time 1.35 seconds
Started Sep 04 01:59:39 AM UTC 24
Finished Sep 04 01:59:41 AM UTC 24
Peak memory 209976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429277642
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.1429277642
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.1859012119
Short name T98
Test name
Test status
Simulation time 32252662 ps
CPU time 1.18 seconds
Started Sep 04 01:59:36 AM UTC 24
Finished Sep 04 01:59:38 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859012119 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1859012119
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.3806609752
Short name T238
Test name
Test status
Simulation time 285166687 ps
CPU time 3.03 seconds
Started Sep 04 01:59:39 AM UTC 24
Finished Sep 04 01:59:43 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806609752 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3806609752
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.1206300504
Short name T94
Test name
Test status
Simulation time 24836564 ps
CPU time 1.31 seconds
Started Sep 04 01:59:34 AM UTC 24
Finished Sep 04 01:59:37 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206300504 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1206300504
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.1612691347
Short name T237
Test name
Test status
Simulation time 92888270 ps
CPU time 1.7 seconds
Started Sep 04 01:59:40 AM UTC 24
Finished Sep 04 01:59:43 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612691347 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.1612691347
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.3289353442
Short name T635
Test name
Test status
Simulation time 39428801848 ps
CPU time 160.9 seconds
Started Sep 04 01:59:40 AM UTC 24
Finished Sep 04 02:02:24 AM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289353442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.3289353442
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.2263956412
Short name T231
Test name
Test status
Simulation time 52628402 ps
CPU time 1.39 seconds
Started Sep 04 01:59:38 AM UTC 24
Finished Sep 04 01:59:40 AM UTC 24
Peak memory 208888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263956412 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2263956412
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.2414582515
Short name T251
Test name
Test status
Simulation time 39093826 ps
CPU time 1.24 seconds
Started Sep 04 01:59:46 AM UTC 24
Finished Sep 04 01:59:49 AM UTC 24
Peak memory 210100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414582515 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.2414582515
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1550712317
Short name T116
Test name
Test status
Simulation time 19136942 ps
CPU time 1.21 seconds
Started Sep 04 01:59:44 AM UTC 24
Finished Sep 04 01:59:46 AM UTC 24
Peak memory 209072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550712317 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.1550712317
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.2934331737
Short name T202
Test name
Test status
Simulation time 72330994 ps
CPU time 1.05 seconds
Started Sep 04 01:59:43 AM UTC 24
Finished Sep 04 01:59:45 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934331737 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.2934331737
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.2776890424
Short name T245
Test name
Test status
Simulation time 15105971 ps
CPU time 1.06 seconds
Started Sep 04 01:59:44 AM UTC 24
Finished Sep 04 01:59:46 AM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776890424 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.2776890424
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.3068192590
Short name T241
Test name
Test status
Simulation time 26378660 ps
CPU time 1.16 seconds
Started Sep 04 01:59:41 AM UTC 24
Finished Sep 04 01:59:44 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068192590 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.3068192590
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2845827270
Short name T33
Test name
Test status
Simulation time 820167832 ps
CPU time 7.01 seconds
Started Sep 04 01:59:42 AM UTC 24
Finished Sep 04 01:59:50 AM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845827270 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2845827270
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.3586891804
Short name T261
Test name
Test status
Simulation time 854838085 ps
CPU time 12.28 seconds
Started Sep 04 01:59:43 AM UTC 24
Finished Sep 04 01:59:56 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586891804 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.3586891804
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.652527681
Short name T244
Test name
Test status
Simulation time 91271874 ps
CPU time 1.33 seconds
Started Sep 04 01:59:43 AM UTC 24
Finished Sep 04 01:59:45 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652527681 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.652527681
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2549413918
Short name T247
Test name
Test status
Simulation time 60561057 ps
CPU time 1.43 seconds
Started Sep 04 01:59:44 AM UTC 24
Finished Sep 04 01:59:46 AM UTC 24
Peak memory 209068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549413918
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.2549413918
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1344487632
Short name T246
Test name
Test status
Simulation time 33492995 ps
CPU time 1.36 seconds
Started Sep 04 01:59:44 AM UTC 24
Finished Sep 04 01:59:46 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344487632
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.1344487632
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.4150026393
Short name T242
Test name
Test status
Simulation time 25287214 ps
CPU time 0.95 seconds
Started Sep 04 01:59:43 AM UTC 24
Finished Sep 04 01:59:45 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150026393 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.4150026393
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.60889475
Short name T138
Test name
Test status
Simulation time 873244906 ps
CPU time 6.76 seconds
Started Sep 04 01:59:45 AM UTC 24
Finished Sep 04 01:59:53 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60889475 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.60889475
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.2814914683
Short name T239
Test name
Test status
Simulation time 18523051 ps
CPU time 1.26 seconds
Started Sep 04 01:59:41 AM UTC 24
Finished Sep 04 01:59:44 AM UTC 24
Peak memory 210036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814914683 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2814914683
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.1339194820
Short name T248
Test name
Test status
Simulation time 25815572 ps
CPU time 1.24 seconds
Started Sep 04 01:59:45 AM UTC 24
Finished Sep 04 01:59:48 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339194820 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.1339194820
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.2459064216
Short name T408
Test name
Test status
Simulation time 9574825458 ps
CPU time 72.44 seconds
Started Sep 04 01:59:45 AM UTC 24
Finished Sep 04 02:00:59 AM UTC 24
Peak memory 227300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459064216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2459064216
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.2729774285
Short name T243
Test name
Test status
Simulation time 32810456 ps
CPU time 1.32 seconds
Started Sep 04 01:59:43 AM UTC 24
Finished Sep 04 01:59:45 AM UTC 24
Peak memory 210156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729774285 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_03/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2729774285
Directory /workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/9.clkmgr_trans/latest
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