Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	218692	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

536378

1

T4

24

T5

11

T6

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	216838	1			T4	42		T5	10		T29	4
values[0x0]	254815	1			T4	18		T5	9		T6	13
values[0x1]	283417	1			T4	21		T5	12		T6	20

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

603994

1

T4

37

T5

17

T6

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3777	1			T1	3		T2	2		T21	1
valid_sources[0x01]	2995	1			T1	4		T28	1		T50	13
valid_sources[0x02]	2694	1			T1	4		T2	13		T3	1
valid_sources[0x03]	3457	1			T44	1		T21	1		T3	1
valid_sources[0x04]	2912	1			T2	16		T25	1		T50	3
valid_sources[0x05]	2724	1			T32	9		T22	1		T3	1
valid_sources[0x06]	2513	1			T1	3		T3	1		T28	4
valid_sources[0x07]	2170	1			T1	1		T50	6		T27	8
valid_sources[0x08]	2550	1			T23	4		T50	9		T27	10
valid_sources[0x09]	4145	1			T5	1		T31	1		T1	2
valid_sources[0x0a]	3086	1			T29	2		T1	1		T19	4
valid_sources[0x0b]	2876	1			T28	1		T50	20		T27	1
valid_sources[0x0c]	2724	1			T1	1		T47	1		T2	7
valid_sources[0x0d]	2933	1			T31	1		T1	4		T21	1
valid_sources[0x0e]	2862	1			T1	1		T47	1		T28	2
valid_sources[0x0f]	2497	1			T5	1		T21	1		T28	2
valid_sources[0x10]	2564	1			T3	2		T25	1		T28	2
valid_sources[0x11]	3394	1			T28	4		T50	9		T36	1
valid_sources[0x12]	4216	1			T47	1		T50	16		T27	1
valid_sources[0x13]	2595	1			T31	1		T21	1		T28	7
valid_sources[0x14]	2793	1			T5	1		T1	3		T50	19
valid_sources[0x15]	2859	1			T20	13		T25	1		T50	19
valid_sources[0x16]	2492	1			T50	6		T27	1		T188	1
valid_sources[0x17]	2464	1			T2	3		T28	2		T50	7
valid_sources[0x18]	2727	1			T47	1		T3	1		T25	1
valid_sources[0x19]	3476	1			T22	1		T28	4		T50	3
valid_sources[0x1a]	2336	1			T47	1		T3	1		T23	3
valid_sources[0x1b]	2795	1			T21	1		T28	1		T50	5
valid_sources[0x1c]	2444	1			T5	1		T21	1		T28	3
valid_sources[0x1d]	2683	1			T57	9		T1	1		T21	1
valid_sources[0x1e]	2350	1			T1	1		T3	4		T28	1
valid_sources[0x1f]	2519	1			T6	10		T31	1		T1	2
valid_sources[0x20]	2999	1			T21	1		T25	2		T50	8
valid_sources[0x21]	2366	1			T57	1		T21	2		T23	1
valid_sources[0x22]	4531	1			T1	2		T3	2		T28	2
valid_sources[0x23]	3597	1			T6	6		T1	1		T50	16
valid_sources[0x24]	2830	1			T1	2		T3	1		T28	1
valid_sources[0x25]	2148	1			T1	1		T23	1		T28	1
valid_sources[0x26]	2387	1			T31	1		T1	1		T28	5
valid_sources[0x27]	3255	1			T1	1		T47	1		T21	1
valid_sources[0x28]	2652	1			T1	1		T50	26		T27	2
valid_sources[0x29]	3483	1			T5	1		T6	2		T31	1
valid_sources[0x2a]	3023	1			T44	1		T47	12		T50	13
valid_sources[0x2b]	2934	1			T31	1		T1	1		T21	2
valid_sources[0x2c]	2463	1			T5	1		T1	1		T21	2
valid_sources[0x2d]	3573	1			T3	1		T28	1		T50	8
valid_sources[0x2e]	3396	1			T1	1		T44	1		T2	11
valid_sources[0x2f]	2718	1			T1	1		T50	17		T27	6
valid_sources[0x30]	2332	1			T44	1		T3	2		T28	1
valid_sources[0x31]	2530	1			T31	1		T28	4		T50	13
valid_sources[0x32]	3146	1			T29	1		T31	1		T47	1
valid_sources[0x33]	2839	1			T31	1		T1	1		T44	1
valid_sources[0x34]	2995	1			T1	1		T28	1		T50	8
valid_sources[0x35]	2857	1			T57	5		T19	24		T21	1
valid_sources[0x36]	2822	1			T32	2		T44	1		T2	3
valid_sources[0x37]	2554	1			T50	21		T27	1		T11	1
valid_sources[0x38]	2965	1			T28	3		T50	10		T27	8
valid_sources[0x39]	2728	1			T5	1		T2	1		T3	4
valid_sources[0x3a]	3292	1			T1	1		T2	1		T3	1
valid_sources[0x3b]	2281	1			T1	2		T47	1		T3	1
valid_sources[0x3c]	2773	1			T1	1		T19	14		T28	2
valid_sources[0x3d]	2476	1			T5	2		T1	1		T2	29
valid_sources[0x3e]	2527	1			T5	1		T21	4		T3	4
valid_sources[0x3f]	2154	1			T2	2		T3	1		T28	1
valid_sources[0x40]	3378	1			T31	1		T21	1		T28	2
valid_sources[0x41]	2584	1			T32	24		T3	2		T28	2
valid_sources[0x42]	2569	1			T31	1		T35	49		T2	7
valid_sources[0x43]	2270	1			T28	2		T50	30		T27	12
valid_sources[0x44]	2468	1			T4	81		T1	4		T3	3
valid_sources[0x45]	3580	1			T31	1		T2	17		T3	2
valid_sources[0x46]	2450	1			T25	1		T50	23		T54	10
valid_sources[0x47]	3341	1			T31	1		T1	1		T49	10
valid_sources[0x48]	2225	1			T57	7		T1	4		T25	2
valid_sources[0x49]	2959	1			T31	1		T22	1		T25	2
valid_sources[0x4a]	2666	1			T2	5		T50	29		T27	5
valid_sources[0x4b]	3082	1			T1	2		T2	10		T50	11
valid_sources[0x4c]	2915	1			T44	1		T21	1		T3	1
valid_sources[0x4d]	2394	1			T6	2		T1	3		T47	2
valid_sources[0x4e]	4029	1			T1	2		T47	1		T26	58
valid_sources[0x4f]	2753	1			T1	1		T3	1		T28	1
valid_sources[0x50]	2764	1			T44	1		T3	3		T50	24
valid_sources[0x51]	2772	1			T1	1		T3	1		T25	1
valid_sources[0x52]	2422	1			T1	2		T44	1		T28	1
valid_sources[0x53]	2413	1			T6	10		T1	1		T25	1
valid_sources[0x54]	2828	1			T31	2		T1	1		T21	3
valid_sources[0x55]	2575	1			T31	1		T1	3		T25	1
valid_sources[0x56]	3271	1			T5	1		T31	1		T1	1
valid_sources[0x57]	3157	1			T5	1		T2	7		T28	5
valid_sources[0x58]	2664	1			T23	3		T28	1		T50	2
valid_sources[0x59]	2930	1			T5	1		T31	1		T1	2
valid_sources[0x5a]	2299	1			T1	1		T23	3		T28	4
valid_sources[0x5b]	2749	1			T31	1		T1	4		T28	2
valid_sources[0x5c]	4125	1			T47	1		T3	2		T28	3
valid_sources[0x5d]	2821	1			T1	1		T47	2		T25	1
valid_sources[0x5e]	2981	1			T1	1		T2	10		T50	13
valid_sources[0x5f]	2643	1			T31	1		T1	1		T3	1
valid_sources[0x60]	3107	1			T58	21		T3	1		T28	2
valid_sources[0x61]	2423	1			T1	1		T22	1		T25	1
valid_sources[0x62]	3234	1			T28	1		T50	1		T27	14
valid_sources[0x63]	2524	1			T47	2		T21	1		T22	1
valid_sources[0x64]	2586	1			T1	2		T44	1		T47	2
valid_sources[0x65]	2350	1			T1	3		T47	1		T28	2
valid_sources[0x66]	2362	1			T31	1		T47	1		T21	2
valid_sources[0x67]	2626	1			T34	1		T1	2		T21	1
valid_sources[0x68]	2212	1			T47	1		T21	1		T3	2
valid_sources[0x69]	3053	1			T1	1		T3	2		T24	16
valid_sources[0x6a]	3506	1			T1	1		T25	1		T28	2
valid_sources[0x6b]	2481	1			T3	1		T28	1		T50	15
valid_sources[0x6c]	3022	1			T31	2		T28	7		T50	10
valid_sources[0x6d]	2780	1			T1	1		T2	10		T50	20
valid_sources[0x6e]	3286	1			T32	6		T1	1		T47	2
valid_sources[0x6f]	3052	1			T31	1		T1	1		T25	1
valid_sources[0x70]	2838	1			T5	1		T1	3		T2	12
valid_sources[0x71]	3566	1			T5	1		T1	2		T47	7
valid_sources[0x72]	3257	1			T1	2		T2	5		T21	1
valid_sources[0x73]	2776	1			T31	1		T57	3		T47	1
valid_sources[0x74]	2592	1			T2	14		T23	8		T28	2
valid_sources[0x75]	3737	1			T31	1		T47	1		T3	2
valid_sources[0x76]	2766	1			T1	1		T2	7		T28	1
valid_sources[0x77]	2735	1			T1	3		T48	98		T2	4
valid_sources[0x78]	3374	1			T1	1		T21	1		T28	4
valid_sources[0x79]	2915	1			T3	1		T28	3		T50	10
valid_sources[0x7a]	2935	1			T57	6		T1	4		T2	2
valid_sources[0x7b]	2915	1			T3	2		T28	5		T50	10
valid_sources[0x7c]	3744	1			T1	1		T25	1		T28	1
valid_sources[0x7d]	2607	1			T1	1		T28	1		T50	12
valid_sources[0x7e]	2427	1			T5	1		T2	8		T3	1
valid_sources[0x7f]	2819	1			T32	4		T3	2		T25	1
valid_sources[0x80]	2982	1			T33	55		T1	1		T44	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

148671

1

T4

14

T5

3

T29

1

values[0x0]

all_enables

biggest_size

207099

1

T4

5

T5

5

T6

3

values[0x1]

all_enables

biggest_size

180608

1

T4

5

T5

3

T6

6