Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T6,T44,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T57
1	0	Covered	T30,T46,T55
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	182725605	9212	0	0
GateOpen_A	182725605	15885	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182725605	9212	0	0
T4	8620	4	0	0
T5	14190	0	0	0
T6	3684	40	0	0
T23	0	3	0	0
T25	0	23	0	0
T29	3313	0	0	0
T30	8379	19	0	0
T31	18968	0	0	0
T32	28087	0	0	0
T33	4380	0	0	0
T34	24494	0	0	0
T35	17769	0	0	0
T44	0	26	0	0
T46	0	12	0	0
T50	0	11	0	0
T55	0	3	0	0
T57	0	4	0	0
T177	0	24	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182725605	15885	0	0
T1	0	20	0	0
T4	8620	4	0	0
T5	14190	4	0	0
T6	3684	40	0	0
T29	3313	4	0	0
T30	8379	23	0	0
T31	18968	0	0	0
T32	28087	4	0	0
T33	4380	0	0	0
T34	24494	0	0	0
T35	17769	0	0	0
T44	0	26	0	0
T57	0	4	0	0
T58	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T6,T44,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T57
1	0	Covered	T30,T46,T55
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	19696329	2205	0	0
GateOpen_A	19696329	3867	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19696329	2205	0	0
T4	952	1	0	0
T5	1661	0	0	0
T6	399	10	0	0
T25	0	6	0	0
T29	351	0	0	0
T30	911	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3785	0	0	0
T35	2174	0	0	0
T44	0	5	0	0
T46	0	3	0	0
T50	0	3	0	0
T55	0	3	0	0
T57	0	1	0	0
T177	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19696329	3867	0	0
T1	0	5	0	0
T4	952	1	0	0
T5	1661	1	0	0
T6	399	10	0	0
T29	351	1	0	0
T30	911	6	0	0
T31	2099	0	0	0
T32	3365	1	0	0
T33	489	0	0	0
T34	3785	0	0	0
T35	2174	0	0	0
T44	0	5	0	0
T57	0	1	0	0
T58	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T6,T44,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T57
1	0	Covered	T30,T46,T55
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	39393085	2326	0	0
GateOpen_A	39393085	3988	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39393085	2326	0	0
T4	1903	1	0	0
T5	3322	0	0	0
T6	797	11	0	0
T23	0	1	0	0
T25	0	4	0	0
T29	701	0	0	0
T30	1821	5	0	0
T31	4198	0	0	0
T32	6732	0	0	0
T33	978	0	0	0
T34	7569	0	0	0
T35	4351	0	0	0
T44	0	7	0	0
T46	0	3	0	0
T50	0	3	0	0
T57	0	1	0	0
T177	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39393085	3988	0	0
T1	0	5	0	0
T4	1903	1	0	0
T5	3322	1	0	0
T6	797	11	0	0
T29	701	1	0	0
T30	1821	6	0	0
T31	4198	0	0	0
T32	6732	1	0	0
T33	978	0	0	0
T34	7569	0	0	0
T35	4351	0	0	0
T44	0	7	0	0
T57	0	1	0	0
T58	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T6,T44,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T57
1	0	Covered	T30,T46,T55
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	80725279	2343	0	0
GateOpen_A	80725279	4017	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80725279	2343	0	0
T4	3843	1	0	0
T5	6138	0	0	0
T6	1659	9	0	0
T23	0	1	0	0
T25	0	7	0	0
T29	1507	0	0	0
T30	3708	5	0	0
T31	8447	0	0	0
T32	11993	0	0	0
T33	1942	0	0	0
T34	8760	0	0	0
T35	7496	0	0	0
T44	0	7	0	0
T46	0	3	0	0
T50	0	3	0	0
T57	0	1	0	0
T177	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80725279	4017	0	0
T1	0	5	0	0
T4	3843	1	0	0
T5	6138	1	0	0
T6	1659	9	0	0
T29	1507	1	0	0
T30	3708	6	0	0
T31	8447	0	0	0
T32	11993	1	0	0
T33	1942	0	0	0
T34	8760	0	0	0
T35	7496	0	0	0
T44	0	7	0	0
T57	0	1	0	0
T58	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T30
0	1	Covered	T6,T44,T25
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T57
1	0	Covered	T30,T46,T55
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	42910912	2338	0	0
GateOpen_A	42910912	4013	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42910912	2338	0	0
T4	1922	1	0	0
T5	3069	0	0	0
T6	829	10	0	0
T23	0	1	0	0
T25	0	6	0	0
T29	754	0	0	0
T30	1939	4	0	0
T31	4224	0	0	0
T32	5997	0	0	0
T33	971	0	0	0
T34	4380	0	0	0
T35	3748	0	0	0
T44	0	7	0	0
T46	0	3	0	0
T50	0	2	0	0
T57	0	1	0	0
T177	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42910912	4013	0	0
T1	0	5	0	0
T4	1922	1	0	0
T5	3069	1	0	0
T6	829	10	0	0
T29	754	1	0	0
T30	1939	5	0	0
T31	4224	0	0	0
T32	5997	1	0	0
T33	971	0	0	0
T34	4380	0	0	0
T35	3748	0	0	0
T44	0	7	0	0
T57	0	1	0	0
T58	0	1	0	0