Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	191160580	32845	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	191160580	32845	0	0
T2	224475	45	0	0
T3	207210	0	0	0
T10	0	35	0	0
T11	0	93	0	0
T12	0	156	0	0
T13	0	199	0	0
T14	0	207	0	0
T15	0	84	0	0
T16	0	99	0	0
T17	0	219	0	0
T18	0	222	0	0
T19	10650	0	0	0
T20	6590	0	0	0
T21	11550	0	0	0
T22	7785	0	0	0
T23	7730	0	0	0
T24	78065	0	0	0
T25	14660	0	0	0
T26	14675	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38232116	4888	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	4888	0	0
T2	44895	8	0	0
T3	41442	0	0	0
T10	0	6	0	0
T11	0	12	0	0
T12	0	24	0	0
T13	0	32	0	0
T14	0	30	0	0
T15	0	11	0	0
T16	0	19	0	0
T17	0	31	0	0
T18	0	33	0	0
T19	2130	0	0	0
T20	1318	0	0	0
T21	2310	0	0	0
T22	1557	0	0	0
T23	1546	0	0	0
T24	15613	0	0	0
T25	2932	0	0	0
T26	2935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38232116	4901	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	4901	0	0
T2	44895	7	0	0
T3	41442	0	0	0
T10	0	6	0	0
T11	0	12	0	0
T12	0	24	0	0
T13	0	32	0	0
T14	0	30	0	0
T15	0	10	0	0
T16	0	19	0	0
T17	0	30	0	0
T18	0	28	0	0
T19	2130	0	0	0
T20	1318	0	0	0
T21	2310	0	0	0
T22	1557	0	0	0
T23	1546	0	0	0
T24	15613	0	0	0
T25	2932	0	0	0
T26	2935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38232116	6623	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	6623	0	0
T2	44895	9	0	0
T3	41442	0	0	0
T10	0	7	0	0
T11	0	19	0	0
T12	0	31	0	0
T13	0	41	0	0
T14	0	42	0	0
T15	0	17	0	0
T16	0	19	0	0
T17	0	49	0	0
T18	0	43	0	0
T19	2130	0	0	0
T20	1318	0	0	0
T21	2310	0	0	0
T22	1557	0	0	0
T23	1546	0	0	0
T24	15613	0	0	0
T25	2932	0	0	0
T26	2935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38232116	6550	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	6550	0	0
T2	44895	9	0	0
T3	41442	0	0	0
T10	0	7	0	0
T11	0	18	0	0
T12	0	32	0	0
T13	0	40	0	0
T14	0	42	0	0
T15	0	18	0	0
T16	0	19	0	0
T17	0	43	0	0
T18	0	45	0	0
T19	2130	0	0	0
T20	1318	0	0	0
T21	2310	0	0	0
T22	1557	0	0	0
T23	1546	0	0	0
T24	15613	0	0	0
T25	2932	0	0	0
T26	2935	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	38232116	9883	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	9883	0	0
T2	44895	12	0	0
T3	41442	0	0	0
T10	0	9	0	0
T11	0	32	0	0
T12	0	45	0	0
T13	0	54	0	0
T14	0	63	0	0
T15	0	28	0	0
T16	0	23	0	0
T17	0	66	0	0
T18	0	73	0	0
T19	2130	0	0	0
T20	1318	0	0	0
T21	2310	0	0	0
T22	1557	0	0	0
T23	1546	0	0	0
T24	15613	0	0	0
T25	2932	0	0	0
T26	2935	0	0	0