Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T45,T24

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	38232116	35399017	0	0
AllClkBypReqTrue_A	38232116	83670	0	0
IoClkBypReqFalse_A	38232116	35340895	0	2415
IoClkBypReqTrue_A	38232116	137054	0	0
LcClkBypAckFalse_A	38232116	35404608	0	0
LcClkBypAckTrue_A	38232116	78079	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	35399017	0	0
T4	1922	1833	0	0
T5	1598	1410	0	0
T6	1727	1629	0	0
T29	1539	1289	0	0
T30	1004	961	0	0
T31	1495	1480	0	0
T32	1873	1803	0	0
T33	2022	1708	0	0
T34	1095	1028	0	0
T35	1717	1422	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	83670	0	0
T5	1598	138	0	0
T6	1727	0	0	0
T19	0	279	0	0
T21	0	315	0	0
T26	0	436	0	0
T29	1539	0	0	0
T30	1004	0	0	0
T31	1495	0	0	0
T32	1873	33	0	0
T33	2022	72	0	0
T34	1095	41	0	0
T35	1717	254	0	0
T49	0	11	0	0
T76	820	25	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	35340895	0	2415
T4	1922	1831	0	3
T5	1598	1363	0	3
T6	1727	1627	0	3
T29	1539	1287	0	3
T30	1004	959	0	3
T31	1495	1478	0	3
T32	1873	1251	0	3
T33	2022	1778	0	3
T34	1095	1037	0	3
T35	1717	1349	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	137054	0	0
T5	1598	183	0	0
T6	1727	0	0	0
T19	0	354	0	0
T20	0	256	0	0
T21	0	481	0	0
T26	0	510	0	0
T29	1539	0	0	0
T30	1004	0	0	0
T31	1495	0	0	0
T32	1873	583	0	0
T33	2022	0	0	0
T34	1095	30	0	0
T35	1717	325	0	0
T76	820	59	0	0
T85	0	468	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	35404608	0	0
T4	1922	1833	0	0
T5	1598	1445	0	0
T6	1727	1629	0	0
T29	1539	1289	0	0
T30	1004	961	0	0
T31	1495	1480	0	0
T32	1873	1622	0	0
T33	2022	1780	0	0
T34	1095	1056	0	0
T35	1717	1468	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	78079	0	0
T5	1598	103	0	0
T6	1727	0	0	0
T19	0	215	0	0
T20	0	19	0	0
T21	0	195	0	0
T26	0	355	0	0
T29	1539	0	0	0
T30	1004	0	0	0
T31	1495	0	0	0
T32	1873	214	0	0
T33	2022	0	0	0
T34	1095	13	0	0
T35	1717	208	0	0
T76	820	22	0	0
T85	0	166	0	0