Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	357756356	9891	0	0
TransStop_A	357756356	5054	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357756356	9891	0	0
T4	16016	4	0	0
T5	25576	0	0	0
T6	6912	0	0	0
T23	0	4	0	0
T25	0	14	0	0
T29	6280	3	0	0
T30	14420	0	0	0
T31	35200	8	0	0
T32	49972	0	0	0
T33	8092	0	0	0
T34	36500	0	0	0
T35	31232	0	0	0
T47	0	24	0	0
T48	0	27	0	0
T50	0	12	0	0
T57	0	4	0	0
T84	0	31	0	0
T86	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	357756356	5054	0	0
T4	16016	4	0	0
T5	25576	0	0	0
T6	6912	0	0	0
T23	0	4	0	0
T25	0	2	0	0
T29	6280	3	0	0
T30	14420	0	0	0
T31	35200	1	0	0
T32	49972	0	0	0
T33	8092	0	0	0
T34	36500	0	0	0
T35	31232	0	0	0
T47	0	15	0	0
T48	0	11	0	0
T50	0	6	0	0
T57	0	4	0	0
T84	0	8	0	0
T86	0	16	0	0
T120	0	2	0	0
T121	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	89439089	2470	0	0
TransStop_A	89439089	1236	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	2470	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T25	0	3	0	0
T29	1570	1	0	0
T30	3605	0	0	0
T31	8800	3	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	7	0	0
T48	0	7	0	0
T50	0	4	0	0
T57	0	1	0	0
T84	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	1236	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T29	1570	1	0	0
T30	3605	0	0	0
T31	8800	1	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	5	0	0
T48	0	3	0	0
T50	0	2	0	0
T57	0	1	0	0
T84	0	2	0	0
T86	0	7	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	89439089	2471	0	0
TransStop_A	89439089	1277	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	2471	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T25	0	6	0	0
T29	1570	1	0	0
T30	3605	0	0	0
T31	8800	2	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	3	0	0
T48	0	7	0	0
T50	0	1	0	0
T57	0	1	0	0
T84	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	1277	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T29	1570	1	0	0
T30	3605	0	0	0
T31	8800	0	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	3	0	0
T48	0	4	0	0
T57	0	1	0	0
T84	0	1	0	0
T86	0	5	0	0
T120	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	89439089	2473	0	0
TransStop_A	89439089	1267	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	2473	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T25	0	3	0	0
T29	1570	1	0	0
T30	3605	0	0	0
T31	8800	2	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	7	0	0
T48	0	6	0	0
T50	0	3	0	0
T57	0	1	0	0
T84	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	1267	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T29	1570	1	0	0
T30	3605	0	0	0
T31	8800	0	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	3	0	0
T48	0	2	0	0
T50	0	2	0	0
T57	0	1	0	0
T84	0	4	0	0
T86	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	89439089	2477	0	0
TransStop_A	89439089	1274	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	2477	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T29	1570	0	0	0
T30	3605	0	0	0
T31	8800	1	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	7	0	0
T48	0	7	0	0
T50	0	4	0	0
T57	0	1	0	0
T84	0	8	0	0
T86	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89439089	1274	0	0
T4	4004	1	0	0
T5	6394	0	0	0
T6	1728	0	0	0
T23	0	1	0	0
T29	1570	0	0	0
T30	3605	0	0	0
T31	8800	0	0	0
T32	12493	0	0	0
T33	2023	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T47	0	4	0	0
T48	0	2	0	0
T50	0	2	0	0
T57	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0