Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	39214857	584430	0	0
clk_enables_rd_A	39214857	8093	0	0
clk_hints_rd_A	39214857	7207	0	0
extclk_ctrl_rd_A	39214857	11688	0	0
extclk_ctrl_regwen_rd_A	39214857	6341	0	0
jitter_enable_rd_A	39214857	15347	0	0
jitter_regwen_rd_A	39214857	6450	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	584430	0	0
T10	35784	0	0	0
T27	21527	0	0	0
T50	131065	3507	0	0
T54	0	3426	0	0
T55	1139	0	0	0
T63	0	3049	0	0
T77	0	8835	0	0
T78	0	9049	0	0
T79	0	9129	0	0
T80	0	3621	0	0
T81	0	27160	0	0
T82	0	17930	0	0
T83	0	6885	0	0
T84	2827	0	0	0
T85	1645	0	0	0
T86	2627	0	0	0
T87	1947	0	0	0
T88	2321	0	0	0
T89	2429	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	8093	0	0
T4	1922	4	0	0
T5	1598	0	0	0
T6	1727	0	0	0
T29	1539	0	0	0
T30	1004	0	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T54	0	167	0	0
T80	0	182	0	0
T83	0	127	0	0
T91	0	5	0	0
T142	0	4	0	0
T143	0	10	0	0
T144	0	1	0	0
T145	0	2	0	0
T146	0	8	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	7207	0	0
T4	1922	1	0	0
T5	1598	0	0	0
T6	1727	0	0	0
T29	1539	0	0	0
T30	1004	0	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T54	0	127	0	0
T80	0	151	0	0
T91	0	1	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	3	0	0
T145	0	5	0	0
T147	0	7	0	0
T148	0	8	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	11688	0	0
T1	2920	0	0	0
T19	0	50	0	0
T21	0	51	0	0
T26	0	41	0	0
T27	0	97	0	0
T32	1873	60	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T44	949	0	0	0
T45	28709	0	0	0
T51	0	34	0	0
T54	0	128	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T89	0	30	0	0
T90	0	9	0	0
T149	0	44	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	6341	0	0
T27	21527	90	0	0
T51	0	20	0	0
T54	0	125	0	0
T59	1268	0	0	0
T80	0	82	0	0
T83	0	145	0	0
T85	1645	0	0	0
T86	2627	0	0	0
T87	1947	0	0	0
T88	2321	0	0	0
T89	2429	0	0	0
T90	0	9	0	0
T120	1851	0	0	0
T150	0	20	0	0
T151	0	27	0	0
T152	0	17	0	0
T153	0	41	0	0
T154	746	0	0	0
T155	973	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	15347	0	0
T4	1922	74	0	0
T5	1598	0	0	0
T6	1727	0	0	0
T29	1539	0	0	0
T30	1004	0	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T54	0	337	0	0
T80	0	546	0	0
T91	0	112	0	0
T142	0	99	0	0
T143	0	116	0	0
T144	0	111	0	0
T145	0	103	0	0
T147	0	76	0	0
T156	0	127	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39214857	6450	0	0
T52	189642	0	0	0
T54	122075	181	0	0
T65	10576	0	0	0
T80	0	136	0	0
T83	0	123	0	0
T90	6678	0	0	0
T157	0	334	0	0
T158	0	363	0	0
T159	0	294	0	0
T160	0	184	0	0
T161	0	218	0	0
T162	0	498	0	0
T163	0	320	0	0
T164	1642	0	0	0
T165	2760	0	0	0
T166	1834	0	0	0
T167	1738	0	0	0
T168	1067	0	0	0
T169	1306	0	0	0