Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	114696348	422	0	0
StatusRise_A	114696348	422	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114696348	422	0	0
T1	8760	0	0	0
T30	3012	13	0	0
T31	4485	0	0	0
T32	5619	0	0	0
T33	6066	0	0	0
T34	3285	0	0	0
T35	5151	0	0	0
T46	0	8	0	0
T55	0	9	0	0
T57	4452	0	0	0
T58	5379	0	0	0
T76	2460	0	0	0
T170	0	16	0	0
T171	0	12	0	0
T172	0	17	0	0
T173	0	8	0	0
T174	0	3	0	0
T175	0	10	0	0
T176	0	4	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	114696348	422	0	0
T1	8760	0	0	0
T30	3012	13	0	0
T31	4485	0	0	0
T32	5619	0	0	0
T33	6066	0	0	0
T34	3285	0	0	0
T35	5151	0	0	0
T46	0	8	0	0
T55	0	9	0	0
T57	4452	0	0	0
T58	5379	0	0	0
T76	2460	0	0	0
T170	0	16	0	0
T171	0	12	0	0
T172	0	17	0	0
T173	0	8	0	0
T174	0	3	0	0
T175	0	10	0	0
T176	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38232116	138	0	0
StatusRise_A	38232116	138	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	138	0	0
T1	2920	0	0	0
T30	1004	4	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T46	0	2	0	0
T55	0	3	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	138	0	0
T1	2920	0	0	0
T30	1004	4	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T46	0	2	0	0
T55	0	3	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38232116	141	0	0
StatusRise_A	38232116	141	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	141	0	0
T1	2920	0	0	0
T30	1004	5	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0
T176	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	141	0	0
T1	2920	0	0	0
T30	1004	5	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0
T176	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	38232116	143	0	0
StatusRise_A	38232116	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	143	0	0
T1	2920	0	0	0
T30	1004	4	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T170	0	4	0	0
T171	0	4	0	0
T172	0	6	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	38232116	143	0	0
T1	2920	0	0	0
T30	1004	4	0	0
T31	1495	0	0	0
T32	1873	0	0	0
T33	2022	0	0	0
T34	1095	0	0	0
T35	1717	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	1484	0	0	0
T58	1793	0	0	0
T76	820	0	0	0
T170	0	4	0	0
T171	0	4	0	0
T172	0	6	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	1	0	0