Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	941471440	35281	0	0
CgEnOn_A	941471440	25802	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941471440	35281	0	0
T1	205427	0	0	0
T4	24635	7	0	0
T5	39761	3	0	0
T6	10590	40	0	0
T29	9590	4	0	0
T30	40198	47	0	0
T31	94924	6	0	0
T32	137860	3	0	0
T33	21866	3	0	0
T34	111300	3	0	0
T35	86726	3	0	0
T46	0	17	0	0
T47	0	7	0	0
T55	0	15	0	0
T57	7129	1	0	0
T58	8152	0	0	0
T63	0	5	0	0
T76	14167	0	0	0
T170	0	25	0	0
T171	0	25	0	0
T172	0	25	0	0
T173	0	15	0	0
T174	0	5	0	0
T175	0	20	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	941471440	25802	0	0
T1	205427	0	0	0
T4	24635	4	0	0
T5	39761	0	0	0
T6	10590	37	0	0
T23	0	3	0	0
T25	0	29	0	0
T29	9590	1	0	0
T30	40198	44	0	0
T31	94924	3	0	0
T32	137860	0	0	0
T33	21866	0	0	0
T34	111300	0	0	0
T35	86726	0	0	0
T44	0	33	0	0
T46	0	26	0	0
T47	0	7	0	0
T50	0	18	0	0
T55	0	18	0	0
T57	7129	4	0	0
T58	8152	0	0	0
T63	0	5	0	0
T76	14167	0	0	0
T170	0	25	0	0
T171	0	25	0	0
T172	0	25	0	0
T173	0	15	0	0
T174	0	5	0	0
T175	0	20	0	0
T177	0	20	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39392667	166	0	0
CgEnOn_A	39392667	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39392667	166	0	0
T1	15187	0	0	0
T30	1821	5	0	0
T31	4197	0	0	0
T32	6732	0	0	0
T33	978	0	0	0
T34	7568	0	0	0
T35	4351	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	703	0	0	0
T58	793	0	0	0
T63	0	1	0	0
T76	1488	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39392667	166	0	0
T1	15187	0	0	0
T30	1821	5	0	0
T31	4197	0	0	0
T32	6732	0	0	0
T33	978	0	0	0
T34	7568	0	0	0
T35	4351	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	703	0	0	0
T58	793	0	0	0
T63	0	1	0	0
T76	1488	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19695921	166	0	0
CgEnOn_A	19695921	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	166	0	0
T1	7594	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	352	0	0	0
T58	397	0	0	0
T63	0	1	0	0
T76	744	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	166	0	0
T1	7594	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	352	0	0	0
T58	397	0	0	0
T63	0	1	0	0
T76	744	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19695921	166	0	0
CgEnOn_A	19695921	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	166	0	0
T1	7594	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	352	0	0	0
T58	397	0	0	0
T63	0	1	0	0
T76	744	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	166	0	0
T1	7594	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	352	0	0	0
T58	397	0	0	0
T63	0	1	0	0
T76	744	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19695921	166	0	0
CgEnOn_A	19695921	166	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	166	0	0
T1	7594	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	352	0	0	0
T58	397	0	0	0
T63	0	1	0	0
T76	744	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	166	0	0
T1	7594	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	352	0	0	0
T58	397	0	0	0
T63	0	1	0	0
T76	744	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80724839	166	0	0
CgEnOn_A	80724839	147	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80724839	166	0	0
T1	46732	0	0	0
T30	3707	5	0	0
T31	8447	0	0	0
T32	11992	0	0	0
T33	1941	0	0	0
T34	8759	0	0	0
T35	7495	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	1499	0	0	0
T58	1721	0	0	0
T63	0	1	0	0
T76	2915	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80724839	147	0	0
T1	46732	0	0	0
T30	3707	5	0	0
T31	8447	0	0	0
T32	11992	0	0	0
T33	1941	0	0	0
T34	8759	0	0	0
T35	7495	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	1499	0	0	0
T58	1721	0	0	0
T63	0	1	0	0
T76	2915	0	0	0
T170	0	5	0	0
T171	0	5	0	0
T172	0	5	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	89438619	148	0	0
CgEnOn_A	89438619	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	148	0	0
T1	48680	0	0	0
T30	3604	4	0	0
T31	8799	0	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T55	0	3	0	0
T57	1561	0	0	0
T58	1793	0	0	0
T76	3037	0	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	141	0	0
T1	48680	0	0	0
T30	3604	4	0	0
T31	8799	0	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T55	0	3	0	0
T57	1561	0	0	0
T58	1793	0	0	0
T76	3037	0	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	89438619	148	0	0
CgEnOn_A	89438619	141	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	148	0	0
T1	48680	0	0	0
T30	3604	4	0	0
T31	8799	0	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T55	0	3	0	0
T57	1561	0	0	0
T58	1793	0	0	0
T76	3037	0	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	141	0	0
T1	48680	0	0	0
T30	3604	4	0	0
T31	8799	0	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T55	0	3	0	0
T57	1561	0	0	0
T58	1793	0	0	0
T76	3037	0	0	0
T170	0	7	0	0
T171	0	3	0	0
T172	0	6	0	0
T173	0	2	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	42910515	147	0	0
CgEnOn_A	42910515	146	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42910515	147	0	0
T1	23366	0	0	0
T30	1939	4	0	0
T31	4223	0	0	0
T32	5997	0	0	0
T33	970	0	0	0
T34	4380	0	0	0
T35	3747	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	749	0	0	0
T58	861	0	0	0
T76	1458	0	0	0
T170	0	4	0	0
T171	0	4	0	0
T172	0	6	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42910515	146	0	0
T1	23366	0	0	0
T30	1939	4	0	0
T31	4223	0	0	0
T32	5997	0	0	0
T33	970	0	0	0
T34	4380	0	0	0
T35	3747	0	0	0
T46	0	3	0	0
T55	0	3	0	0
T57	749	0	0	0
T58	861	0	0	0
T76	1458	0	0	0
T170	0	4	0	0
T171	0	4	0	0
T172	0	6	0	0
T173	0	3	0	0
T174	0	1	0	0
T175	0	3	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T46,T55
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	19695921	5871	0	0
CgEnOn_A	19695921	3527	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	5871	0	0
T4	951	2	0	0
T5	1661	1	0	0
T6	398	14	0	0
T29	350	1	0	0
T30	910	6	0	0
T31	2099	1	0	0
T32	3365	1	0	0
T33	489	1	0	0
T34	3784	1	0	0
T35	2173	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	19695921	3527	0	0
T4	951	1	0	0
T5	1661	0	0	0
T6	398	13	0	0
T25	0	9	0	0
T29	350	0	0	0
T30	910	5	0	0
T31	2099	0	0	0
T32	3365	0	0	0
T33	489	0	0	0
T34	3784	0	0	0
T35	2173	0	0	0
T44	0	11	0	0
T46	0	3	0	0
T50	0	6	0	0
T55	0	3	0	0
T57	0	1	0	0
T177	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T46,T55
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	39392667	5875	0	0
CgEnOn_A	39392667	3531	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39392667	5875	0	0
T4	1903	2	0	0
T5	3321	1	0	0
T6	796	13	0	0
T29	700	1	0	0
T30	1821	6	0	0
T31	4197	1	0	0
T32	6732	1	0	0
T33	978	1	0	0
T34	7568	1	0	0
T35	4351	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	39392667	3531	0	0
T4	1903	1	0	0
T5	3321	0	0	0
T6	796	12	0	0
T23	0	1	0	0
T25	0	8	0	0
T29	700	0	0	0
T30	1821	5	0	0
T31	4197	0	0	0
T32	6732	0	0	0
T33	978	0	0	0
T34	7568	0	0	0
T35	4351	0	0	0
T44	0	10	0	0
T46	0	3	0	0
T50	0	6	0	0
T57	0	1	0	0
T177	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T46,T55
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	80724839	5870	0	0
CgEnOn_A	80724839	3507	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80724839	5870	0	0
T4	3843	2	0	0
T5	6138	1	0	0
T6	1659	13	0	0
T29	1507	1	0	0
T30	3707	6	0	0
T31	8447	1	0	0
T32	11992	1	0	0
T33	1941	1	0	0
T34	8759	1	0	0
T35	7495	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	80724839	3507	0	0
T4	3843	1	0	0
T5	6138	0	0	0
T6	1659	12	0	0
T23	0	1	0	0
T25	0	9	0	0
T29	1507	0	0	0
T30	3707	5	0	0
T31	8447	0	0	0
T32	11992	0	0	0
T33	1941	0	0	0
T34	8759	0	0	0
T35	7495	0	0	0
T44	0	12	0	0
T46	0	3	0	0
T50	0	6	0	0
T57	0	1	0	0
T177	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T46,T55
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	42910515	5909	0	0
CgEnOn_A	42910515	3543	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42910515	5909	0	0
T4	1922	2	0	0
T5	3069	1	0	0
T6	829	14	0	0
T29	753	1	0	0
T30	1939	5	0	0
T31	4223	1	0	0
T32	5997	1	0	0
T33	970	1	0	0
T34	4380	1	0	0
T35	3747	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	42910515	3543	0	0
T4	1922	1	0	0
T5	3069	0	0	0
T6	829	13	0	0
T23	0	1	0	0
T25	0	10	0	0
T29	753	0	0	0
T30	1939	4	0	0
T31	4223	0	0	0
T32	5997	0	0	0
T33	970	0	0	0
T34	4380	0	0	0
T35	3747	0	0	0
T44	0	13	0	0
T46	0	3	0	0
T50	0	6	0	0
T57	0	1	0	0
T177	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	89438619	2618	0	0
CgEnOn_A	89438619	2611	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2618	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	3	0	0
T29	1570	1	0	0
T30	3604	4	0	0
T31	8799	3	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	7	0	0
T48	0	7	0	0
T57	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2611	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	3	0	0
T29	1570	1	0	0
T30	3604	4	0	0
T31	8799	3	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	7	0	0
T48	0	7	0	0
T57	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	89438619	2619	0	0
CgEnOn_A	89438619	2612	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2619	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	6	0	0
T29	1570	1	0	0
T30	3604	4	0	0
T31	8799	2	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	7	0	0
T57	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2612	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	6	0	0
T29	1570	1	0	0
T30	3604	4	0	0
T31	8799	2	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	7	0	0
T57	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Covered	T4,T29,T31
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	89438619	2621	0	0
CgEnOn_A	89438619	2614	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2621	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	3	0	0
T29	1570	1	0	0
T30	3604	4	0	0
T31	8799	2	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	7	0	0
T48	0	6	0	0
T57	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2614	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	3	0	0
T29	1570	1	0	0
T30	3604	4	0	0
T31	8799	2	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	7	0	0
T48	0	6	0	0
T57	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

23                        logic clk_enable;
24         1/1            always_comb clk_enable = ip_clk_en && sw_clk_en;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T30,T1,T45
1	0	Covered	T4,T31,T57
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	89438619	2625	0	0
CgEnOn_A	89438619	2618	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2625	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T29	1570	0	0	0
T30	3604	4	0	0
T31	8799	1	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	7	0	0
T48	0	7	0	0
T50	0	4	0	0
T57	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	89438619	2618	0	0
T4	4004	1	0	0
T5	6393	0	0	0
T6	1727	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T29	1570	0	0	0
T30	3604	4	0	0
T31	8799	1	0	0
T32	12493	0	0	0
T33	2022	0	0	0
T34	9125	0	0	0
T35	7808	0	0	0
T46	0	2	0	0
T47	0	7	0	0
T48	0	7	0	0
T50	0	4	0	0
T57	0	1	0	0