Unified Coverage Report :: Tests

Tests

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Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.51	99.15	95.80	100.00	100.00	98.81	97.02	98.80

Total test records in report: 1010

tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T1001	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.4100364089			Sep 09 05:18:04 AM UTC 24	Sep 09 05:18:09 AM UTC 24	12860030 ps
T1002	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.4172072395			Sep 09 05:18:04 AM UTC 24	Sep 09 05:18:09 AM UTC 24	23204396 ps
T1003	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.1881711815			Sep 09 05:18:04 AM UTC 24	Sep 09 05:18:09 AM UTC 24	18123649 ps
T1004	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.88767754			Sep 09 05:18:04 AM UTC 24	Sep 09 05:18:09 AM UTC 24	42161257 ps
T1005	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.3716676535			Sep 09 05:18:04 AM UTC 24	Sep 09 05:18:09 AM UTC 24	19472345 ps
T1006	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.893185084			Sep 09 05:18:05 AM UTC 24	Sep 09 05:18:09 AM UTC 24	11541641 ps
T1007	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2859006131			Sep 09 05:18:04 AM UTC 24	Sep 09 05:18:09 AM UTC 24	21802797 ps
T1008	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.2014181073			Sep 09 05:18:05 AM UTC 24	Sep 09 05:18:09 AM UTC 24	26865055 ps
T1009	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.4145569388			Sep 09 05:18:05 AM UTC 24	Sep 09 05:18:19 AM UTC 24	17142836 ps
T1010	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.3298523535			Sep 09 05:18:05 AM UTC 24	Sep 09 05:18:19 AM UTC 24	13360280 ps

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.4268582067
Short name	T35
Test name
Test status
Simulation time	78103081 ps
CPU time	1.73 seconds
Started	Sep 09 05:13:03 AM UTC 24
Finished	Sep 09 05:13:06 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268582067 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.4268582067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.1500833588
Short name	T50
Test name
Test status
Simulation time	1310684387 ps
CPU time	18.32 seconds
Started	Sep 09 05:13:04 AM UTC 24
Finished	Sep 09 05:13:24 AM UTC 24
Peak memory	220104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500833588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.1500833588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.226358793
Short name	T2
Test name
Test status
Simulation time	2137875887 ps
CPU time	18.57 seconds
Started	Sep 09 05:12:54 AM UTC 24
Finished	Sep 09 05:13:14 AM UTC 24
Peak memory	210776 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226358793 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.226358793
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.2541362138
Short name	T1
Test name
Test status
Simulation time	486832692 ps
CPU time	3.76 seconds
Started	Sep 09 05:13:03 AM UTC 24
Finished	Sep 09 05:13:08 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541362138 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.2541362138
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1552600223
Short name	T70
Test name
Test status
Simulation time	269056154 ps
CPU time	2.09 seconds
Started	Sep 09 05:17:37 AM UTC 24
Finished	Sep 09 05:17:40 AM UTC 24
Peak memory	222028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552600 223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.1552600223
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.2899573146
Short name	T24
Test name
Test status
Simulation time	162665967 ps
CPU time	3.55 seconds
Started	Sep 09 05:13:15 AM UTC 24
Finished	Sep 09 05:13:20 AM UTC 24
Peak memory	242604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899573146 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.2899573146
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.2407630755
Short name	T46
Test name
Test status
Simulation time	17232550 ps
CPU time	1.18 seconds
Started	Sep 09 05:13:09 AM UTC 24
Finished	Sep 09 05:13:11 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407630755 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2407630755
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.1650028072
Short name	T91
Test name
Test status
Simulation time	2056469985 ps
CPU time	16.44 seconds
Started	Sep 09 05:13:26 AM UTC 24
Finished	Sep 09 05:13:44 AM UTC 24
Peak memory	210588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650028072 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.1650028072
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.2845456731
Short name	T48
Test name
Test status
Simulation time	23902548 ps
CPU time	1.44 seconds
Started	Sep 09 05:13:09 AM UTC 24
Finished	Sep 09 05:13:11 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845456731 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.2845456731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.2277593160
Short name	T5
Test name
Test status
Simulation time	63961130 ps
CPU time	1.57 seconds
Started	Sep 09 05:12:53 AM UTC 24
Finished	Sep 09 05:12:56 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277593160 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2277593160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.2924722600
Short name	T108
Test name
Test status
Simulation time	557906318 ps
CPU time	5.23 seconds
Started	Sep 09 05:17:30 AM UTC 24
Finished	Sep 09 05:17:36 AM UTC 24
Peak memory	212512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924722600 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.2924722600
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.3613809908
Short name	T10
Test name
Test status
Simulation time	2385714914 ps
CPU time	17.7 seconds
Started	Sep 09 05:13:07 AM UTC 24
Finished	Sep 09 05:13:25 AM UTC 24
Peak memory	210764 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613809908 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3613809908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.2352352080
Short name	T66
Test name
Test status
Simulation time	312224062 ps
CPU time	3.78 seconds
Started	Sep 09 05:17:29 AM UTC 24
Finished	Sep 09 05:17:34 AM UTC 24
Peak memory	221972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352352 080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.2352352080
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.3240561051
Short name	T374
Test name
Test status
Simulation time	8022764297 ps
CPU time	47.12 seconds
Started	Sep 09 05:14:08 AM UTC 24
Finished	Sep 09 05:14:57 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240561051 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.3240561051
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.3817475625
Short name	T159
Test name
Test status
Simulation time	5234477738 ps
CPU time	50.27 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:16:23 AM UTC 24
Peak memory	223940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817475625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3817475625
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.295981092
Short name	T58
Test name
Test status
Simulation time	17957428 ps
CPU time	1.25 seconds
Started	Sep 09 05:13:05 AM UTC 24
Finished	Sep 09 05:13:08 AM UTC 24
Peak memory	210212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295981092 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.295981092
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1376563164
Short name	T32
Test name
Test status
Simulation time	124950606 ps
CPU time	2.04 seconds
Started	Sep 09 05:13:01 AM UTC 24
Finished	Sep 09 05:13:04 AM UTC 24
Peak memory	210244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376563164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.1376563164
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2534116602
Short name	T118
Test name
Test status
Simulation time	99126731 ps
CPU time	2.31 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534116602 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.2534116602
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.6317768
Short name	T8
Test name
Test status
Simulation time	985658219 ps
CPU time	7.07 seconds
Started	Sep 09 05:16:20 AM UTC 24
Finished	Sep 09 05:16:28 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6317768 -assert nopostproc +UVM_TESTNAME=clkmg r_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.6317768
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.44465085
Short name	T112
Test name
Test status
Simulation time	166625675 ps
CPU time	3.03 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:44 AM UTC 24
Peak memory	212400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44465085 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.44465085
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.934661650
Short name	T43
Test name
Test status
Simulation time	3009031869 ps
CPU time	18.02 seconds
Started	Sep 09 05:14:19 AM UTC 24
Finished	Sep 09 05:14:38 AM UTC 24
Peak memory	210996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934661650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.934661650
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1437641818
Short name	T72
Test name
Test status
Simulation time	164040984 ps
CPU time	2.89 seconds
Started	Sep 09 05:17:39 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	221920 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1437641818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_ errors_with_csr_rw.1437641818
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.153215825
Short name	T93
Test name
Test status
Simulation time	19349815 ps
CPU time	1.65 seconds
Started	Sep 09 05:17:32 AM UTC 24
Finished	Sep 09 05:17:34 AM UTC 24
Peak memory	211932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153215825 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.153215825
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.2168412210
Short name	T34
Test name
Test status
Simulation time	91272904 ps
CPU time	1.73 seconds
Started	Sep 09 05:13:02 AM UTC 24
Finished	Sep 09 05:13:05 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168412210 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.2168412210
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.2902742836
Short name	T27
Test name
Test status
Simulation time	1956976839 ps
CPU time	12.23 seconds
Started	Sep 09 05:13:12 AM UTC 24
Finished	Sep 09 05:13:26 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902742836 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2902742836
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.1380056416
Short name	T126
Test name
Test status
Simulation time	333340718 ps
CPU time	2.56 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:55 AM UTC 24
Peak memory	222044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380056 416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.1380056416
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.503644065
Short name	T130
Test name
Test status
Simulation time	258329291 ps
CPU time	2.19 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	212756 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5036440 65 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.503644065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.970747578
Short name	T62
Test name
Test status
Simulation time	20404441801 ps
CPU time	136.12 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:19:10 AM UTC 24
Peak memory	227540 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970747578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.970747578
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2798913665
Short name	T116
Test name
Test status
Simulation time	398554205 ps
CPU time	3.75 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:05 AM UTC 24
Peak memory	212400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798913665 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.2798913665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2193700628
Short name	T877
Test name
Test status
Simulation time	1739511581 ps
CPU time	10.33 seconds
Started	Sep 09 05:17:31 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	212596 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193700628 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.2193700628
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1788460980
Short name	T111
Test name
Test status
Simulation time	59804509 ps
CPU time	1.45 seconds
Started	Sep 09 05:17:31 AM UTC 24
Finished	Sep 09 05:17:34 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788460980 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.1788460980
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.903294512
Short name	T860
Test name
Test status
Simulation time	58600489 ps
CPU time	1.56 seconds
Started	Sep 09 05:17:33 AM UTC 24
Finished	Sep 09 05:17:35 AM UTC 24
Peak memory	211744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=903294512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 0.clkmgr_csr_mem_rw_with_rand_reset.903294512
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.74942301
Short name	T92
Test name
Test status
Simulation time	19842005 ps
CPU time	1.34 seconds
Started	Sep 09 05:17:31 AM UTC 24
Finished	Sep 09 05:17:34 AM UTC 24
Peak memory	211616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74942301 -assert nopos tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.74942301
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.791740290
Short name	T858
Test name
Test status
Simulation time	13186579 ps
CPU time	0.99 seconds
Started	Sep 09 05:17:30 AM UTC 24
Finished	Sep 09 05:17:32 AM UTC 24
Peak memory	210968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791740290 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.791740290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1070488506
Short name	T94
Test name
Test status
Simulation time	93093574 ps
CPU time	2.19 seconds
Started	Sep 09 05:17:32 AM UTC 24
Finished	Sep 09 05:17:35 AM UTC 24
Peak memory	212412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070 488506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.1070488506
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3664859038
Short name	T67
Test name
Test status
Simulation time	266683004 ps
CPU time	4.41 seconds
Started	Sep 09 05:17:30 AM UTC 24
Finished	Sep 09 05:17:36 AM UTC 24
Peak memory	229376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3664859038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_ errors_with_csr_rw.3664859038
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.2262291532
Short name	T859
Test name
Test status
Simulation time	89163169 ps
CPU time	3.69 seconds
Started	Sep 09 05:17:30 AM UTC 24
Finished	Sep 09 05:17:35 AM UTC 24
Peak memory	212300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262291532 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.2262291532
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1693844471
Short name	T96
Test name
Test status
Simulation time	88406751 ps
CPU time	2.16 seconds
Started	Sep 09 05:17:35 AM UTC 24
Finished	Sep 09 05:17:38 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693844471 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.1693844471
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.445534190
Short name	T996
Test name
Test status
Simulation time	7912987306 ps
CPU time	28.05 seconds
Started	Sep 09 05:17:35 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	212668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445534190 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.445534190
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1485416137
Short name	T863
Test name
Test status
Simulation time	48256938 ps
CPU time	1.4 seconds
Started	Sep 09 05:17:35 AM UTC 24
Finished	Sep 09 05:17:37 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485416137 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.1485416137
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1822846333
Short name	T868
Test name
Test status
Simulation time	402567420 ps
CPU time	3.14 seconds
Started	Sep 09 05:17:37 AM UTC 24
Finished	Sep 09 05:17:41 AM UTC 24
Peak memory	212192 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1822846333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 1.clkmgr_csr_mem_rw_with_rand_reset.1822846333
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.3349068957
Short name	T95
Test name
Test status
Simulation time	55347656 ps
CPU time	1.3 seconds
Started	Sep 09 05:17:35 AM UTC 24
Finished	Sep 09 05:17:37 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349068957 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.3349068957
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.1875308645
Short name	T861
Test name
Test status
Simulation time	91415339 ps
CPU time	1.07 seconds
Started	Sep 09 05:17:35 AM UTC 24
Finished	Sep 09 05:17:37 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875308645 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.1875308645
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3952629131
Short name	T97
Test name
Test status
Simulation time	87725714 ps
CPU time	1.5 seconds
Started	Sep 09 05:17:36 AM UTC 24
Finished	Sep 09 05:17:39 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952 629131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.3952629131
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.3495746866
Short name	T68
Test name
Test status
Simulation time	275662957 ps
CPU time	2.5 seconds
Started	Sep 09 05:17:33 AM UTC 24
Finished	Sep 09 05:17:36 AM UTC 24
Peak memory	212348 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495746 866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.3495746866
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.559035045
Short name	T69
Test name
Test status
Simulation time	91060953 ps
CPU time	2.6 seconds
Started	Sep 09 05:17:33 AM UTC 24
Finished	Sep 09 05:17:36 AM UTC 24
Peak memory	222296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=559035045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_e rrors_with_csr_rw.559035045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.3400758947
Short name	T862
Test name
Test status
Simulation time	158375063 ps
CPU time	3.38 seconds
Started	Sep 09 05:17:33 AM UTC 24
Finished	Sep 09 05:17:37 AM UTC 24
Peak memory	212476 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400758947 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.3400758947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3321461248
Short name	T109
Test name
Test status
Simulation time	139338786 ps
CPU time	1.77 seconds
Started	Sep 09 05:17:34 AM UTC 24
Finished	Sep 09 05:17:37 AM UTC 24
Peak memory	211936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321461248 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.3321461248
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2368961325
Short name	T922
Test name
Test status
Simulation time	71568991 ps
CPU time	1.47 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2368961325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 10.clkmgr_csr_mem_rw_with_rand_reset.2368961325
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1845768876
Short name	T914
Test name
Test status
Simulation time	56399728 ps
CPU time	0.92 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845768876 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.1845768876
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.1995067259
Short name	T910
Test name
Test status
Simulation time	28935529 ps
CPU time	0.9 seconds
Started	Sep 09 05:17:50 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995067259 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.1995067259
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.323717226
Short name	T921
Test name
Test status
Simulation time	49129143 ps
CPU time	1.41 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237 17226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.323717226
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2445793243
Short name	T125
Test name
Test status
Simulation time	584874447 ps
CPU time	2.84 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	228692 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445793 243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.2445793243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.198921786
Short name	T140
Test name
Test status
Simulation time	100483824 ps
CPU time	1.99 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	221244 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=198921786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_ errors_with_csr_rw.198921786
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.252342457
Short name	T915
Test name
Test status
Simulation time	80838414 ps
CPU time	2.37 seconds
Started	Sep 09 05:17:50 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	212464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252342457 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.252342457
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.3006416158
Short name	T916
Test name
Test status
Simulation time	179990102 ps
CPU time	2.38 seconds
Started	Sep 09 05:17:50 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006416158 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.3006416158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3827603207
Short name	T924
Test name
Test status
Simulation time	154874275 ps
CPU time	1.6 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:54 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3827603207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 11.clkmgr_csr_mem_rw_with_rand_reset.3827603207
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.3667181520
Short name	T920
Test name
Test status
Simulation time	41359851 ps
CPU time	1.09 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667181520 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.3667181520
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.4293483957
Short name	T919
Test name
Test status
Simulation time	30281069 ps
CPU time	0.98 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293483957 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.4293483957
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2531415633
Short name	T923
Test name
Test status
Simulation time	33711744 ps
CPU time	1.36 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:54 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531 415633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.2531415633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1206844983
Short name	T134
Test name
Test status
Simulation time	1112318140 ps
CPU time	4.96 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	221980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1206844983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg _errors_with_csr_rw.1206844983
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.2902822174
Short name	T943
Test name
Test status
Simulation time	1375849644 ps
CPU time	5.59 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	212480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902822174 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.2902822174
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1356702535
Short name	T927
Test name
Test status
Simulation time	427592047 ps
CPU time	2.86 seconds
Started	Sep 09 05:17:51 AM UTC 24
Finished	Sep 09 05:17:55 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356702535 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.1356702535
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1424560660
Short name	T928
Test name
Test status
Simulation time	117321259 ps
CPU time	1.68 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1424560660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 12.clkmgr_csr_mem_rw_with_rand_reset.1424560660
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.3011391207
Short name	T926
Test name
Test status
Simulation time	21907326 ps
CPU time	1.05 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:55 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011391207 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.3011391207
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.1607367536
Short name	T925
Test name
Test status
Simulation time	16251945 ps
CPU time	0.91 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:55 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607367536 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.1607367536
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3134622612
Short name	T930
Test name
Test status
Simulation time	424762467 ps
CPU time	2.02 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	212388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134 622612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.3134622612
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.1015129423
Short name	T138
Test name
Test status
Simulation time	109757989 ps
CPU time	2.09 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	221976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015129 423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.1015129423
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2983867921
Short name	T133
Test name
Test status
Simulation time	148059001 ps
CPU time	3.64 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	221968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2983867921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg _errors_with_csr_rw.2983867921
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.2560244584
Short name	T931
Test name
Test status
Simulation time	76451754 ps
CPU time	2.23 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	212464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560244584 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.2560244584
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2350014826
Short name	T929
Test name
Test status
Simulation time	68584198 ps
CPU time	2.01 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	211956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350014826 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.2350014826
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.681182469
Short name	T939
Test name
Test status
Simulation time	118487799 ps
CPU time	1.42 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=681182469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.clkmgr_csr_mem_rw_with_rand_reset.681182469
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.614678226
Short name	T934
Test name
Test status
Simulation time	15885861 ps
CPU time	1.04 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614678226 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.614678226
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.486242094
Short name	T932
Test name
Test status
Simulation time	14303315 ps
CPU time	0.69 seconds
Started	Sep 09 05:17:54 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486242094 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.486242094
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1654780827
Short name	T938
Test name
Test status
Simulation time	49731152 ps
CPU time	1.39 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654 780827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.1654780827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3502057621
Short name	T137
Test name
Test status
Simulation time	176207194 ps
CPU time	1.82 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502057 621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.3502057621
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.4243065970
Short name	T127
Test name
Test status
Simulation time	143313596 ps
CPU time	1.7 seconds
Started	Sep 09 05:17:53 AM UTC 24
Finished	Sep 09 05:17:56 AM UTC 24
Peak memory	221188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=4243065970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg _errors_with_csr_rw.4243065970
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.2171394249
Short name	T936
Test name
Test status
Simulation time	46060331 ps
CPU time	1.46 seconds
Started	Sep 09 05:17:54 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171394249 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.2171394249
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3660075161
Short name	T941
Test name
Test status
Simulation time	139686863 ps
CPU time	1.89 seconds
Started	Sep 09 05:17:54 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660075161 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.3660075161
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4192156986
Short name	T940
Test name
Test status
Simulation time	22868981 ps
CPU time	1.15 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=4192156986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 14.clkmgr_csr_mem_rw_with_rand_reset.4192156986
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.3656411010
Short name	T937
Test name
Test status
Simulation time	62345825 ps
CPU time	1.07 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656411010 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.3656411010
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.744693982
Short name	T935
Test name
Test status
Simulation time	34936663 ps
CPU time	0.78 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744693982 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.744693982
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3625188137
Short name	T944
Test name
Test status
Simulation time	102008679 ps
CPU time	1.82 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	211940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625 188137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.3625188137
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1653596857
Short name	T945
Test name
Test status
Simulation time	108190520 ps
CPU time	2.35 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	212952 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1653596857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg _errors_with_csr_rw.1653596857
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.2129202545
Short name	T942
Test name
Test status
Simulation time	92558715 ps
CPU time	1.89 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	211576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129202545 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.2129202545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.4044568441
Short name	T117
Test name
Test status
Simulation time	233972396 ps
CPU time	3.03 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	211976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044568441 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.4044568441
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2266065895
Short name	T950
Test name
Test status
Simulation time	139604417 ps
CPU time	1.46 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2266065895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 15.clkmgr_csr_mem_rw_with_rand_reset.2266065895
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.3239181593
Short name	T952
Test name
Test status
Simulation time	207465311 ps
CPU time	1.62 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	212044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239181593 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.3239181593
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.2731856695
Short name	T947
Test name
Test status
Simulation time	12150322 ps
CPU time	0.87 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2731856695 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.2731856695
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3514022638
Short name	T948
Test name
Test status
Simulation time	24237354 ps
CPU time	1.1 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514 022638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.3514022638
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.4161071899
Short name	T946
Test name
Test status
Simulation time	228554064 ps
CPU time	2.26 seconds
Started	Sep 09 05:17:55 AM UTC 24
Finished	Sep 09 05:17:58 AM UTC 24
Peak memory	212748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161071 899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.4161071899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.560338758
Short name	T953
Test name
Test status
Simulation time	194885599 ps
CPU time	1.87 seconds
Started	Sep 09 05:17:56 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	220768 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=560338758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_ errors_with_csr_rw.560338758
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.2427927464
Short name	T951
Test name
Test status
Simulation time	154963979 ps
CPU time	1.7 seconds
Started	Sep 09 05:17:56 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427927464 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.2427927464
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.4138034096
Short name	T960
Test name
Test status
Simulation time	353322095 ps
CPU time	2.95 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:18:00 AM UTC 24
Peak memory	212744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138034096 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.4138034096
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2481880034
Short name	T967
Test name
Test status
Simulation time	340578775 ps
CPU time	2.09 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	212472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2481880034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 16.clkmgr_csr_mem_rw_with_rand_reset.2481880034
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.2413607484
Short name	T958
Test name
Test status
Simulation time	44858024 ps
CPU time	0.93 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:00 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413607484 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.2413607484
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.453992593
Short name	T954
Test name
Test status
Simulation time	31066123 ps
CPU time	0.72 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:00 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453992593 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.453992593
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.606631347
Short name	T961
Test name
Test status
Simulation time	81313019 ps
CPU time	1.27 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6066 31347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.606631347
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.495242818
Short name	T949
Test name
Test status
Simulation time	72516103 ps
CPU time	1.26 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4952428 18 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.495242818
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2489793568
Short name	T955
Test name
Test status
Simulation time	88088032 ps
CPU time	2.16 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:18:00 AM UTC 24
Peak memory	222280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2489793568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg _errors_with_csr_rw.2489793568
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.3046465743
Short name	T957
Test name
Test status
Simulation time	86964647 ps
CPU time	2.27 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:18:00 AM UTC 24
Peak memory	212720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046465743 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.3046465743
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3282853643
Short name	T114
Test name
Test status
Simulation time	49073825 ps
CPU time	1.44 seconds
Started	Sep 09 05:17:57 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	211876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282853643 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.3282853643
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3453487575
Short name	T963
Test name
Test status
Simulation time	25211405 ps
CPU time	1.05 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3453487575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 17.clkmgr_csr_mem_rw_with_rand_reset.3453487575
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.3757717061
Short name	T962
Test name
Test status
Simulation time	37715644 ps
CPU time	0.98 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757717061 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.3757717061
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.213652984
Short name	T959
Test name
Test status
Simulation time	13225824 ps
CPU time	0.75 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:00 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213652984 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.213652984
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3637557292
Short name	T964
Test name
Test status
Simulation time	144959138 ps
CPU time	1.45 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637 557292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.3637557292
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.90856578
Short name	T135
Test name
Test status
Simulation time	194827731 ps
CPU time	2.25 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	221968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9085657 8 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.90856578
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.969544721
Short name	T965
Test name
Test status
Simulation time	86951409 ps
CPU time	1.76 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=969544721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_ errors_with_csr_rw.969544721
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.2231362983
Short name	T956
Test name
Test status
Simulation time	51195628 ps
CPU time	1.71 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211732 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2231362983 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.2231362983
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1905474116
Short name	T968
Test name
Test status
Simulation time	151123478 ps
CPU time	2.3 seconds
Started	Sep 09 05:17:58 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	212612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905474116 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.1905474116
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.821019649
Short name	T973
Test name
Test status
Simulation time	40023914 ps
CPU time	1.17 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=821019649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.clkmgr_csr_mem_rw_with_rand_reset.821019649
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.1001996772
Short name	T933
Test name
Test status
Simulation time	15983932 ps
CPU time	1.05 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	211804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001996772 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.1001996772
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.2311697051
Short name	T971
Test name
Test status
Simulation time	56304209 ps
CPU time	0.83 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311697051 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.2311697051
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3084836845
Short name	T977
Test name
Test status
Simulation time	135678499 ps
CPU time	1.45 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3084 836845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.3084836845
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.433885774
Short name	T966
Test name
Test status
Simulation time	96598082 ps
CPU time	1.45 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:01 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4338857 74 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.433885774
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1233849193
Short name	T969
Test name
Test status
Simulation time	235177363 ps
CPU time	2.04 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	221976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1233849193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg _errors_with_csr_rw.1233849193
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.1127183967
Short name	T970
Test name
Test status
Simulation time	90274178 ps
CPU time	2.17 seconds
Started	Sep 09 05:17:59 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	212480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127183967 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.1127183967
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.929475919
Short name	T979
Test name
Test status
Simulation time	50972232 ps
CPU time	1.17 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=929475919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.clkmgr_csr_mem_rw_with_rand_reset.929475919
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.508037703
Short name	T975
Test name
Test status
Simulation time	24499719 ps
CPU time	0.95 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508037703 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.508037703
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.755800552
Short name	T972
Test name
Test status
Simulation time	34547193 ps
CPU time	0.89 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755800552 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.755800552
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3785930828
Short name	T978
Test name
Test status
Simulation time	77731546 ps
CPU time	1.11 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785 930828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.3785930828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1628465190
Short name	T136
Test name
Test status
Simulation time	66637478 ps
CPU time	1.38 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628465 190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.1628465190
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3571529517
Short name	T981
Test name
Test status
Simulation time	62584336 ps
CPU time	1.77 seconds
Started	Sep 09 05:18:00 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211628 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3571529517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg _errors_with_csr_rw.3571529517
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.1571354163
Short name	T982
Test name
Test status
Simulation time	128092313 ps
CPU time	2.34 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	212464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571354163 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.1571354163
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3445975836
Short name	T869
Test name
Test status
Simulation time	32600948 ps
CPU time	2.09 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:41 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445975836 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.3445975836
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.249678242
Short name	T886
Test name
Test status
Simulation time	351004034 ps
CPU time	6.58 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	212484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249678242 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.249678242
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3613545796
Short name	T865
Test name
Test status
Simulation time	36480532 ps
CPU time	1.01 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:40 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613545796 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.3613545796
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.821693552
Short name	T867
Test name
Test status
Simulation time	110443236 ps
CPU time	1.46 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:41 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=821693552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.clkmgr_csr_mem_rw_with_rand_reset.821693552
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.3861952151
Short name	T866
Test name
Test status
Simulation time	19644222 ps
CPU time	1.29 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:40 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861952151 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.3861952151
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.444387968
Short name	T864
Test name
Test status
Simulation time	12538158 ps
CPU time	1.04 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:40 AM UTC 24
Peak memory	211420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444387968 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.444387968
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3566319354
Short name	T98
Test name
Test status
Simulation time	88888911 ps
CPU time	1.41 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:41 AM UTC 24
Peak memory	212040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566 319354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.3566319354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2783258213
Short name	T75
Test name
Test status
Simulation time	235200109 ps
CPU time	2.76 seconds
Started	Sep 09 05:17:37 AM UTC 24
Finished	Sep 09 05:17:40 AM UTC 24
Peak memory	229092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2783258213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_ errors_with_csr_rw.2783258213
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.77431888
Short name	T874
Test name
Test status
Simulation time	381444202 ps
CPU time	4.74 seconds
Started	Sep 09 05:17:37 AM UTC 24
Finished	Sep 09 05:17:42 AM UTC 24
Peak memory	212460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77431888 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.77431888
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.2533448035
Short name	T110
Test name
Test status
Simulation time	83259137 ps
CPU time	2.05 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:41 AM UTC 24
Peak memory	212408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533448035 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.2533448035
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.4086086574
Short name	T976
Test name
Test status
Simulation time	11580138 ps
CPU time	0.92 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4086086574 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.4086086574
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.3882157231
Short name	T974
Test name
Test status
Simulation time	28262969 ps
CPU time	0.81 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882157231 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.3882157231
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.1665134123
Short name	T980
Test name
Test status
Simulation time	84798892 ps
CPU time	1.06 seconds
Started	Sep 09 05:18:01 AM UTC 24
Finished	Sep 09 05:18:03 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665134123 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.1665134123
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.2254469471
Short name	T984
Test name
Test status
Simulation time	49919831 ps
CPU time	0.7 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254469471 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.2254469471
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.3033572947
Short name	T989
Test name
Test status
Simulation time	99981101 ps
CPU time	0.94 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033572947 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.3033572947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.2164612344
Short name	T983
Test name
Test status
Simulation time	30494314 ps
CPU time	0.68 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164612344 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.2164612344
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.422933134
Short name	T985
Test name
Test status
Simulation time	32071240 ps
CPU time	0.74 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422933134 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.422933134
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.2760000658
Short name	T988
Test name
Test status
Simulation time	14422059 ps
CPU time	0.74 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760000658 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.2760000658
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.1910350572
Short name	T994
Test name
Test status
Simulation time	66103070 ps
CPU time	0.89 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910350572 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.1910350572
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.3721532034
Short name	T986
Test name
Test status
Simulation time	28086820 ps
CPU time	0.69 seconds
Started	Sep 09 05:18:02 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721532034 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.3721532034
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2277678751
Short name	T876
Test name
Test status
Simulation time	139597069 ps
CPU time	1.95 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	211940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277678751 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.2277678751
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.111678060
Short name	T908
Test name
Test status
Simulation time	738119273 ps
CPU time	10.17 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:51 AM UTC 24
Peak memory	212252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111678060 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.111678060
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.391110629
Short name	T870
Test name
Test status
Simulation time	15023953 ps
CPU time	0.91 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:41 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391110629 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.391110629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.379498360
Short name	T880
Test name
Test status
Simulation time	101254628 ps
CPU time	1.43 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	211736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=379498360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.clkmgr_csr_mem_rw_with_rand_reset.379498360
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.3146085436
Short name	T871
Test name
Test status
Simulation time	43985109 ps
CPU time	1.27 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:42 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146085436 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.3146085436
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.4080358949
Short name	T873
Test name
Test status
Simulation time	94797808 ps
CPU time	1.42 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:42 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080358949 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.4080358949
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.303988630
Short name	T872
Test name
Test status
Simulation time	29747883 ps
CPU time	1.11 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:42 AM UTC 24
Peak memory	211812 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039 88630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.303988630
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1196795021
Short name	T71
Test name
Test status
Simulation time	81718226 ps
CPU time	2.66 seconds
Started	Sep 09 05:17:38 AM UTC 24
Finished	Sep 09 05:17:42 AM UTC 24
Peak memory	228848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196795 021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.1196795021
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.2060515063
Short name	T884
Test name
Test status
Simulation time	488620367 ps
CPU time	4.78 seconds
Started	Sep 09 05:17:40 AM UTC 24
Finished	Sep 09 05:17:45 AM UTC 24
Peak memory	212640 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060515063 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.2060515063
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.2380448918
Short name	T992
Test name
Test status
Simulation time	22681851 ps
CPU time	0.67 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380448918 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.2380448918
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.1842774359
Short name	T987
Test name
Test status
Simulation time	30527117 ps
CPU time	0.67 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842774359 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.1842774359
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.4193235002
Short name	T991
Test name
Test status
Simulation time	13217253 ps
CPU time	0.64 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193235002 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.4193235002
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.2909156802
Short name	T993
Test name
Test status
Simulation time	13119423 ps
CPU time	0.66 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909156802 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.2909156802
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.261253325
Short name	T990
Test name
Test status
Simulation time	28126898 ps
CPU time	0.65 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261253325 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.261253325
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.4177703294
Short name	T997
Test name
Test status
Simulation time	37348752 ps
CPU time	0.65 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177703294 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.4177703294
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.166555367
Short name	T995
Test name
Test status
Simulation time	46420931 ps
CPU time	0.69 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:04 AM UTC 24
Peak memory	211552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166555367 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.166555367
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.2777855596
Short name	T999
Test name
Test status
Simulation time	20776927 ps
CPU time	0.72 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:05 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777855596 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.2777855596
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.1746308459
Short name	T998
Test name
Test status
Simulation time	11496078 ps
CPU time	0.61 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:05 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746308459 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.1746308459
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.2133420309
Short name	T1000
Test name
Test status
Simulation time	32130786 ps
CPU time	0.66 seconds
Started	Sep 09 05:18:03 AM UTC 24
Finished	Sep 09 05:18:05 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133420309 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.2133420309
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1505120206
Short name	T882
Test name
Test status
Simulation time	35746050 ps
CPU time	1.28 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:45 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505120206 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.1505120206
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2846895348
Short name	T918
Test name
Test status
Simulation time	1423871097 ps
CPU time	9.48 seconds
Started	Sep 09 05:17:42 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	212472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846895348 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.2846895348
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2279713485
Short name	T879
Test name
Test status
Simulation time	25195714 ps
CPU time	1.05 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	211684 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279713485 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.2279713485
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1685489280
Short name	T885
Test name
Test status
Simulation time	108011406 ps
CPU time	1.98 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	211956 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=1685489280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 4.clkmgr_csr_mem_rw_with_rand_reset.1685489280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.225264643
Short name	T883
Test name
Test status
Simulation time	50792155 ps
CPU time	1.33 seconds
Started	Sep 09 05:17:42 AM UTC 24
Finished	Sep 09 05:17:45 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225264643 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.225264643
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.2568267032
Short name	T878
Test name
Test status
Simulation time	13993865 ps
CPU time	0.86 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568267032 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.2568267032
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1195657052
Short name	T881
Test name
Test status
Simulation time	38140655 ps
CPU time	1.1 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:45 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195 657052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.1195657052
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.778179102
Short name	T74
Test name
Test status
Simulation time	92197360 ps
CPU time	1.66 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:44 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7781791 02 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.778179102
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1474548316
Short name	T131
Test name
Test status
Simulation time	101168141 ps
CPU time	2.2 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:44 AM UTC 24
Peak memory	229148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1474548316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_ errors_with_csr_rw.1474548316
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.204791741
Short name	T892
Test name
Test status
Simulation time	512736966 ps
CPU time	4.64 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:47 AM UTC 24
Peak memory	212484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204791741 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.204791741
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2950924876
Short name	T178
Test name
Test status
Simulation time	214431022 ps
CPU time	2.8 seconds
Started	Sep 09 05:17:41 AM UTC 24
Finished	Sep 09 05:17:45 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950924876 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.2950924876
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.4100364089
Short name	T1001
Test name
Test status
Simulation time	12860030 ps
CPU time	0.69 seconds
Started	Sep 09 05:18:04 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100364089 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.4100364089
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.4172072395
Short name	T1002
Test name
Test status
Simulation time	23204396 ps
CPU time	0.72 seconds
Started	Sep 09 05:18:04 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172072395 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.4172072395
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.1881711815
Short name	T1003
Test name
Test status
Simulation time	18123649 ps
CPU time	0.64 seconds
Started	Sep 09 05:18:04 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881711815 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.1881711815
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.88767754
Short name	T1004
Test name
Test status
Simulation time	42161257 ps
CPU time	0.71 seconds
Started	Sep 09 05:18:04 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88767754 -assert nopostpr oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.88767754
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.2859006131
Short name	T1007
Test name
Test status
Simulation time	21802797 ps
CPU time	0.68 seconds
Started	Sep 09 05:18:04 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859006131 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.2859006131
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.3716676535
Short name	T1005
Test name
Test status
Simulation time	19472345 ps
CPU time	0.68 seconds
Started	Sep 09 05:18:04 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3716676535 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.3716676535
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.893185084
Short name	T1006
Test name
Test status
Simulation time	11541641 ps
CPU time	0.66 seconds
Started	Sep 09 05:18:05 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893185084 -assert nopostp roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.893185084
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.4145569388
Short name	T1009
Test name
Test status
Simulation time	17142836 ps
CPU time	0.63 seconds
Started	Sep 09 05:18:05 AM UTC 24
Finished	Sep 09 05:18:19 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145569388 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.4145569388
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.2014181073
Short name	T1008
Test name
Test status
Simulation time	26865055 ps
CPU time	0.68 seconds
Started	Sep 09 05:18:05 AM UTC 24
Finished	Sep 09 05:18:09 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014181073 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.2014181073
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.3298523535
Short name	T1010
Test name
Test status
Simulation time	13360280 ps
CPU time	0.64 seconds
Started	Sep 09 05:18:05 AM UTC 24
Finished	Sep 09 05:18:19 AM UTC 24
Peak memory	211484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298523535 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.3298523535
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2694242648
Short name	T896
Test name
Test status
Simulation time	157268005 ps
CPU time	2.36 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	228152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2694242648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 5.clkmgr_csr_mem_rw_with_rand_reset.2694242648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.2729171765
Short name	T890
Test name
Test status
Simulation time	54403675 ps
CPU time	1.36 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	211752 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729171765 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.2729171765
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.4092017559
Short name	T887
Test name
Test status
Simulation time	12752145 ps
CPU time	0.77 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092017559 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.4092017559
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1722368519
Short name	T897
Test name
Test status
Simulation time	266771351 ps
CPU time	2.66 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	212336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722 368519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.1722368519
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2897384547
Short name	T128
Test name
Test status
Simulation time	155517493 ps
CPU time	1.86 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897384 547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.2897384547
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.523935322
Short name	T132
Test name
Test status
Simulation time	96866092 ps
CPU time	2.05 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	221940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=523935322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_e rrors_with_csr_rw.523935322
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.1596884026
Short name	T888
Test name
Test status
Simulation time	181581049 ps
CPU time	2.37 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	212472 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596884026 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.1596884026
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1696072087
Short name	T181
Test name
Test status
Simulation time	4225998173 ps
CPU time	12.57 seconds
Started	Sep 09 05:17:43 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	212416 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696072087 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.1696072087
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2770612714
Short name	T899
Test name
Test status
Simulation time	83081469 ps
CPU time	1.39 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2770612714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 6.clkmgr_csr_mem_rw_with_rand_reset.2770612714
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.1581456087
Short name	T889
Test name
Test status
Simulation time	15737081 ps
CPU time	0.87 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	211992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581456087 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.1581456087
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.1890686151
Short name	T891
Test name
Test status
Simulation time	16229865 ps
CPU time	1.01 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:46 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890686151 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.1890686151
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2732218070
Short name	T893
Test name
Test status
Simulation time	92012871 ps
CPU time	1.44 seconds
Started	Sep 09 05:17:45 AM UTC 24
Finished	Sep 09 05:17:47 AM UTC 24
Peak memory	211860 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732 218070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.2732218070
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2861934386
Short name	T73
Test name
Test status
Simulation time	121842534 ps
CPU time	2.92 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	228944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861934 386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.2861934386
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3008336862
Short name	T141
Test name
Test status
Simulation time	129094727 ps
CPU time	2.62 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	221964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=3008336862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_ errors_with_csr_rw.3008336862
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.3832130283
Short name	T894
Test name
Test status
Simulation time	150192576 ps
CPU time	1.98 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:47 AM UTC 24
Peak memory	211992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832130283 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.3832130283
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1477203540
Short name	T180
Test name
Test status
Simulation time	144698411 ps
CPU time	2.84 seconds
Started	Sep 09 05:17:44 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477203540 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.1477203540
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2223879698
Short name	T903
Test name
Test status
Simulation time	30773405 ps
CPU time	1.16 seconds
Started	Sep 09 05:17:47 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=2223879698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 7.clkmgr_csr_mem_rw_with_rand_reset.2223879698
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.2396550540
Short name	T898
Test name
Test status
Simulation time	35512983 ps
CPU time	0.87 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	212052 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396550540 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.2396550540
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.1594242728
Short name	T875
Test name
Test status
Simulation time	11019393 ps
CPU time	0.92 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	211536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594242728 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.1594242728
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1137886397
Short name	T900
Test name
Test status
Simulation time	32639681 ps
CPU time	1.41 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:49 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137 886397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.1137886397
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.238320427
Short name	T139
Test name
Test status
Simulation time	218618457 ps
CPU time	2.48 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:49 AM UTC 24
Peak memory	212816 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383204 27 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works paces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.238320427
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1702489784
Short name	T901
Test name
Test status
Simulation time	213769779 ps
CPU time	2.56 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:49 AM UTC 24
Peak memory	222044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=1702489784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_ errors_with_csr_rw.1702489784
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.2876272588
Short name	T905
Test name
Test status
Simulation time	296250865 ps
CPU time	2.88 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	212400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876272588 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.2876272588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.115750855
Short name	T179
Test name
Test status
Simulation time	69960585 ps
CPU time	2.19 seconds
Started	Sep 09 05:17:46 AM UTC 24
Finished	Sep 09 05:17:49 AM UTC 24
Peak memory	212536 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115750855 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.115750855
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3645127587
Short name	T907
Test name
Test status
Simulation time	131670539 ps
CPU time	1.46 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	211800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3645127587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 8.clkmgr_csr_mem_rw_with_rand_reset.3645127587
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.235776207
Short name	T904
Test name
Test status
Simulation time	86108968 ps
CPU time	1.02 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	211748 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235776207 -assert nopo stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.235776207
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.2545658841
Short name	T902
Test name
Test status
Simulation time	25023777 ps
CPU time	0.99 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545658841 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.2545658841
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3227664109
Short name	T906
Test name
Test status
Simulation time	31704491 ps
CPU time	1.4 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	211680 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227 664109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.3227664109
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2197254680
Short name	T122
Test name
Test status
Simulation time	91007887 ps
CPU time	2.24 seconds
Started	Sep 09 05:17:47 AM UTC 24
Finished	Sep 09 05:17:51 AM UTC 24
Peak memory	221976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197254 680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.2197254680
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2865213886
Short name	T123
Test name
Test status
Simulation time	435366944 ps
CPU time	3.73 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	222292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2865213886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_ errors_with_csr_rw.2865213886
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.2746079380
Short name	T913
Test name
Test status
Simulation time	191836717 ps
CPU time	3.29 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	212588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746079380 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.2746079380
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2282338787
Short name	T113
Test name
Test status
Simulation time	368958725 ps
CPU time	3.29 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	212424 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282338787 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.2282338787
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3520887925
Short name	T911
Test name
Test status
Simulation time	92244328 ps
CPU time	1.21 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	211792 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/ tools/sim.tcl +ntb_random_seed=3520887925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm _name 9.clkmgr_csr_mem_rw_with_rand_reset.3520887925
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.2558384789
Short name	T895
Test name
Test status
Simulation time	21193712 ps
CPU time	0.78 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:51 AM UTC 24
Peak memory	211928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558384789 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.2558384789
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.1074467592
Short name	T909
Test name
Test status
Simulation time	11772878 ps
CPU time	0.74 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:51 AM UTC 24
Peak memory	211548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074467592 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.1074467592
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.258200749
Short name	T912
Test name
Test status
Simulation time	91022706 ps
CPU time	1.56 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	211948 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582 00749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.258200749
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3401311964
Short name	T129
Test name
Test status
Simulation time	65164447 ps
CPU time	1.18 seconds
Started	Sep 09 05:17:48 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	211688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401311 964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work spaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.3401311964
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.2187078947
Short name	T124
Test name
Test status
Simulation time	96008737 ps
CPU time	2.7 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	212576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_ seed=2187078947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_ errors_with_csr_rw.2187078947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.2704615425
Short name	T917
Test name
Test status
Simulation time	191526992 ps
CPU time	2.77 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:53 AM UTC 24
Peak memory	212376 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704615425 -assert nopost proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.2704615425
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3629431747
Short name	T115
Test name
Test status
Simulation time	56213109 ps
CPU time	1.6 seconds
Started	Sep 09 05:17:49 AM UTC 24
Finished	Sep 09 05:17:52 AM UTC 24
Peak memory	211896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629431747 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.3629431747
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.842468686
Short name	T30
Test name
Test status
Simulation time	43673303 ps
CPU time	1.27 seconds
Started	Sep 09 05:12:59 AM UTC 24
Finished	Sep 09 05:13:01 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842468686 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.842468686
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.3954659516
Short name	T28
Test name
Test status
Simulation time	2311383458 ps
CPU time	24.46 seconds
Started	Sep 09 05:12:56 AM UTC 24
Finished	Sep 09 05:13:22 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954659516 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.3954659516
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.317140582
Short name	T31
Test name
Test status
Simulation time	88016144 ps
CPU time	1.71 seconds
Started	Sep 09 05:13:00 AM UTC 24
Finished	Sep 09 05:13:02 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317140582 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.317140582
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1487044407
Short name	T33
Test name
Test status
Simulation time	20246242 ps
CPU time	1.33 seconds
Started	Sep 09 05:13:02 AM UTC 24
Finished	Sep 09 05:13:04 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487044407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.1487044407
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.232320616
Short name	T6
Test name
Test status
Simulation time	17302210 ps
CPU time	1.17 seconds
Started	Sep 09 05:12:57 AM UTC 24
Finished	Sep 09 05:12:59 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232320616 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.232320616
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.1949855354
Short name	T45
Test name
Test status
Simulation time	315508313 ps
CPU time	5.66 seconds
Started	Sep 09 05:13:04 AM UTC 24
Finished	Sep 09 05:13:11 AM UTC 24
Peak memory	242876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949855354 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.1949855354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.1954954194
Short name	T4
Test name
Test status
Simulation time	40059412 ps
CPU time	1.5 seconds
Started	Sep 09 05:12:53 AM UTC 24
Finished	Sep 09 05:12:56 AM UTC 24
Peak memory	209648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954954194 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1954954194
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.2541073642
Short name	T13
Test name
Test status
Simulation time	8797849292 ps
CPU time	46.28 seconds
Started	Sep 09 05:13:04 AM UTC 24
Finished	Sep 09 05:13:52 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2541073642 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.2541073642
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.516965180
Short name	T29
Test name
Test status
Simulation time	15724814 ps
CPU time	1.13 seconds
Started	Sep 09 05:12:58 AM UTC 24
Finished	Sep 09 05:13:00 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516965180 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.516965180
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.3803629293
Short name	T22
Test name
Test status
Simulation time	16254268 ps
CPU time	1.18 seconds
Started	Sep 09 05:13:16 AM UTC 24
Finished	Sep 09 05:13:19 AM UTC 24
Peak memory	210088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803629293 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.3803629293
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1775524852
Short name	T21
Test name
Test status
Simulation time	144453004 ps
CPU time	2.27 seconds
Started	Sep 09 05:13:12 AM UTC 24
Finished	Sep 09 05:13:15 AM UTC 24
Peak memory	210308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775524852 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.1775524852
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.293735603
Short name	T19
Test name
Test status
Simulation time	92639369 ps
CPU time	1.75 seconds
Started	Sep 09 05:13:12 AM UTC 24
Finished	Sep 09 05:13:15 AM UTC 24
Peak memory	209132 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293735603 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.293735603
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.3650887961
Short name	T76
Test name
Test status
Simulation time	30398207 ps
CPU time	0.9 seconds
Started	Sep 09 05:13:05 AM UTC 24
Finished	Sep 09 05:13:07 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3650887961 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3650887961
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.3206664841
Short name	T3
Test name
Test status
Simulation time	863372738 ps
CPU time	9.89 seconds
Started	Sep 09 05:13:08 AM UTC 24
Finished	Sep 09 05:13:19 AM UTC 24
Peak memory	210656 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206664841 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.3206664841
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1553218976
Short name	T49
Test name
Test status
Simulation time	13049499 ps
CPU time	1.14 seconds
Started	Sep 09 05:13:12 AM UTC 24
Finished	Sep 09 05:13:14 AM UTC 24
Peak memory	210252 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553218976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.1553218976
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1890863969
Short name	T20
Test name
Test status
Simulation time	219815337 ps
CPU time	2.3 seconds
Started	Sep 09 05:13:12 AM UTC 24
Finished	Sep 09 05:13:15 AM UTC 24
Peak memory	210064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890863969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.1890863969
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.2768598659
Short name	T44
Test name
Test status
Simulation time	31667424 ps
CPU time	1.16 seconds
Started	Sep 09 05:13:09 AM UTC 24
Finished	Sep 09 05:13:11 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768598659 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2768598659
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.1004914572
Short name	T57
Test name
Test status
Simulation time	15639484 ps
CPU time	1.23 seconds
Started	Sep 09 05:13:05 AM UTC 24
Finished	Sep 09 05:13:08 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004914572 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1004914572
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.3359869901
Short name	T25
Test name
Test status
Simulation time	366615000 ps
CPU time	3.66 seconds
Started	Sep 09 05:13:15 AM UTC 24
Finished	Sep 09 05:13:20 AM UTC 24
Peak memory	210488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359869901 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.3359869901
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.1209724638
Short name	T54
Test name
Test status
Simulation time	1220782603 ps
CPU time	20.3 seconds
Started	Sep 09 05:13:15 AM UTC 24
Finished	Sep 09 05:13:37 AM UTC 24
Peak memory	220356 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209724638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.1209724638
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.2639655152
Short name	T47
Test name
Test status
Simulation time	30149946 ps
CPU time	1.5 seconds
Started	Sep 09 05:13:09 AM UTC 24
Finished	Sep 09 05:13:11 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639655152 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2639655152
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.3699935484
Short name	T263
Test name
Test status
Simulation time	95225087 ps
CPU time	1.5 seconds
Started	Sep 09 05:14:09 AM UTC 24
Finished	Sep 09 05:14:12 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699935484 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.3699935484
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2367244874
Short name	T103
Test name
Test status
Simulation time	26652444 ps
CPU time	1.42 seconds
Started	Sep 09 05:14:07 AM UTC 24
Finished	Sep 09 05:14:10 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367244874 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.2367244874
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.2794958682
Short name	T254
Test name
Test status
Simulation time	34078406 ps
CPU time	1.16 seconds
Started	Sep 09 05:14:06 AM UTC 24
Finished	Sep 09 05:14:08 AM UTC 24
Peak memory	209980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794958682 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2794958682
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.2478059067
Short name	T259
Test name
Test status
Simulation time	25356443 ps
CPU time	1.2 seconds
Started	Sep 09 05:14:07 AM UTC 24
Finished	Sep 09 05:14:09 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478059067 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.2478059067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.1659316509
Short name	T252
Test name
Test status
Simulation time	70077858 ps
CPU time	1.54 seconds
Started	Sep 09 05:14:05 AM UTC 24
Finished	Sep 09 05:14:07 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659316509 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1659316509
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.1504169071
Short name	T39
Test name
Test status
Simulation time	800624280 ps
CPU time	7.28 seconds
Started	Sep 09 05:14:05 AM UTC 24
Finished	Sep 09 05:14:13 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504169071 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1504169071
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.3250414337
Short name	T261
Test name
Test status
Simulation time	527288601 ps
CPU time	5.03 seconds
Started	Sep 09 05:14:05 AM UTC 24
Finished	Sep 09 05:14:11 AM UTC 24
Peak memory	210652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250414337 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.3250414337
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.2607811806
Short name	T256
Test name
Test status
Simulation time	93212836 ps
CPU time	1.74 seconds
Started	Sep 09 05:14:06 AM UTC 24
Finished	Sep 09 05:14:09 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607811806 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.2607811806
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3570865601
Short name	T258
Test name
Test status
Simulation time	20668584 ps
CPU time	1.22 seconds
Started	Sep 09 05:14:07 AM UTC 24
Finished	Sep 09 05:14:09 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570865601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.3570865601
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2447031436
Short name	T257
Test name
Test status
Simulation time	16529316 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:07 AM UTC 24
Finished	Sep 09 05:14:09 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447031436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.2447031436
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.1119883985
Short name	T255
Test name
Test status
Simulation time	54504398 ps
CPU time	1.34 seconds
Started	Sep 09 05:14:06 AM UTC 24
Finished	Sep 09 05:14:08 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119883985 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.1119883985
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.541085354
Short name	T272
Test name
Test status
Simulation time	1216814978 ps
CPU time	5.07 seconds
Started	Sep 09 05:14:08 AM UTC 24
Finished	Sep 09 05:14:15 AM UTC 24
Peak memory	210616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541085354 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.541085354
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.866038631
Short name	T249
Test name
Test status
Simulation time	14593027 ps
CPU time	1.14 seconds
Started	Sep 09 05:14:05 AM UTC 24
Finished	Sep 09 05:14:07 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866038631 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.866038631
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.1093930070
Short name	T486
Test name
Test status
Simulation time	11113193235 ps
CPU time	91.47 seconds
Started	Sep 09 05:14:08 AM UTC 24
Finished	Sep 09 05:15:42 AM UTC 24
Peak memory	224624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093930070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.1093930070
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.3317181961
Short name	T253
Test name
Test status
Simulation time	37406845 ps
CPU time	1.19 seconds
Started	Sep 09 05:14:06 AM UTC 24
Finished	Sep 09 05:14:08 AM UTC 24
Peak memory	210444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317181961 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.3317181961
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.42093464
Short name	T275
Test name
Test status
Simulation time	44869855 ps
CPU time	1.22 seconds
Started	Sep 09 05:14:14 AM UTC 24
Finished	Sep 09 05:14:17 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42093464 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.42093464
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2172218908
Short name	T270
Test name
Test status
Simulation time	12023965 ps
CPU time	1.11 seconds
Started	Sep 09 05:14:12 AM UTC 24
Finished	Sep 09 05:14:14 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172218908 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.2172218908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.1739342390
Short name	T267
Test name
Test status
Simulation time	12753089 ps
CPU time	1.1 seconds
Started	Sep 09 05:14:11 AM UTC 24
Finished	Sep 09 05:14:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739342390 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.1739342390
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.2207088915
Short name	T273
Test name
Test status
Simulation time	16707306 ps
CPU time	1.21 seconds
Started	Sep 09 05:14:12 AM UTC 24
Finished	Sep 09 05:14:15 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207088915 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.2207088915
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.2949594999
Short name	T264
Test name
Test status
Simulation time	41308415 ps
CPU time	1.5 seconds
Started	Sep 09 05:14:10 AM UTC 24
Finished	Sep 09 05:14:12 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949594999 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2949594999
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.3593844576
Short name	T37
Test name
Test status
Simulation time	1714464271 ps
CPU time	9.03 seconds
Started	Sep 09 05:14:10 AM UTC 24
Finished	Sep 09 05:14:20 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593844576 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3593844576
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.3433436391
Short name	T285
Test name
Test status
Simulation time	1217031993 ps
CPU time	10.6 seconds
Started	Sep 09 05:14:10 AM UTC 24
Finished	Sep 09 05:14:21 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433436391 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.3433436391
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.1610903628
Short name	T266
Test name
Test status
Simulation time	20200223 ps
CPU time	1.16 seconds
Started	Sep 09 05:14:11 AM UTC 24
Finished	Sep 09 05:14:13 AM UTC 24
Peak memory	209788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610903628 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.1610903628
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.2272369723
Short name	T271
Test name
Test status
Simulation time	63644743 ps
CPU time	1.2 seconds
Started	Sep 09 05:14:12 AM UTC 24
Finished	Sep 09 05:14:15 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272369723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.2272369723
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.3684018688
Short name	T268
Test name
Test status
Simulation time	27611696 ps
CPU time	1.41 seconds
Started	Sep 09 05:14:11 AM UTC 24
Finished	Sep 09 05:14:13 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3684018688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.3684018688
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.455599302
Short name	T265
Test name
Test status
Simulation time	30039196 ps
CPU time	0.94 seconds
Started	Sep 09 05:14:11 AM UTC 24
Finished	Sep 09 05:14:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=455599302 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.455599302
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.2076924560
Short name	T290
Test name
Test status
Simulation time	973401797 ps
CPU time	8.58 seconds
Started	Sep 09 05:14:13 AM UTC 24
Finished	Sep 09 05:14:23 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076924560 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2076924560
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.3456222843
Short name	T262
Test name
Test status
Simulation time	23441194 ps
CPU time	1.34 seconds
Started	Sep 09 05:14:10 AM UTC 24
Finished	Sep 09 05:14:12 AM UTC 24
Peak memory	209848 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456222843 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.3456222843
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.2563138973
Short name	T42
Test name
Test status
Simulation time	4818378606 ps
CPU time	17.88 seconds
Started	Sep 09 05:14:13 AM UTC 24
Finished	Sep 09 05:14:33 AM UTC 24
Peak memory	211000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563138973 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.2563138973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.648840766
Short name	T158
Test name
Test status
Simulation time	9415980926 ps
CPU time	96.6 seconds
Started	Sep 09 05:14:13 AM UTC 24
Finished	Sep 09 05:15:52 AM UTC 24
Peak memory	220316 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648840766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.648840766
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.2327527733
Short name	T269
Test name
Test status
Simulation time	130206701 ps
CPU time	1.58 seconds
Started	Sep 09 05:14:11 AM UTC 24
Finished	Sep 09 05:14:14 AM UTC 24
Peak memory	209632 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327527733 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2327527733
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.1730862619
Short name	T286
Test name
Test status
Simulation time	20014395 ps
CPU time	1.21 seconds
Started	Sep 09 05:14:19 AM UTC 24
Finished	Sep 09 05:14:22 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730862619 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.1730862619
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.1055452014
Short name	T281
Test name
Test status
Simulation time	19535782 ps
CPU time	1.3 seconds
Started	Sep 09 05:14:18 AM UTC 24
Finished	Sep 09 05:14:20 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055452014 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.1055452014
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.1985914938
Short name	T276
Test name
Test status
Simulation time	22451779 ps
CPU time	1.1 seconds
Started	Sep 09 05:14:16 AM UTC 24
Finished	Sep 09 05:14:18 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985914938 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1985914938
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.1802850670
Short name	T284
Test name
Test status
Simulation time	22317707 ps
CPU time	1.07 seconds
Started	Sep 09 05:14:19 AM UTC 24
Finished	Sep 09 05:14:21 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802850670 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.1802850670
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.3746854884
Short name	T274
Test name
Test status
Simulation time	14072576 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:15 AM UTC 24
Finished	Sep 09 05:14:17 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3746854884 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3746854884
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.792349861
Short name	T40
Test name
Test status
Simulation time	228783334 ps
CPU time	3.03 seconds
Started	Sep 09 05:14:15 AM UTC 24
Finished	Sep 09 05:14:19 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792349861 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.792349861
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.2648112342
Short name	T283
Test name
Test status
Simulation time	779882972 ps
CPU time	5.17 seconds
Started	Sep 09 05:14:15 AM UTC 24
Finished	Sep 09 05:14:21 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648112342 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.2648112342
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.3782591768
Short name	T279
Test name
Test status
Simulation time	37065101 ps
CPU time	1.66 seconds
Started	Sep 09 05:14:16 AM UTC 24
Finished	Sep 09 05:14:19 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782591768 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.3782591768
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2385936149
Short name	T282
Test name
Test status
Simulation time	24612255 ps
CPU time	1.37 seconds
Started	Sep 09 05:14:18 AM UTC 24
Finished	Sep 09 05:14:20 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385936149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.2385936149
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2467664549
Short name	T280
Test name
Test status
Simulation time	46957151 ps
CPU time	0.97 seconds
Started	Sep 09 05:14:18 AM UTC 24
Finished	Sep 09 05:14:20 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467664549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.2467664549
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.3196289912
Short name	T277
Test name
Test status
Simulation time	44593787 ps
CPU time	1.37 seconds
Started	Sep 09 05:14:16 AM UTC 24
Finished	Sep 09 05:14:18 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196289912 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3196289912
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.4238276490
Short name	T150
Test name
Test status
Simulation time	1441195788 ps
CPU time	6.71 seconds
Started	Sep 09 05:14:19 AM UTC 24
Finished	Sep 09 05:14:27 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238276490 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.4238276490
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.3974913366
Short name	T142
Test name
Test status
Simulation time	79720511 ps
CPU time	1.58 seconds
Started	Sep 09 05:14:15 AM UTC 24
Finished	Sep 09 05:14:17 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974913366 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3974913366
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.2077279409
Short name	T78
Test name
Test status
Simulation time	2177094748 ps
CPU time	34.84 seconds
Started	Sep 09 05:14:19 AM UTC 24
Finished	Sep 09 05:14:55 AM UTC 24
Peak memory	220268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077279409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.2077279409
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.1394058844
Short name	T278
Test name
Test status
Simulation time	54146189 ps
CPU time	1.49 seconds
Started	Sep 09 05:14:16 AM UTC 24
Finished	Sep 09 05:14:19 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394058844 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1394058844
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.4052417707
Short name	T299
Test name
Test status
Simulation time	11507167 ps
CPU time	1.11 seconds
Started	Sep 09 05:14:25 AM UTC 24
Finished	Sep 09 05:14:27 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052417707 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.4052417707
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.4270434334
Short name	T104
Test name
Test status
Simulation time	41013708 ps
CPU time	1.32 seconds
Started	Sep 09 05:14:23 AM UTC 24
Finished	Sep 09 05:14:25 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270434334 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.4270434334
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.3903020596
Short name	T292
Test name
Test status
Simulation time	14613804 ps
CPU time	1.12 seconds
Started	Sep 09 05:14:22 AM UTC 24
Finished	Sep 09 05:14:24 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903020596 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3903020596
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.1422758244
Short name	T297
Test name
Test status
Simulation time	34118835 ps
CPU time	1.31 seconds
Started	Sep 09 05:14:24 AM UTC 24
Finished	Sep 09 05:14:26 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422758244 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1422758244
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.209988006
Short name	T288
Test name
Test status
Simulation time	14742494 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:20 AM UTC 24
Finished	Sep 09 05:14:23 AM UTC 24
Peak memory	210080 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209988006 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.209988006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.517047251
Short name	T332
Test name
Test status
Simulation time	1995937994 ps
CPU time	20.35 seconds
Started	Sep 09 05:14:21 AM UTC 24
Finished	Sep 09 05:14:42 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517047251 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.517047251
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.4270232415
Short name	T304
Test name
Test status
Simulation time	1237642795 ps
CPU time	6.6 seconds
Started	Sep 09 05:14:22 AM UTC 24
Finished	Sep 09 05:14:29 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270232415 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.4270232415
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.3787834378
Short name	T294
Test name
Test status
Simulation time	28613885 ps
CPU time	1.5 seconds
Started	Sep 09 05:14:22 AM UTC 24
Finished	Sep 09 05:14:24 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787834378 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.3787834378
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.789576280
Short name	T295
Test name
Test status
Simulation time	22409540 ps
CPU time	1.26 seconds
Started	Sep 09 05:14:23 AM UTC 24
Finished	Sep 09 05:14:25 AM UTC 24
Peak memory	210076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789576280 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.789576280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3083141367
Short name	T296
Test name
Test status
Simulation time	52824690 ps
CPU time	1.44 seconds
Started	Sep 09 05:14:23 AM UTC 24
Finished	Sep 09 05:14:25 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083141367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.3083141367
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.2025671446
Short name	T291
Test name
Test status
Simulation time	79451169 ps
CPU time	1.16 seconds
Started	Sep 09 05:14:22 AM UTC 24
Finished	Sep 09 05:14:24 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025671446 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2025671446
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.3777890326
Short name	T298
Test name
Test status
Simulation time	87064410 ps
CPU time	1.72 seconds
Started	Sep 09 05:14:24 AM UTC 24
Finished	Sep 09 05:14:27 AM UTC 24
Peak memory	209008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777890326 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3777890326
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.1511310571
Short name	T287
Test name
Test status
Simulation time	23757803 ps
CPU time	1.28 seconds
Started	Sep 09 05:14:19 AM UTC 24
Finished	Sep 09 05:14:22 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511310571 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1511310571
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.3169296936
Short name	T324
Test name
Test status
Simulation time	1992713485 ps
CPU time	14 seconds
Started	Sep 09 05:14:24 AM UTC 24
Finished	Sep 09 05:14:39 AM UTC 24
Peak memory	210872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169296936 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.3169296936
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.965947081
Short name	T157
Test name
Test status
Simulation time	5080156899 ps
CPU time	78.6 seconds
Started	Sep 09 05:14:24 AM UTC 24
Finished	Sep 09 05:15:44 AM UTC 24
Peak memory	220288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965947081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.965947081
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.2481888221
Short name	T293
Test name
Test status
Simulation time	27293759 ps
CPU time	1.38 seconds
Started	Sep 09 05:14:22 AM UTC 24
Finished	Sep 09 05:14:24 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481888221 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2481888221
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.2034922137
Short name	T311
Test name
Test status
Simulation time	22330969 ps
CPU time	1.18 seconds
Started	Sep 09 05:14:30 AM UTC 24
Finished	Sep 09 05:14:33 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034922137 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.2034922137
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3555383958
Short name	T309
Test name
Test status
Simulation time	18250718 ps
CPU time	1.22 seconds
Started	Sep 09 05:14:29 AM UTC 24
Finished	Sep 09 05:14:31 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555383958 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.3555383958
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.2391388811
Short name	T305
Test name
Test status
Simulation time	14759833 ps
CPU time	1.08 seconds
Started	Sep 09 05:14:28 AM UTC 24
Finished	Sep 09 05:14:30 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391388811 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2391388811
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.1209385842
Short name	T310
Test name
Test status
Simulation time	28557530 ps
CPU time	1.32 seconds
Started	Sep 09 05:14:29 AM UTC 24
Finished	Sep 09 05:14:31 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209385842 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.1209385842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.174452588
Short name	T300
Test name
Test status
Simulation time	42500731 ps
CPU time	1.36 seconds
Started	Sep 09 05:14:25 AM UTC 24
Finished	Sep 09 05:14:28 AM UTC 24
Peak memory	210508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174452588 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.174452588
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.2198888897
Short name	T336
Test name
Test status
Simulation time	1530417395 ps
CPU time	16.51 seconds
Started	Sep 09 05:14:26 AM UTC 24
Finished	Sep 09 05:14:44 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198888897 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.2198888897
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.4199866387
Short name	T331
Test name
Test status
Simulation time	1460093425 ps
CPU time	14.28 seconds
Started	Sep 09 05:14:27 AM UTC 24
Finished	Sep 09 05:14:42 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199866387 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.4199866387
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.1694412052
Short name	T306
Test name
Test status
Simulation time	36126225 ps
CPU time	1.36 seconds
Started	Sep 09 05:14:28 AM UTC 24
Finished	Sep 09 05:14:30 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694412052 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.1694412052
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.704297645
Short name	T308
Test name
Test status
Simulation time	75357524 ps
CPU time	1.61 seconds
Started	Sep 09 05:14:28 AM UTC 24
Finished	Sep 09 05:14:30 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704297645 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.704297645
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.676108248
Short name	T307
Test name
Test status
Simulation time	24266548 ps
CPU time	1.34 seconds
Started	Sep 09 05:14:28 AM UTC 24
Finished	Sep 09 05:14:30 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676108248 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.676108248
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.1897778239
Short name	T302
Test name
Test status
Simulation time	13384905 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:27 AM UTC 24
Finished	Sep 09 05:14:29 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897778239 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1897778239
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.1981631105
Short name	T7
Test name
Test status
Simulation time	1230185661 ps
CPU time	7.69 seconds
Started	Sep 09 05:14:29 AM UTC 24
Finished	Sep 09 05:14:38 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981631105 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1981631105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.3506024741
Short name	T301
Test name
Test status
Simulation time	61927229 ps
CPU time	1.57 seconds
Started	Sep 09 05:14:25 AM UTC 24
Finished	Sep 09 05:14:28 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3506024741 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.3506024741
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.4070699977
Short name	T408
Test name
Test status
Simulation time	6728720733 ps
CPU time	38.51 seconds
Started	Sep 09 05:14:30 AM UTC 24
Finished	Sep 09 05:15:10 AM UTC 24
Peak memory	211060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4070699977 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.4070699977
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.2126038784
Short name	T489
Test name
Test status
Simulation time	12229622138 ps
CPU time	70.38 seconds
Started	Sep 09 05:14:30 AM UTC 24
Finished	Sep 09 05:15:42 AM UTC 24
Peak memory	220200 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126038784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.2126038784
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.527389806
Short name	T303
Test name
Test status
Simulation time	28951174 ps
CPU time	1.28 seconds
Started	Sep 09 05:14:27 AM UTC 24
Finished	Sep 09 05:14:29 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527389806 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.527389806
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.2770446170
Short name	T322
Test name
Test status
Simulation time	25567937 ps
CPU time	1.19 seconds
Started	Sep 09 05:14:36 AM UTC 24
Finished	Sep 09 05:14:39 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770446170 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.2770446170
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1310778072
Short name	T105
Test name
Test status
Simulation time	27109050 ps
CPU time	1.38 seconds
Started	Sep 09 05:14:34 AM UTC 24
Finished	Sep 09 05:14:36 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310778072 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.1310778072
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.115405257
Short name	T313
Test name
Test status
Simulation time	42537962 ps
CPU time	1.03 seconds
Started	Sep 09 05:14:32 AM UTC 24
Finished	Sep 09 05:14:34 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115405257 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.115405257
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.229636623
Short name	T319
Test name
Test status
Simulation time	84925877 ps
CPU time	1.8 seconds
Started	Sep 09 05:14:34 AM UTC 24
Finished	Sep 09 05:14:37 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229636623 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.229636623
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.2356962166
Short name	T312
Test name
Test status
Simulation time	21426505 ps
CPU time	1.29 seconds
Started	Sep 09 05:14:30 AM UTC 24
Finished	Sep 09 05:14:33 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356962166 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2356962166
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.2069471939
Short name	T334
Test name
Test status
Simulation time	918521668 ps
CPU time	9.97 seconds
Started	Sep 09 05:14:32 AM UTC 24
Finished	Sep 09 05:14:43 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069471939 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2069471939
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.1978379331
Short name	T320
Test name
Test status
Simulation time	874037328 ps
CPU time	4.77 seconds
Started	Sep 09 05:14:32 AM UTC 24
Finished	Sep 09 05:14:37 AM UTC 24
Peak memory	210524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978379331 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.1978379331
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.1303523370
Short name	T316
Test name
Test status
Simulation time	126512226 ps
CPU time	2.25 seconds
Started	Sep 09 05:14:33 AM UTC 24
Finished	Sep 09 05:14:36 AM UTC 24
Peak memory	210444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303523370 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.1303523370
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.1387515986
Short name	T318
Test name
Test status
Simulation time	25041615 ps
CPU time	1.25 seconds
Started	Sep 09 05:14:34 AM UTC 24
Finished	Sep 09 05:14:36 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387515986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.1387515986
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.235741819
Short name	T317
Test name
Test status
Simulation time	39620942 ps
CPU time	1.27 seconds
Started	Sep 09 05:14:34 AM UTC 24
Finished	Sep 09 05:14:36 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235741819 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.235741819
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.3181270591
Short name	T314
Test name
Test status
Simulation time	16837411 ps
CPU time	1.23 seconds
Started	Sep 09 05:14:32 AM UTC 24
Finished	Sep 09 05:14:34 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181270591 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.3181270591
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.3209669209
Short name	T321
Test name
Test status
Simulation time	124019837 ps
CPU time	1.94 seconds
Started	Sep 09 05:14:35 AM UTC 24
Finished	Sep 09 05:14:38 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209669209 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3209669209
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.1163743398
Short name	T143
Test name
Test status
Simulation time	23222865 ps
CPU time	1.31 seconds
Started	Sep 09 05:14:30 AM UTC 24
Finished	Sep 09 05:14:33 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163743398 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1163743398
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.1226075368
Short name	T323
Test name
Test status
Simulation time	221700473 ps
CPU time	2.32 seconds
Started	Sep 09 05:14:35 AM UTC 24
Finished	Sep 09 05:14:39 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226075368 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.1226075368
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.3448547833
Short name	T585
Test name
Test status
Simulation time	13151431897 ps
CPU time	99.36 seconds
Started	Sep 09 05:14:35 AM UTC 24
Finished	Sep 09 05:16:17 AM UTC 24
Peak memory	220484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448547833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3448547833
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.1555307948
Short name	T315
Test name
Test status
Simulation time	24493328 ps
CPU time	1.42 seconds
Started	Sep 09 05:14:32 AM UTC 24
Finished	Sep 09 05:14:34 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555307948 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1555307948
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.623391930
Short name	T338
Test name
Test status
Simulation time	15205664 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:45 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623391930 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.623391930
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.213995544
Short name	T106
Test name
Test status
Simulation time	21562395 ps
CPU time	1.08 seconds
Started	Sep 09 05:14:40 AM UTC 24
Finished	Sep 09 05:14:42 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213995544 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.213995544
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.3986271899
Short name	T328
Test name
Test status
Simulation time	41765654 ps
CPU time	1.21 seconds
Started	Sep 09 05:14:39 AM UTC 24
Finished	Sep 09 05:14:41 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986271899 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.3986271899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.3483358816
Short name	T335
Test name
Test status
Simulation time	100511711 ps
CPU time	1.78 seconds
Started	Sep 09 05:14:41 AM UTC 24
Finished	Sep 09 05:14:44 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483358816 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.3483358816
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.493303161
Short name	T325
Test name
Test status
Simulation time	53052838 ps
CPU time	1.38 seconds
Started	Sep 09 05:14:38 AM UTC 24
Finished	Sep 09 05:14:40 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493303161 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.493303161
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.1793129180
Short name	T354
Test name
Test status
Simulation time	1918829653 ps
CPU time	10.25 seconds
Started	Sep 09 05:14:38 AM UTC 24
Finished	Sep 09 05:14:49 AM UTC 24
Peak memory	210420 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793129180 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1793129180
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.3044342404
Short name	T363
Test name
Test status
Simulation time	1695115328 ps
CPU time	14.01 seconds
Started	Sep 09 05:14:38 AM UTC 24
Finished	Sep 09 05:14:53 AM UTC 24
Peak memory	210456 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044342404 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.3044342404
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.1168006953
Short name	T327
Test name
Test status
Simulation time	27560550 ps
CPU time	1.1 seconds
Started	Sep 09 05:14:39 AM UTC 24
Finished	Sep 09 05:14:41 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168006953 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.1168006953
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.4131511168
Short name	T333
Test name
Test status
Simulation time	19225032 ps
CPU time	1.24 seconds
Started	Sep 09 05:14:40 AM UTC 24
Finished	Sep 09 05:14:42 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131511168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.4131511168
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.4001872230
Short name	T330
Test name
Test status
Simulation time	87649496 ps
CPU time	1.6 seconds
Started	Sep 09 05:14:39 AM UTC 24
Finished	Sep 09 05:14:42 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001872230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.4001872230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.652092541
Short name	T289
Test name
Test status
Simulation time	42376717 ps
CPU time	1.24 seconds
Started	Sep 09 05:14:39 AM UTC 24
Finished	Sep 09 05:14:41 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652092541 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.652092541
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.485580732
Short name	T337
Test name
Test status
Simulation time	360167404 ps
CPU time	2.37 seconds
Started	Sep 09 05:14:41 AM UTC 24
Finished	Sep 09 05:14:45 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485580732 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.485580732
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.2489859514
Short name	T326
Test name
Test status
Simulation time	62077696 ps
CPU time	1.52 seconds
Started	Sep 09 05:14:38 AM UTC 24
Finished	Sep 09 05:14:40 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489859514 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2489859514
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.192065964
Short name	T496
Test name
Test status
Simulation time	6653957083 ps
CPU time	61.58 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:15:46 AM UTC 24
Peak memory	210968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192065964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.192065964
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.4261955816
Short name	T80
Test name
Test status
Simulation time	1628880355 ps
CPU time	25.33 seconds
Started	Sep 09 05:14:41 AM UTC 24
Finished	Sep 09 05:15:08 AM UTC 24
Peak memory	227152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261955816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.4261955816
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.3189804486
Short name	T329
Test name
Test status
Simulation time	28928074 ps
CPU time	1.51 seconds
Started	Sep 09 05:14:39 AM UTC 24
Finished	Sep 09 05:14:41 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189804486 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3189804486
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.2747655413
Short name	T352
Test name
Test status
Simulation time	22637856 ps
CPU time	1.18 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:14:49 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747655413 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.2747655413
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2398330601
Short name	T348
Test name
Test status
Simulation time	32316506 ps
CPU time	1.19 seconds
Started	Sep 09 05:14:45 AM UTC 24
Finished	Sep 09 05:14:47 AM UTC 24
Peak memory	210580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398330601 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.2398330601
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.1176435317
Short name	T344
Test name
Test status
Simulation time	21439262 ps
CPU time	1.11 seconds
Started	Sep 09 05:14:44 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176435317 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1176435317
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.4260843693
Short name	T350
Test name
Test status
Simulation time	15861504 ps
CPU time	1.17 seconds
Started	Sep 09 05:14:45 AM UTC 24
Finished	Sep 09 05:14:48 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260843693 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.4260843693
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.2764636633
Short name	T339
Test name
Test status
Simulation time	43431855 ps
CPU time	1.4 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:45 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764636633 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2764636633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.1040721896
Short name	T345
Test name
Test status
Simulation time	365561789 ps
CPU time	2.45 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040721896 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1040721896
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.3106206995
Short name	T373
Test name
Test status
Simulation time	1224687027 ps
CPU time	12.6 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:57 AM UTC 24
Peak memory	210388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106206995 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.3106206995
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.4249288874
Short name	T346
Test name
Test status
Simulation time	140481019 ps
CPU time	1.61 seconds
Started	Sep 09 05:14:44 AM UTC 24
Finished	Sep 09 05:14:47 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249288874 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.4249288874
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.236143256
Short name	T347
Test name
Test status
Simulation time	13486689 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:45 AM UTC 24
Finished	Sep 09 05:14:47 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236143256 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.236143256
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4236627997
Short name	T349
Test name
Test status
Simulation time	16257860 ps
CPU time	1.21 seconds
Started	Sep 09 05:14:45 AM UTC 24
Finished	Sep 09 05:14:47 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236627997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.4236627997
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.993002006
Short name	T340
Test name
Test status
Simulation time	127679184 ps
CPU time	1.71 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993002006 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.993002006
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.1064426446
Short name	T368
Test name
Test status
Simulation time	1415891105 ps
CPU time	7.06 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:14:55 AM UTC 24
Peak memory	210408 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064426446 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1064426446
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.3072222664
Short name	T144
Test name
Test status
Simulation time	188715251 ps
CPU time	2.17 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	210496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072222664 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3072222664
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.3951776614
Short name	T529
Test name
Test status
Simulation time	8674111939 ps
CPU time	73.41 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:16:02 AM UTC 24
Peak memory	210840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951776614 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.3951776614
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.276798253
Short name	T83
Test name
Test status
Simulation time	4646086584 ps
CPU time	43.59 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:15:31 AM UTC 24
Peak memory	220100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276798253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.276798253
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.1199658811
Short name	T343
Test name
Test status
Simulation time	125275295 ps
CPU time	2.13 seconds
Started	Sep 09 05:14:43 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	210488 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199658811 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1199658811
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.71711740
Short name	T364
Test name
Test status
Simulation time	28744166 ps
CPU time	1.28 seconds
Started	Sep 09 05:14:52 AM UTC 24
Finished	Sep 09 05:14:54 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71711740 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.71711740
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1825553108
Short name	T107
Test name
Test status
Simulation time	190690110 ps
CPU time	2.25 seconds
Started	Sep 09 05:14:49 AM UTC 24
Finished	Sep 09 05:14:52 AM UTC 24
Peak memory	210308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825553108 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.1825553108
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.4225476502
Short name	T356
Test name
Test status
Simulation time	37581306 ps
CPU time	1.17 seconds
Started	Sep 09 05:14:48 AM UTC 24
Finished	Sep 09 05:14:50 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225476502 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.4225476502
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.588845041
Short name	T360
Test name
Test status
Simulation time	20741962 ps
CPU time	1.29 seconds
Started	Sep 09 05:14:49 AM UTC 24
Finished	Sep 09 05:14:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588845041 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.588845041
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.390567105
Short name	T351
Test name
Test status
Simulation time	23573875 ps
CPU time	1.06 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:14:49 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390567105 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.390567105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.13574580
Short name	T367
Test name
Test status
Simulation time	924415420 ps
CPU time	6.8 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:14:55 AM UTC 24
Peak memory	210548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13574580 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.13574580
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.469406932
Short name	T362
Test name
Test status
Simulation time	263611801 ps
CPU time	3.24 seconds
Started	Sep 09 05:14:48 AM UTC 24
Finished	Sep 09 05:14:52 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469406932 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.469406932
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.1351061201
Short name	T359
Test name
Test status
Simulation time	107272831 ps
CPU time	1.85 seconds
Started	Sep 09 05:14:48 AM UTC 24
Finished	Sep 09 05:14:51 AM UTC 24
Peak memory	210012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351061201 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.1351061201
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.255267043
Short name	T361
Test name
Test status
Simulation time	102416657 ps
CPU time	1.67 seconds
Started	Sep 09 05:14:49 AM UTC 24
Finished	Sep 09 05:14:52 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255267043 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.255267043
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.741276872
Short name	T358
Test name
Test status
Simulation time	25243477 ps
CPU time	1.35 seconds
Started	Sep 09 05:14:48 AM UTC 24
Finished	Sep 09 05:14:50 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741276872 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.741276872
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.2392550830
Short name	T355
Test name
Test status
Simulation time	21871127 ps
CPU time	1.17 seconds
Started	Sep 09 05:14:48 AM UTC 24
Finished	Sep 09 05:14:50 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392550830 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2392550830
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.3623432754
Short name	T382
Test name
Test status
Simulation time	1506350587 ps
CPU time	8.31 seconds
Started	Sep 09 05:14:50 AM UTC 24
Finished	Sep 09 05:15:00 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623432754 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3623432754
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.3748943972
Short name	T353
Test name
Test status
Simulation time	17478802 ps
CPU time	1.22 seconds
Started	Sep 09 05:14:47 AM UTC 24
Finished	Sep 09 05:14:49 AM UTC 24
Peak memory	209968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748943972 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3748943972
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.2241793263
Short name	T419
Test name
Test status
Simulation time	1640676176 ps
CPU time	22.25 seconds
Started	Sep 09 05:14:52 AM UTC 24
Finished	Sep 09 05:15:15 AM UTC 24
Peak memory	210808 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241793263 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.2241793263
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.2458000364
Short name	T184
Test name
Test status
Simulation time	5172813059 ps
CPU time	71.95 seconds
Started	Sep 09 05:14:50 AM UTC 24
Finished	Sep 09 05:16:04 AM UTC 24
Peak memory	220296 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458000364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.2458000364
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.1886020700
Short name	T357
Test name
Test status
Simulation time	31401308 ps
CPU time	1.43 seconds
Started	Sep 09 05:14:48 AM UTC 24
Finished	Sep 09 05:14:50 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886020700 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1886020700
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.3159682407
Short name	T381
Test name
Test status
Simulation time	25085942 ps
CPU time	1.2 seconds
Started	Sep 09 05:14:57 AM UTC 24
Finished	Sep 09 05:14:59 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159682407 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.3159682407
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2063957851
Short name	T378
Test name
Test status
Simulation time	84368334 ps
CPU time	1.66 seconds
Started	Sep 09 05:14:55 AM UTC 24
Finished	Sep 09 05:14:58 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063957851 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.2063957851
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.3257313825
Short name	T372
Test name
Test status
Simulation time	45722357 ps
CPU time	1.3 seconds
Started	Sep 09 05:14:54 AM UTC 24
Finished	Sep 09 05:14:56 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3257313825 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3257313825
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.4025711592
Short name	T377
Test name
Test status
Simulation time	22096109 ps
CPU time	1.27 seconds
Started	Sep 09 05:14:55 AM UTC 24
Finished	Sep 09 05:14:58 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025711592 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.4025711592
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.2237878372
Short name	T366
Test name
Test status
Simulation time	26834602 ps
CPU time	1.44 seconds
Started	Sep 09 05:14:52 AM UTC 24
Finished	Sep 09 05:14:54 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237878372 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2237878372
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.3673631617
Short name	T383
Test name
Test status
Simulation time	1507494739 ps
CPU time	5.85 seconds
Started	Sep 09 05:14:53 AM UTC 24
Finished	Sep 09 05:15:00 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673631617 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3673631617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.3465927700
Short name	T380
Test name
Test status
Simulation time	500019463 ps
CPU time	5 seconds
Started	Sep 09 05:14:53 AM UTC 24
Finished	Sep 09 05:14:59 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465927700 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.3465927700
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.1303771924
Short name	T379
Test name
Test status
Simulation time	79424850 ps
CPU time	1.7 seconds
Started	Sep 09 05:14:55 AM UTC 24
Finished	Sep 09 05:14:58 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1303771924 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.1303771924
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.900696096
Short name	T375
Test name
Test status
Simulation time	17729558 ps
CPU time	1.25 seconds
Started	Sep 09 05:14:55 AM UTC 24
Finished	Sep 09 05:14:57 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900696096 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.900696096
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2132438668
Short name	T376
Test name
Test status
Simulation time	23232770 ps
CPU time	1.31 seconds
Started	Sep 09 05:14:55 AM UTC 24
Finished	Sep 09 05:14:57 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132438668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.2132438668
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.3095784546
Short name	T369
Test name
Test status
Simulation time	62610248 ps
CPU time	1.22 seconds
Started	Sep 09 05:14:53 AM UTC 24
Finished	Sep 09 05:14:55 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095784546 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.3095784546
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.2433826139
Short name	T151
Test name
Test status
Simulation time	830756677 ps
CPU time	9.48 seconds
Started	Sep 09 05:14:56 AM UTC 24
Finished	Sep 09 05:15:07 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433826139 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2433826139
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.3843372824
Short name	T365
Test name
Test status
Simulation time	51047307 ps
CPU time	1.38 seconds
Started	Sep 09 05:14:52 AM UTC 24
Finished	Sep 09 05:14:54 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843372824 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.3843372824
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.3006693090
Short name	T477
Test name
Test status
Simulation time	5446587477 ps
CPU time	39.85 seconds
Started	Sep 09 05:14:57 AM UTC 24
Finished	Sep 09 05:15:38 AM UTC 24
Peak memory	210800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006693090 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.3006693090
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.3710565228
Short name	T498
Test name
Test status
Simulation time	2629709347 ps
CPU time	48.36 seconds
Started	Sep 09 05:14:56 AM UTC 24
Finished	Sep 09 05:15:46 AM UTC 24
Peak memory	220292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710565228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.3710565228
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.3476348026
Short name	T370
Test name
Test status
Simulation time	53852596 ps
CPU time	1.47 seconds
Started	Sep 09 05:14:53 AM UTC 24
Finished	Sep 09 05:14:55 AM UTC 24
Peak memory	208992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476348026 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3476348026
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.2882314105
Short name	T59
Test name
Test status
Simulation time	26433655 ps
CPU time	1.15 seconds
Started	Sep 09 05:13:26 AM UTC 24
Finished	Sep 09 05:13:29 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882314105 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.2882314105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3304475689
Short name	T88
Test name
Test status
Simulation time	23460230 ps
CPU time	1.21 seconds
Started	Sep 09 05:13:24 AM UTC 24
Finished	Sep 09 05:13:26 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304475689 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.3304475689
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.2508569036
Short name	T55
Test name
Test status
Simulation time	32556959 ps
CPU time	1.08 seconds
Started	Sep 09 05:13:22 AM UTC 24
Finished	Sep 09 05:13:24 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508569036 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2508569036
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.1501204442
Short name	T89
Test name
Test status
Simulation time	25861868 ps
CPU time	1.3 seconds
Started	Sep 09 05:13:25 AM UTC 24
Finished	Sep 09 05:13:28 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501204442 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.1501204442
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.1968111951
Short name	T26
Test name
Test status
Simulation time	30608632 ps
CPU time	1.43 seconds
Started	Sep 09 05:13:20 AM UTC 24
Finished	Sep 09 05:13:22 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968111951 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1968111951
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.598711828
Short name	T36
Test name
Test status
Simulation time	801869253 ps
CPU time	11.33 seconds
Started	Sep 09 05:13:20 AM UTC 24
Finished	Sep 09 05:13:32 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598711828 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.598711828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.276112221
Short name	T52
Test name
Test status
Simulation time	1935126957 ps
CPU time	17.82 seconds
Started	Sep 09 05:13:20 AM UTC 24
Finished	Sep 09 05:13:39 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276112221 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.276112221
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.1582546833
Short name	T86
Test name
Test status
Simulation time	53628646 ps
CPU time	1.61 seconds
Started	Sep 09 05:13:23 AM UTC 24
Finished	Sep 09 05:13:26 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582546833 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.1582546833
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3049505961
Short name	T87
Test name
Test status
Simulation time	19498401 ps
CPU time	1.15 seconds
Started	Sep 09 05:13:24 AM UTC 24
Finished	Sep 09 05:13:26 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049505961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.3049505961
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.731304930
Short name	T85
Test name
Test status
Simulation time	68611042 ps
CPU time	1.51 seconds
Started	Sep 09 05:13:23 AM UTC 24
Finished	Sep 09 05:13:26 AM UTC 24
Peak memory	209076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731304930 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.731304930
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.2399416219
Short name	T177
Test name
Test status
Simulation time	25569981 ps
CPU time	1.15 seconds
Started	Sep 09 05:13:21 AM UTC 24
Finished	Sep 09 05:13:23 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399416219 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2399416219
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.1554931971
Short name	T51
Test name
Test status
Simulation time	511828402 ps
CPU time	4.64 seconds
Started	Sep 09 05:13:25 AM UTC 24
Finished	Sep 09 05:13:31 AM UTC 24
Peak memory	210428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554931971 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1554931971
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.1801560133
Short name	T56
Test name
Test status
Simulation time	619085296 ps
CPU time	6.51 seconds
Started	Sep 09 05:13:25 AM UTC 24
Finished	Sep 09 05:13:33 AM UTC 24
Peak memory	242740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801560133 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.1801560133
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.2710477290
Short name	T23
Test name
Test status
Simulation time	15488077 ps
CPU time	1.21 seconds
Started	Sep 09 05:13:16 AM UTC 24
Finished	Sep 09 05:13:19 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710477290 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2710477290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.3454757677
Short name	T465
Test name
Test status
Simulation time	19376633126 ps
CPU time	125.05 seconds
Started	Sep 09 05:13:26 AM UTC 24
Finished	Sep 09 05:15:34 AM UTC 24
Peak memory	226344 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454757677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.3454757677
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.2641549568
Short name	T84
Test name
Test status
Simulation time	113144886 ps
CPU time	2 seconds
Started	Sep 09 05:13:21 AM UTC 24
Finished	Sep 09 05:13:24 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641549568 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2641549568
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.3331260618
Short name	T397
Test name
Test status
Simulation time	56489334 ps
CPU time	1.43 seconds
Started	Sep 09 05:15:03 AM UTC 24
Finished	Sep 09 05:15:05 AM UTC 24
Peak memory	210004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331260618 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.3331260618
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3254748847
Short name	T392
Test name
Test status
Simulation time	21261210 ps
CPU time	1.33 seconds
Started	Sep 09 05:15:00 AM UTC 24
Finished	Sep 09 05:15:03 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254748847 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.3254748847
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.1257682629
Short name	T388
Test name
Test status
Simulation time	33484698 ps
CPU time	1.22 seconds
Started	Sep 09 05:14:59 AM UTC 24
Finished	Sep 09 05:15:01 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257682629 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1257682629
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.1030537859
Short name	T393
Test name
Test status
Simulation time	81748937 ps
CPU time	1.61 seconds
Started	Sep 09 05:15:00 AM UTC 24
Finished	Sep 09 05:15:03 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030537859 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.1030537859
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.978562903
Short name	T385
Test name
Test status
Simulation time	90139154 ps
CPU time	1.3 seconds
Started	Sep 09 05:14:58 AM UTC 24
Finished	Sep 09 05:15:00 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978562903 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.978562903
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.2635035040
Short name	T394
Test name
Test status
Simulation time	461633312 ps
CPU time	5.29 seconds
Started	Sep 09 05:14:58 AM UTC 24
Finished	Sep 09 05:15:04 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2635035040 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2635035040
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.3058198981
Short name	T400
Test name
Test status
Simulation time	1960005568 ps
CPU time	7.17 seconds
Started	Sep 09 05:14:58 AM UTC 24
Finished	Sep 09 05:15:06 AM UTC 24
Peak memory	210524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058198981 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.3058198981
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.359512730
Short name	T389
Test name
Test status
Simulation time	72412591 ps
CPU time	1.65 seconds
Started	Sep 09 05:14:59 AM UTC 24
Finished	Sep 09 05:15:02 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359512730 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.359512730
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3551186397
Short name	T391
Test name
Test status
Simulation time	41971230 ps
CPU time	1.28 seconds
Started	Sep 09 05:15:00 AM UTC 24
Finished	Sep 09 05:15:03 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551186397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.3551186397
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2202427159
Short name	T390
Test name
Test status
Simulation time	48392093 ps
CPU time	1.31 seconds
Started	Sep 09 05:15:00 AM UTC 24
Finished	Sep 09 05:15:03 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202427159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.2202427159
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.4165863828
Short name	T386
Test name
Test status
Simulation time	13686834 ps
CPU time	1.14 seconds
Started	Sep 09 05:14:59 AM UTC 24
Finished	Sep 09 05:15:01 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165863828 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.4165863828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.1753738264
Short name	T396
Test name
Test status
Simulation time	110928154 ps
CPU time	2.24 seconds
Started	Sep 09 05:15:02 AM UTC 24
Finished	Sep 09 05:15:05 AM UTC 24
Peak memory	210248 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753738264 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1753738264
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.310715156
Short name	T384
Test name
Test status
Simulation time	20632562 ps
CPU time	1.33 seconds
Started	Sep 09 05:14:58 AM UTC 24
Finished	Sep 09 05:15:00 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310715156 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.310715156
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.3737518692
Short name	T148
Test name
Test status
Simulation time	1358872082 ps
CPU time	17.06 seconds
Started	Sep 09 05:15:02 AM UTC 24
Finished	Sep 09 05:15:20 AM UTC 24
Peak memory	210668 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737518692 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.3737518692
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.2849493928
Short name	T788
Test name
Test status
Simulation time	31154890615 ps
CPU time	135.54 seconds
Started	Sep 09 05:15:02 AM UTC 24
Finished	Sep 09 05:17:19 AM UTC 24
Peak memory	227304 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849493928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.2849493928
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.4263252978
Short name	T387
Test name
Test status
Simulation time	25419258 ps
CPU time	1.26 seconds
Started	Sep 09 05:14:59 AM UTC 24
Finished	Sep 09 05:15:01 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263252978 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.4263252978
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.2761281907
Short name	T409
Test name
Test status
Simulation time	63120438 ps
CPU time	1.5 seconds
Started	Sep 09 05:15:08 AM UTC 24
Finished	Sep 09 05:15:10 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761281907 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.2761281907
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.9471407
Short name	T406
Test name
Test status
Simulation time	30808796 ps
CPU time	1.39 seconds
Started	Sep 09 05:15:06 AM UTC 24
Finished	Sep 09 05:15:09 AM UTC 24
Peak memory	209828 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9471407 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.9471407
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.1654430657
Short name	T403
Test name
Test status
Simulation time	37537215 ps
CPU time	1.26 seconds
Started	Sep 09 05:15:05 AM UTC 24
Finished	Sep 09 05:15:07 AM UTC 24
Peak memory	209924 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654430657 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1654430657
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.548810763
Short name	T407
Test name
Test status
Simulation time	256102987 ps
CPU time	2.71 seconds
Started	Sep 09 05:15:06 AM UTC 24
Finished	Sep 09 05:15:10 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548810763 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.548810763
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.1349997402
Short name	T395
Test name
Test status
Simulation time	48940750 ps
CPU time	0.99 seconds
Started	Sep 09 05:15:03 AM UTC 24
Finished	Sep 09 05:15:05 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349997402 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1349997402
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.2924783427
Short name	T436
Test name
Test status
Simulation time	2122166780 ps
CPU time	17.74 seconds
Started	Sep 09 05:15:04 AM UTC 24
Finished	Sep 09 05:15:23 AM UTC 24
Peak memory	210648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924783427 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2924783427
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.1358488949
Short name	T421
Test name
Test status
Simulation time	1095228362 ps
CPU time	10.69 seconds
Started	Sep 09 05:15:04 AM UTC 24
Finished	Sep 09 05:15:16 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358488949 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.1358488949
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.2779248010
Short name	T404
Test name
Test status
Simulation time	26951925 ps
CPU time	1.46 seconds
Started	Sep 09 05:15:05 AM UTC 24
Finished	Sep 09 05:15:08 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779248010 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.2779248010
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.876050586
Short name	T405
Test name
Test status
Simulation time	20364555 ps
CPU time	1.21 seconds
Started	Sep 09 05:15:06 AM UTC 24
Finished	Sep 09 05:15:09 AM UTC 24
Peak memory	209704 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876050586 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.876050586
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2778817032
Short name	T402
Test name
Test status
Simulation time	92374335 ps
CPU time	1.12 seconds
Started	Sep 09 05:15:05 AM UTC 24
Finished	Sep 09 05:15:07 AM UTC 24
Peak memory	210464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778817032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.2778817032
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.3909213012
Short name	T399
Test name
Test status
Simulation time	30678918 ps
CPU time	1.14 seconds
Started	Sep 09 05:15:04 AM UTC 24
Finished	Sep 09 05:15:06 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909213012 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3909213012
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.1659348254
Short name	T152
Test name
Test status
Simulation time	601784331 ps
CPU time	6.93 seconds
Started	Sep 09 05:15:08 AM UTC 24
Finished	Sep 09 05:15:16 AM UTC 24
Peak memory	210616 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659348254 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1659348254
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.3233573896
Short name	T398
Test name
Test status
Simulation time	114035052 ps
CPU time	1.48 seconds
Started	Sep 09 05:15:03 AM UTC 24
Finished	Sep 09 05:15:05 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233573896 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.3233573896
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.1474910539
Short name	T437
Test name
Test status
Simulation time	2806812225 ps
CPU time	14.34 seconds
Started	Sep 09 05:15:08 AM UTC 24
Finished	Sep 09 05:15:23 AM UTC 24
Peak memory	210800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474910539 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.1474910539
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.3446556899
Short name	T628
Test name
Test status
Simulation time	8073765352 ps
CPU time	83.31 seconds
Started	Sep 09 05:15:08 AM UTC 24
Finished	Sep 09 05:16:33 AM UTC 24
Peak memory	227532 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446556899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.3446556899
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.9192349
Short name	T401
Test name
Test status
Simulation time	37590221 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:04 AM UTC 24
Finished	Sep 09 05:15:06 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9192349 -assert nopostproc +UVM_TESTNAME=clkmg r_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 8/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.9192349
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.144794673
Short name	T422
Test name
Test status
Simulation time	15950691 ps
CPU time	1.22 seconds
Started	Sep 09 05:15:15 AM UTC 24
Finished	Sep 09 05:15:17 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144794673 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.144794673
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.2960078993
Short name	T418
Test name
Test status
Simulation time	50569866 ps
CPU time	1.47 seconds
Started	Sep 09 05:15:12 AM UTC 24
Finished	Sep 09 05:15:15 AM UTC 24
Peak memory	209940 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960078993 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.2960078993
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.858951065
Short name	T414
Test name
Test status
Simulation time	12599427 ps
CPU time	0.88 seconds
Started	Sep 09 05:15:11 AM UTC 24
Finished	Sep 09 05:15:13 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858951065 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.858951065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.1214375312
Short name	T420
Test name
Test status
Simulation time	41310420 ps
CPU time	1.5 seconds
Started	Sep 09 05:15:12 AM UTC 24
Finished	Sep 09 05:15:15 AM UTC 24
Peak memory	209896 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1214375312 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.1214375312
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2642227855
Short name	T411
Test name
Test status
Simulation time	47307344 ps
CPU time	1.43 seconds
Started	Sep 09 05:15:09 AM UTC 24
Finished	Sep 09 05:15:11 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642227855 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2642227855
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.4076699873
Short name	T413
Test name
Test status
Simulation time	215236673 ps
CPU time	2.98 seconds
Started	Sep 09 05:15:09 AM UTC 24
Finished	Sep 09 05:15:13 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076699873 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.4076699873
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.320278947
Short name	T432
Test name
Test status
Simulation time	1957864087 ps
CPU time	11.21 seconds
Started	Sep 09 05:15:09 AM UTC 24
Finished	Sep 09 05:15:21 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320278947 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.320278947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.3715215603
Short name	T415
Test name
Test status
Simulation time	15856428 ps
CPU time	1.12 seconds
Started	Sep 09 05:15:11 AM UTC 24
Finished	Sep 09 05:15:13 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715215603 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.3715215603
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2827363471
Short name	T417
Test name
Test status
Simulation time	25772798 ps
CPU time	1.39 seconds
Started	Sep 09 05:15:11 AM UTC 24
Finished	Sep 09 05:15:14 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827363471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.2827363471
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2344502885
Short name	T416
Test name
Test status
Simulation time	26582245 ps
CPU time	1.15 seconds
Started	Sep 09 05:15:11 AM UTC 24
Finished	Sep 09 05:15:13 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344502885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.2344502885
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.254738547
Short name	T410
Test name
Test status
Simulation time	14714943 ps
CPU time	1.15 seconds
Started	Sep 09 05:15:09 AM UTC 24
Finished	Sep 09 05:15:11 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254738547 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.254738547
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.3141963093
Short name	T425
Test name
Test status
Simulation time	490330943 ps
CPU time	3.49 seconds
Started	Sep 09 05:15:14 AM UTC 24
Finished	Sep 09 05:15:18 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141963093 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.3141963093
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.1643340582
Short name	T156
Test name
Test status
Simulation time	23773339 ps
CPU time	1.29 seconds
Started	Sep 09 05:15:08 AM UTC 24
Finished	Sep 09 05:15:10 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643340582 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1643340582
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.2028386741
Short name	T145
Test name
Test status
Simulation time	54828238 ps
CPU time	1.87 seconds
Started	Sep 09 05:15:14 AM UTC 24
Finished	Sep 09 05:15:17 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028386741 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.2028386741
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.2434927613
Short name	T646
Test name
Test status
Simulation time	5535336765 ps
CPU time	82.6 seconds
Started	Sep 09 05:15:14 AM UTC 24
Finished	Sep 09 05:16:38 AM UTC 24
Peak memory	220464 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434927613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.2434927613
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.1848950314
Short name	T412
Test name
Test status
Simulation time	17899382 ps
CPU time	1.23 seconds
Started	Sep 09 05:15:10 AM UTC 24
Finished	Sep 09 05:15:12 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848950314 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1848950314
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.1117006024
Short name	T438
Test name
Test status
Simulation time	22057263 ps
CPU time	1.23 seconds
Started	Sep 09 05:15:21 AM UTC 24
Finished	Sep 09 05:15:23 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117006024 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.1117006024
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1091762585
Short name	T434
Test name
Test status
Simulation time	217343326 ps
CPU time	1.87 seconds
Started	Sep 09 05:15:19 AM UTC 24
Finished	Sep 09 05:15:21 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091762585 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.1091762585
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.1825568537
Short name	T427
Test name
Test status
Simulation time	57683532 ps
CPU time	1.37 seconds
Started	Sep 09 05:15:16 AM UTC 24
Finished	Sep 09 05:15:19 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825568537 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.1825568537
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.338451119
Short name	T433
Test name
Test status
Simulation time	87784941 ps
CPU time	1.79 seconds
Started	Sep 09 05:15:19 AM UTC 24
Finished	Sep 09 05:15:21 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338451119 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.338451119
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.1337551648
Short name	T423
Test name
Test status
Simulation time	22320132 ps
CPU time	1.14 seconds
Started	Sep 09 05:15:15 AM UTC 24
Finished	Sep 09 05:15:17 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337551648 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1337551648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.376139583
Short name	T435
Test name
Test status
Simulation time	569629982 ps
CPU time	4.44 seconds
Started	Sep 09 05:15:16 AM UTC 24
Finished	Sep 09 05:15:22 AM UTC 24
Peak memory	210324 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376139583 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.376139583
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.2728596678
Short name	T444
Test name
Test status
Simulation time	497405244 ps
CPU time	8.51 seconds
Started	Sep 09 05:15:16 AM UTC 24
Finished	Sep 09 05:15:26 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728596678 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.2728596678
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.1934157966
Short name	T429
Test name
Test status
Simulation time	26931135 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:17 AM UTC 24
Finished	Sep 09 05:15:20 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934157966 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.1934157966
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3207287115
Short name	T430
Test name
Test status
Simulation time	22884103 ps
CPU time	1.38 seconds
Started	Sep 09 05:15:17 AM UTC 24
Finished	Sep 09 05:15:20 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207287115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.3207287115
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2382665836
Short name	T431
Test name
Test status
Simulation time	122059308 ps
CPU time	1.84 seconds
Started	Sep 09 05:15:17 AM UTC 24
Finished	Sep 09 05:15:20 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382665836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.2382665836
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.1916732045
Short name	T426
Test name
Test status
Simulation time	18320198 ps
CPU time	1.23 seconds
Started	Sep 09 05:15:16 AM UTC 24
Finished	Sep 09 05:15:18 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916732045 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1916732045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.2506756334
Short name	T153
Test name
Test status
Simulation time	923970688 ps
CPU time	5.26 seconds
Started	Sep 09 05:15:20 AM UTC 24
Finished	Sep 09 05:15:26 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506756334 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2506756334
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.3103197636
Short name	T424
Test name
Test status
Simulation time	64239811 ps
CPU time	1.49 seconds
Started	Sep 09 05:15:15 AM UTC 24
Finished	Sep 09 05:15:17 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103197636 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.3103197636
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.1700672916
Short name	T470
Test name
Test status
Simulation time	1964945632 ps
CPU time	15 seconds
Started	Sep 09 05:15:20 AM UTC 24
Finished	Sep 09 05:15:36 AM UTC 24
Peak memory	210868 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700672916 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.1700672916
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.1743988278
Short name	T186
Test name
Test status
Simulation time	5089593692 ps
CPU time	59.16 seconds
Started	Sep 09 05:15:20 AM UTC 24
Finished	Sep 09 05:16:21 AM UTC 24
Peak memory	220548 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743988278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.1743988278
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.2538402565
Short name	T428
Test name
Test status
Simulation time	53541201 ps
CPU time	1.53 seconds
Started	Sep 09 05:15:16 AM UTC 24
Finished	Sep 09 05:15:19 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538402565 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2538402565
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.3870614016
Short name	T450
Test name
Test status
Simulation time	44696693 ps
CPU time	1.4 seconds
Started	Sep 09 05:15:25 AM UTC 24
Finished	Sep 09 05:15:28 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870614016 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.3870614016
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.542568758
Short name	T447
Test name
Test status
Simulation time	23474040 ps
CPU time	1.33 seconds
Started	Sep 09 05:15:24 AM UTC 24
Finished	Sep 09 05:15:26 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542568758 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.542568758
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.544288045
Short name	T440
Test name
Test status
Simulation time	19099035 ps
CPU time	1.07 seconds
Started	Sep 09 05:15:22 AM UTC 24
Finished	Sep 09 05:15:24 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544288045 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.544288045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.1686042563
Short name	T448
Test name
Test status
Simulation time	71352225 ps
CPU time	1.6 seconds
Started	Sep 09 05:15:24 AM UTC 24
Finished	Sep 09 05:15:26 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686042563 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1686042563
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.1344430090
Short name	T439
Test name
Test status
Simulation time	21111278 ps
CPU time	1.28 seconds
Started	Sep 09 05:15:21 AM UTC 24
Finished	Sep 09 05:15:24 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344430090 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1344430090
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.4124286464
Short name	T461
Test name
Test status
Simulation time	1036754748 ps
CPU time	9.5 seconds
Started	Sep 09 05:15:21 AM UTC 24
Finished	Sep 09 05:15:32 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124286464 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.4124286464
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.182029528
Short name	T482
Test name
Test status
Simulation time	1944728122 ps
CPU time	17.59 seconds
Started	Sep 09 05:15:21 AM UTC 24
Finished	Sep 09 05:15:40 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182029528 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.182029528
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.1259370040
Short name	T443
Test name
Test status
Simulation time	25226501 ps
CPU time	1.47 seconds
Started	Sep 09 05:15:22 AM UTC 24
Finished	Sep 09 05:15:25 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259370040 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.1259370040
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.801755708
Short name	T445
Test name
Test status
Simulation time	29901180 ps
CPU time	1.34 seconds
Started	Sep 09 05:15:24 AM UTC 24
Finished	Sep 09 05:15:26 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801755708 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.801755708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.742205659
Short name	T446
Test name
Test status
Simulation time	23014149 ps
CPU time	1.35 seconds
Started	Sep 09 05:15:24 AM UTC 24
Finished	Sep 09 05:15:26 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742205659 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.742205659
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.3565342763
Short name	T441
Test name
Test status
Simulation time	18127816 ps
CPU time	1.24 seconds
Started	Sep 09 05:15:22 AM UTC 24
Finished	Sep 09 05:15:24 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565342763 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3565342763
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.4121395344
Short name	T452
Test name
Test status
Simulation time	323001647 ps
CPU time	4.04 seconds
Started	Sep 09 05:15:25 AM UTC 24
Finished	Sep 09 05:15:30 AM UTC 24
Peak memory	210496 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121395344 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.4121395344
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.2626195702
Short name	T146
Test name
Test status
Simulation time	25291670 ps
CPU time	1.34 seconds
Started	Sep 09 05:15:21 AM UTC 24
Finished	Sep 09 05:15:24 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626195702 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2626195702
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.2163595059
Short name	T510
Test name
Test status
Simulation time	3079763719 ps
CPU time	23.11 seconds
Started	Sep 09 05:15:25 AM UTC 24
Finished	Sep 09 05:15:49 AM UTC 24
Peak memory	211116 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163595059 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.2163595059
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.717760444
Short name	T627
Test name
Test status
Simulation time	7702673941 ps
CPU time	65.84 seconds
Started	Sep 09 05:15:25 AM UTC 24
Finished	Sep 09 05:16:33 AM UTC 24
Peak memory	227336 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717760444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.717760444
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.741629858
Short name	T442
Test name
Test status
Simulation time	61830987 ps
CPU time	1.58 seconds
Started	Sep 09 05:15:22 AM UTC 24
Finished	Sep 09 05:15:25 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741629858 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.741629858
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.3130515927
Short name	T463
Test name
Test status
Simulation time	32965415 ps
CPU time	1.23 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:15:34 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130515927 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.3130515927
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.327773983
Short name	T459
Test name
Test status
Simulation time	21685388 ps
CPU time	1.26 seconds
Started	Sep 09 05:15:29 AM UTC 24
Finished	Sep 09 05:15:31 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327773983 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.327773983
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.4188863946
Short name	T453
Test name
Test status
Simulation time	15532633 ps
CPU time	1.14 seconds
Started	Sep 09 05:15:27 AM UTC 24
Finished	Sep 09 05:15:30 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188863946 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.4188863946
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.1291120435
Short name	T462
Test name
Test status
Simulation time	20060762 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:30 AM UTC 24
Finished	Sep 09 05:15:32 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291120435 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.1291120435
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.1063573896
Short name	T451
Test name
Test status
Simulation time	29669407 ps
CPU time	1.51 seconds
Started	Sep 09 05:15:26 AM UTC 24
Finished	Sep 09 05:15:29 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063573896 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.1063573896
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.312481698
Short name	T508
Test name
Test status
Simulation time	1753726327 ps
CPU time	20.67 seconds
Started	Sep 09 05:15:26 AM UTC 24
Finished	Sep 09 05:15:49 AM UTC 24
Peak memory	210836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312481698 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.312481698
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.1744377441
Short name	T455
Test name
Test status
Simulation time	151868783 ps
CPU time	2.21 seconds
Started	Sep 09 05:15:26 AM UTC 24
Finished	Sep 09 05:15:30 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744377441 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.1744377441
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.1374053889
Short name	T458
Test name
Test status
Simulation time	40917484 ps
CPU time	1.66 seconds
Started	Sep 09 05:15:27 AM UTC 24
Finished	Sep 09 05:15:31 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374053889 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.1374053889
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.3651456046
Short name	T460
Test name
Test status
Simulation time	47217922 ps
CPU time	1.37 seconds
Started	Sep 09 05:15:29 AM UTC 24
Finished	Sep 09 05:15:31 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651456046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.3651456046
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2595493337
Short name	T456
Test name
Test status
Simulation time	42911949 ps
CPU time	1.24 seconds
Started	Sep 09 05:15:28 AM UTC 24
Finished	Sep 09 05:15:30 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595493337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.2595493337
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.947473491
Short name	T454
Test name
Test status
Simulation time	29799559 ps
CPU time	1.19 seconds
Started	Sep 09 05:15:27 AM UTC 24
Finished	Sep 09 05:15:30 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947473491 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.947473491
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.3944414249
Short name	T481
Test name
Test status
Simulation time	1108279717 ps
CPU time	7.74 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:15:40 AM UTC 24
Peak memory	210452 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944414249 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3944414249
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.3353070536
Short name	T449
Test name
Test status
Simulation time	57876863 ps
CPU time	1.42 seconds
Started	Sep 09 05:15:25 AM UTC 24
Finished	Sep 09 05:15:28 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353070536 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3353070536
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.2192558418
Short name	T544
Test name
Test status
Simulation time	6021733976 ps
CPU time	27.21 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:16:00 AM UTC 24
Peak memory	210600 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192558418 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.2192558418
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.1046156915
Short name	T457
Test name
Test status
Simulation time	43523953 ps
CPU time	1.53 seconds
Started	Sep 09 05:15:27 AM UTC 24
Finished	Sep 09 05:15:31 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046156915 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1046156915
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.3621061765
Short name	T478
Test name
Test status
Simulation time	29856239 ps
CPU time	1.14 seconds
Started	Sep 09 05:15:36 AM UTC 24
Finished	Sep 09 05:15:38 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621061765 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.3621061765
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.783188412
Short name	T476
Test name
Test status
Simulation time	85443183 ps
CPU time	1.68 seconds
Started	Sep 09 05:15:35 AM UTC 24
Finished	Sep 09 05:15:37 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783188412 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.783188412
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.1098951054
Short name	T469
Test name
Test status
Simulation time	18081608 ps
CPU time	1.2 seconds
Started	Sep 09 05:15:32 AM UTC 24
Finished	Sep 09 05:15:35 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098951054 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1098951054
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.2349475473
Short name	T475
Test name
Test status
Simulation time	28486339 ps
CPU time	1.34 seconds
Started	Sep 09 05:15:35 AM UTC 24
Finished	Sep 09 05:15:37 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349475473 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.2349475473
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.2068871762
Short name	T466
Test name
Test status
Simulation time	63211851 ps
CPU time	1.48 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:15:34 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2068871762 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.2068871762
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.2356553943
Short name	T500
Test name
Test status
Simulation time	2019136376 ps
CPU time	13.89 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:15:47 AM UTC 24
Peak memory	210644 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356553943 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.2356553943
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.565227966
Short name	T479
Test name
Test status
Simulation time	998436315 ps
CPU time	5.47 seconds
Started	Sep 09 05:15:32 AM UTC 24
Finished	Sep 09 05:15:39 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565227966 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.565227966
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.567444634
Short name	T473
Test name
Test status
Simulation time	148365553 ps
CPU time	2.1 seconds
Started	Sep 09 05:15:34 AM UTC 24
Finished	Sep 09 05:15:37 AM UTC 24
Peak memory	210492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567444634 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.567444634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3286862142
Short name	T474
Test name
Test status
Simulation time	38569613 ps
CPU time	1.28 seconds
Started	Sep 09 05:15:35 AM UTC 24
Finished	Sep 09 05:15:37 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286862142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.3286862142
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.42189151
Short name	T471
Test name
Test status
Simulation time	47667767 ps
CPU time	1.4 seconds
Started	Sep 09 05:15:34 AM UTC 24
Finished	Sep 09 05:15:36 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42189151 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.42189151
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.3599994168
Short name	T467
Test name
Test status
Simulation time	15744833 ps
CPU time	1.24 seconds
Started	Sep 09 05:15:32 AM UTC 24
Finished	Sep 09 05:15:35 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599994168 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3599994168
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.4006946306
Short name	T494
Test name
Test status
Simulation time	1237907115 ps
CPU time	8.87 seconds
Started	Sep 09 05:15:35 AM UTC 24
Finished	Sep 09 05:15:45 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006946306 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.4006946306
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.4138508063
Short name	T464
Test name
Test status
Simulation time	35937798 ps
CPU time	1.34 seconds
Started	Sep 09 05:15:31 AM UTC 24
Finished	Sep 09 05:15:34 AM UTC 24
Peak memory	210076 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138508063 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.4138508063
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.3210733804
Short name	T737
Test name
Test status
Simulation time	8907842237 ps
CPU time	85.09 seconds
Started	Sep 09 05:15:36 AM UTC 24
Finished	Sep 09 05:17:03 AM UTC 24
Peak memory	210996 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210733804 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.3210733804
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.3149300600
Short name	T558
Test name
Test status
Simulation time	2696012879 ps
CPU time	28.19 seconds
Started	Sep 09 05:15:36 AM UTC 24
Finished	Sep 09 05:16:06 AM UTC 24
Peak memory	226976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149300600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.3149300600
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.4003388751
Short name	T468
Test name
Test status
Simulation time	29932026 ps
CPU time	1.23 seconds
Started	Sep 09 05:15:32 AM UTC 24
Finished	Sep 09 05:15:35 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003388751 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.4003388751
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.1768528617
Short name	T493
Test name
Test status
Simulation time	26584136 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:42 AM UTC 24
Finished	Sep 09 05:15:45 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768528617 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.1768528617
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1393710851
Short name	T490
Test name
Test status
Simulation time	15654534 ps
CPU time	1.18 seconds
Started	Sep 09 05:15:41 AM UTC 24
Finished	Sep 09 05:15:43 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393710851 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.1393710851
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.3805111031
Short name	T483
Test name
Test status
Simulation time	25547125 ps
CPU time	0.86 seconds
Started	Sep 09 05:15:38 AM UTC 24
Finished	Sep 09 05:15:40 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805111031 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3805111031
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.2842684661
Short name	T492
Test name
Test status
Simulation time	30321982 ps
CPU time	1.39 seconds
Started	Sep 09 05:15:41 AM UTC 24
Finished	Sep 09 05:15:44 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842684661 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.2842684661
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.3489009797
Short name	T472
Test name
Test status
Simulation time	17349449 ps
CPU time	1.19 seconds
Started	Sep 09 05:15:37 AM UTC 24
Finished	Sep 09 05:15:39 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489009797 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3489009797
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.3121330827
Short name	T506
Test name
Test status
Simulation time	1884837193 ps
CPU time	10.11 seconds
Started	Sep 09 05:15:37 AM UTC 24
Finished	Sep 09 05:15:49 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121330827 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.3121330827
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.3670679042
Short name	T497
Test name
Test status
Simulation time	1133078029 ps
CPU time	6.26 seconds
Started	Sep 09 05:15:38 AM UTC 24
Finished	Sep 09 05:15:46 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670679042 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.3670679042
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.3443961794
Short name	T488
Test name
Test status
Simulation time	20197927 ps
CPU time	1.33 seconds
Started	Sep 09 05:15:40 AM UTC 24
Finished	Sep 09 05:15:42 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443961794 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.3443961794
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.600587506
Short name	T491
Test name
Test status
Simulation time	18348201 ps
CPU time	1.28 seconds
Started	Sep 09 05:15:41 AM UTC 24
Finished	Sep 09 05:15:43 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600587506 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.600587506
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1852836865
Short name	T487
Test name
Test status
Simulation time	29338649 ps
CPU time	1.18 seconds
Started	Sep 09 05:15:40 AM UTC 24
Finished	Sep 09 05:15:42 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852836865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.1852836865
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.1976483607
Short name	T484
Test name
Test status
Simulation time	20275606 ps
CPU time	1.17 seconds
Started	Sep 09 05:15:38 AM UTC 24
Finished	Sep 09 05:15:41 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976483607 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1976483607
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.622929043
Short name	T514
Test name
Test status
Simulation time	1141563114 ps
CPU time	7.79 seconds
Started	Sep 09 05:15:41 AM UTC 24
Finished	Sep 09 05:15:50 AM UTC 24
Peak memory	210580 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622929043 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.622929043
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.932779087
Short name	T480
Test name
Test status
Simulation time	26831248 ps
CPU time	1.29 seconds
Started	Sep 09 05:15:37 AM UTC 24
Finished	Sep 09 05:15:40 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932779087 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.932779087
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.504392370
Short name	T559
Test name
Test status
Simulation time	3756249742 ps
CPU time	22.9 seconds
Started	Sep 09 05:15:42 AM UTC 24
Finished	Sep 09 05:16:07 AM UTC 24
Peak memory	210712 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504392370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.504392370
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.4206038957
Short name	T161
Test name
Test status
Simulation time	9124060281 ps
CPU time	56.02 seconds
Started	Sep 09 05:15:42 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	220228 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206038957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.4206038957
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.598247482
Short name	T485
Test name
Test status
Simulation time	33470603 ps
CPU time	1.51 seconds
Started	Sep 09 05:15:38 AM UTC 24
Finished	Sep 09 05:15:41 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598247482 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.598247482
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.1867047648
Short name	T511
Test name
Test status
Simulation time	35969671 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:47 AM UTC 24
Finished	Sep 09 05:15:50 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867047648 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.1867047648
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.2668999856
Short name	T513
Test name
Test status
Simulation time	69575042 ps
CPU time	1.66 seconds
Started	Sep 09 05:15:47 AM UTC 24
Finished	Sep 09 05:15:50 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668999856 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.2668999856
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.1738108214
Short name	T502
Test name
Test status
Simulation time	100081528 ps
CPU time	1.53 seconds
Started	Sep 09 05:15:45 AM UTC 24
Finished	Sep 09 05:15:47 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738108214 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1738108214
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.3374144365
Short name	T512
Test name
Test status
Simulation time	25078270 ps
CPU time	1.37 seconds
Started	Sep 09 05:15:47 AM UTC 24
Finished	Sep 09 05:15:50 AM UTC 24
Peak memory	210140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374144365 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.3374144365
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.752438488
Short name	T499
Test name
Test status
Simulation time	105636694 ps
CPU time	1.95 seconds
Started	Sep 09 05:15:43 AM UTC 24
Finished	Sep 09 05:15:46 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752438488 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.752438488
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.2807116156
Short name	T555
Test name
Test status
Simulation time	2237233399 ps
CPU time	19.87 seconds
Started	Sep 09 05:15:43 AM UTC 24
Finished	Sep 09 05:16:04 AM UTC 24
Peak memory	211028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807116156 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2807116156
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.2244553908
Short name	T509
Test name
Test status
Simulation time	768244391 ps
CPU time	4.79 seconds
Started	Sep 09 05:15:43 AM UTC 24
Finished	Sep 09 05:15:49 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244553908 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.2244553908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.3578443748
Short name	T507
Test name
Test status
Simulation time	190696786 ps
CPU time	1.76 seconds
Started	Sep 09 05:15:46 AM UTC 24
Finished	Sep 09 05:15:49 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578443748 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.3578443748
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1157208123
Short name	T504
Test name
Test status
Simulation time	64184170 ps
CPU time	1.08 seconds
Started	Sep 09 05:15:46 AM UTC 24
Finished	Sep 09 05:15:48 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157208123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.1157208123
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3573161789
Short name	T505
Test name
Test status
Simulation time	64843651 ps
CPU time	1.33 seconds
Started	Sep 09 05:15:46 AM UTC 24
Finished	Sep 09 05:15:48 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573161789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.3573161789
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.2521598527
Short name	T501
Test name
Test status
Simulation time	22417528 ps
CPU time	1.22 seconds
Started	Sep 09 05:15:44 AM UTC 24
Finished	Sep 09 05:15:47 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521598527 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2521598527
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.2964063465
Short name	T517
Test name
Test status
Simulation time	267299770 ps
CPU time	2.53 seconds
Started	Sep 09 05:15:47 AM UTC 24
Finished	Sep 09 05:15:51 AM UTC 24
Peak memory	210428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964063465 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2964063465
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.2599142894
Short name	T495
Test name
Test status
Simulation time	20266560 ps
CPU time	1.24 seconds
Started	Sep 09 05:15:43 AM UTC 24
Finished	Sep 09 05:15:46 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599142894 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.2599142894
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.2370855786
Short name	T690
Test name
Test status
Simulation time	8737882154 ps
CPU time	59.45 seconds
Started	Sep 09 05:15:47 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370855786 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.2370855786
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.1771879654
Short name	T852
Test name
Test status
Simulation time	41300653632 ps
CPU time	159.71 seconds
Started	Sep 09 05:15:47 AM UTC 24
Finished	Sep 09 05:18:30 AM UTC 24
Peak memory	220292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771879654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.1771879654
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.49731081
Short name	T503
Test name
Test status
Simulation time	60931304 ps
CPU time	1.77 seconds
Started	Sep 09 05:15:45 AM UTC 24
Finished	Sep 09 05:15:48 AM UTC 24
Peak memory	209000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49731081 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.49731081
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.3596656088
Short name	T530
Test name
Test status
Simulation time	189672037 ps
CPU time	2.29 seconds
Started	Sep 09 05:15:52 AM UTC 24
Finished	Sep 09 05:15:55 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3596656088 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.3596656088
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.343879549
Short name	T523
Test name
Test status
Simulation time	21058661 ps
CPU time	1.11 seconds
Started	Sep 09 05:15:51 AM UTC 24
Finished	Sep 09 05:15:53 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343879549 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.343879549
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.2778418625
Short name	T519
Test name
Test status
Simulation time	21083791 ps
CPU time	1.08 seconds
Started	Sep 09 05:15:50 AM UTC 24
Finished	Sep 09 05:15:52 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778418625 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2778418625
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.2425314815
Short name	T524
Test name
Test status
Simulation time	33813886 ps
CPU time	1.28 seconds
Started	Sep 09 05:15:51 AM UTC 24
Finished	Sep 09 05:15:53 AM UTC 24
Peak memory	209840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425314815 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.2425314815
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.3277872708
Short name	T516
Test name
Test status
Simulation time	33462729 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:48 AM UTC 24
Finished	Sep 09 05:15:51 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277872708 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.3277872708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.2697139095
Short name	T574
Test name
Test status
Simulation time	1997669498 ps
CPU time	22.32 seconds
Started	Sep 09 05:15:48 AM UTC 24
Finished	Sep 09 05:16:12 AM UTC 24
Peak memory	210708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697139095 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2697139095
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.3149486011
Short name	T522
Test name
Test status
Simulation time	275263025 ps
CPU time	2.21 seconds
Started	Sep 09 05:15:50 AM UTC 24
Finished	Sep 09 05:15:53 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149486011 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.3149486011
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.974983389
Short name	T518
Test name
Test status
Simulation time	44148773 ps
CPU time	0.9 seconds
Started	Sep 09 05:15:50 AM UTC 24
Finished	Sep 09 05:15:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974983389 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.974983389
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1533355862
Short name	T526
Test name
Test status
Simulation time	74652325 ps
CPU time	1.67 seconds
Started	Sep 09 05:15:51 AM UTC 24
Finished	Sep 09 05:15:54 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533355862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.1533355862
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3623417683
Short name	T525
Test name
Test status
Simulation time	47746330 ps
CPU time	1.56 seconds
Started	Sep 09 05:15:51 AM UTC 24
Finished	Sep 09 05:15:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623417683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.3623417683
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.2120322569
Short name	T520
Test name
Test status
Simulation time	20603169 ps
CPU time	1.21 seconds
Started	Sep 09 05:15:50 AM UTC 24
Finished	Sep 09 05:15:52 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120322569 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2120322569
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.3081318937
Short name	T533
Test name
Test status
Simulation time	376661466 ps
CPU time	3.81 seconds
Started	Sep 09 05:15:51 AM UTC 24
Finished	Sep 09 05:15:56 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081318937 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3081318937
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.1977623012
Short name	T515
Test name
Test status
Simulation time	14341042 ps
CPU time	1.25 seconds
Started	Sep 09 05:15:48 AM UTC 24
Finished	Sep 09 05:15:51 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977623012 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1977623012
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.1754853851
Short name	T624
Test name
Test status
Simulation time	4618587076 ps
CPU time	38.58 seconds
Started	Sep 09 05:15:52 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	210840 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754853851 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.1754853851
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.3423370416
Short name	T855
Test name
Test status
Simulation time	35216941679 ps
CPU time	176.99 seconds
Started	Sep 09 05:15:51 AM UTC 24
Finished	Sep 09 05:18:51 AM UTC 24
Peak memory	227332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423370416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.3423370416
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.1373698239
Short name	T521
Test name
Test status
Simulation time	26240745 ps
CPU time	1.49 seconds
Started	Sep 09 05:15:50 AM UTC 24
Finished	Sep 09 05:15:52 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373698239 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1373698239
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.3306126298
Short name	T164
Test name
Test status
Simulation time	16607590 ps
CPU time	1.2 seconds
Started	Sep 09 05:13:35 AM UTC 24
Finished	Sep 09 05:13:37 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306126298 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.3306126298
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.746941792
Short name	T191
Test name
Test status
Simulation time	23061144 ps
CPU time	1.37 seconds
Started	Sep 09 05:13:33 AM UTC 24
Finished	Sep 09 05:13:36 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746941792 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.746941792
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.84541788
Short name	T170
Test name
Test status
Simulation time	16457394 ps
CPU time	1.15 seconds
Started	Sep 09 05:13:30 AM UTC 24
Finished	Sep 09 05:13:32 AM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84541788 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.84541788
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.69275810
Short name	T192
Test name
Test status
Simulation time	23439175 ps
CPU time	1.37 seconds
Started	Sep 09 05:13:33 AM UTC 24
Finished	Sep 09 05:13:36 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69275810 -asse rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.69275810
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.1157110671
Short name	T155
Test name
Test status
Simulation time	162408718 ps
CPU time	1.96 seconds
Started	Sep 09 05:13:28 AM UTC 24
Finished	Sep 09 05:13:31 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157110671 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1157110671
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.2245870204
Short name	T11
Test name
Test status
Simulation time	443302015 ps
CPU time	5.52 seconds
Started	Sep 09 05:13:28 AM UTC 24
Finished	Sep 09 05:13:34 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245870204 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2245870204
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.2973327968
Short name	T53
Test name
Test status
Simulation time	1845797429 ps
CPU time	11.64 seconds
Started	Sep 09 05:13:28 AM UTC 24
Finished	Sep 09 05:13:40 AM UTC 24
Peak memory	210588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2973327968 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.2973327968
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.1446692985
Short name	T188
Test name
Test status
Simulation time	49248616 ps
CPU time	1.37 seconds
Started	Sep 09 05:13:31 AM UTC 24
Finished	Sep 09 05:13:33 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446692985 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1446692985
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3725883524
Short name	T190
Test name
Test status
Simulation time	64181268 ps
CPU time	1.4 seconds
Started	Sep 09 05:13:32 AM UTC 24
Finished	Sep 09 05:13:35 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725883524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.3725883524
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.2219346330
Short name	T149
Test name
Test status
Simulation time	28291915 ps
CPU time	1.38 seconds
Started	Sep 09 05:13:32 AM UTC 24
Finished	Sep 09 05:13:34 AM UTC 24
Peak memory	209008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219346330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.2219346330
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.1914476672
Short name	T189
Test name
Test status
Simulation time	24680243 ps
CPU time	1.23 seconds
Started	Sep 09 05:13:29 AM UTC 24
Finished	Sep 09 05:13:31 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914476672 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1914476672
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.1046315972
Short name	T90
Test name
Test status
Simulation time	267165402 ps
CPU time	2.62 seconds
Started	Sep 09 05:13:33 AM UTC 24
Finished	Sep 09 05:13:37 AM UTC 24
Peak memory	210492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046315972 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.1046315972
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.917628417
Short name	T65
Test name
Test status
Simulation time	440739955 ps
CPU time	2.94 seconds
Started	Sep 09 05:13:33 AM UTC 24
Finished	Sep 09 05:13:37 AM UTC 24
Peak memory	242604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917628417 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.917628417
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.3255196906
Short name	T120
Test name
Test status
Simulation time	37793376 ps
CPU time	1.44 seconds
Started	Sep 09 05:13:27 AM UTC 24
Finished	Sep 09 05:13:29 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255196906 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.3255196906
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.3075971663
Short name	T165
Test name
Test status
Simulation time	102244499 ps
CPU time	1.77 seconds
Started	Sep 09 05:13:35 AM UTC 24
Finished	Sep 09 05:13:37 AM UTC 24
Peak memory	210444 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075971663 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.3075971663
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.2717536210
Short name	T63
Test name
Test status
Simulation time	571831663 ps
CPU time	12.79 seconds
Started	Sep 09 05:13:35 AM UTC 24
Finished	Sep 09 05:13:49 AM UTC 24
Peak memory	220008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717536210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2717536210
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.1794685655
Short name	T121
Test name
Test status
Simulation time	23581475 ps
CPU time	1.36 seconds
Started	Sep 09 05:13:30 AM UTC 24
Finished	Sep 09 05:13:32 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794685655 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1794685655
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.2669052045
Short name	T541
Test name
Test status
Simulation time	64987360 ps
CPU time	1.53 seconds
Started	Sep 09 05:15:56 AM UTC 24
Finished	Sep 09 05:15:59 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669052045 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.2669052045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1731117793
Short name	T538
Test name
Test status
Simulation time	60221610 ps
CPU time	1.14 seconds
Started	Sep 09 05:15:55 AM UTC 24
Finished	Sep 09 05:15:57 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731117793 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1731117793
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.2150526776
Short name	T532
Test name
Test status
Simulation time	23385608 ps
CPU time	1.1 seconds
Started	Sep 09 05:15:54 AM UTC 24
Finished	Sep 09 05:15:56 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150526776 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2150526776
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.986942105
Short name	T540
Test name
Test status
Simulation time	21506064 ps
CPU time	1.33 seconds
Started	Sep 09 05:15:56 AM UTC 24
Finished	Sep 09 05:15:58 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986942105 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.986942105
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.2806845623
Short name	T528
Test name
Test status
Simulation time	125514971 ps
CPU time	1.95 seconds
Started	Sep 09 05:15:52 AM UTC 24
Finished	Sep 09 05:15:55 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806845623 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2806845623
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.4158157258
Short name	T537
Test name
Test status
Simulation time	415407063 ps
CPU time	3.2 seconds
Started	Sep 09 05:15:52 AM UTC 24
Finished	Sep 09 05:15:57 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158157258 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.4158157258
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.521789936
Short name	T569
Test name
Test status
Simulation time	1817244000 ps
CPU time	15.97 seconds
Started	Sep 09 05:15:52 AM UTC 24
Finished	Sep 09 05:16:10 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521789936 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.521789936
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.1110082854
Short name	T536
Test name
Test status
Simulation time	36439234 ps
CPU time	1.69 seconds
Started	Sep 09 05:15:54 AM UTC 24
Finished	Sep 09 05:15:56 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110082854 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.1110082854
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.11393290
Short name	T539
Test name
Test status
Simulation time	93241399 ps
CPU time	1.4 seconds
Started	Sep 09 05:15:55 AM UTC 24
Finished	Sep 09 05:15:57 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11393290 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.11393290
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1716737312
Short name	T534
Test name
Test status
Simulation time	77373193 ps
CPU time	1.2 seconds
Started	Sep 09 05:15:54 AM UTC 24
Finished	Sep 09 05:15:56 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1716737312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.1716737312
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.779505454
Short name	T531
Test name
Test status
Simulation time	13928641 ps
CPU time	1.13 seconds
Started	Sep 09 05:15:54 AM UTC 24
Finished	Sep 09 05:15:56 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779505454 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.779505454
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.782700470
Short name	T542
Test name
Test status
Simulation time	135893885 ps
CPU time	1.84 seconds
Started	Sep 09 05:15:56 AM UTC 24
Finished	Sep 09 05:15:59 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=782700470 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.782700470
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.2656181906
Short name	T527
Test name
Test status
Simulation time	22210868 ps
CPU time	1.31 seconds
Started	Sep 09 05:15:52 AM UTC 24
Finished	Sep 09 05:15:55 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2656181906 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2656181906
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.916461099
Short name	T650
Test name
Test status
Simulation time	9971291100 ps
CPU time	42.03 seconds
Started	Sep 09 05:15:56 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210932 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916461099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.916461099
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.2050370209
Short name	T162
Test name
Test status
Simulation time	4475638424 ps
CPU time	74.8 seconds
Started	Sep 09 05:15:56 AM UTC 24
Finished	Sep 09 05:17:13 AM UTC 24
Peak memory	227308 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2050370209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2050370209
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.1922081252
Short name	T535
Test name
Test status
Simulation time	27012810 ps
CPU time	1.41 seconds
Started	Sep 09 05:15:54 AM UTC 24
Finished	Sep 09 05:15:56 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922081252 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1922081252
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.2877074142
Short name	T554
Test name
Test status
Simulation time	65550279 ps
CPU time	1.55 seconds
Started	Sep 09 05:16:01 AM UTC 24
Finished	Sep 09 05:16:04 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877074142 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.2877074142
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3799901185
Short name	T552
Test name
Test status
Simulation time	40018649 ps
CPU time	1.29 seconds
Started	Sep 09 05:16:01 AM UTC 24
Finished	Sep 09 05:16:03 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799901185 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.3799901185
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.2869903160
Short name	T549
Test name
Test status
Simulation time	23177259 ps
CPU time	1.12 seconds
Started	Sep 09 05:15:59 AM UTC 24
Finished	Sep 09 05:16:01 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869903160 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2869903160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.289481923
Short name	T553
Test name
Test status
Simulation time	59484865 ps
CPU time	1.54 seconds
Started	Sep 09 05:16:01 AM UTC 24
Finished	Sep 09 05:16:04 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289481923 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.289481923
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.2039819887
Short name	T547
Test name
Test status
Simulation time	202278594 ps
CPU time	2.28 seconds
Started	Sep 09 05:15:57 AM UTC 24
Finished	Sep 09 05:16:01 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039819887 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2039819887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.302110228
Short name	T584
Test name
Test status
Simulation time	1653240752 ps
CPU time	17.61 seconds
Started	Sep 09 05:15:58 AM UTC 24
Finished	Sep 09 05:16:16 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302110228 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.302110228
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.632574304
Short name	T633
Test name
Test status
Simulation time	2296496249 ps
CPU time	36.35 seconds
Started	Sep 09 05:15:58 AM UTC 24
Finished	Sep 09 05:16:35 AM UTC 24
Peak memory	210836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632574304 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.632574304
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.3950523156
Short name	T548
Test name
Test status
Simulation time	13351616 ps
CPU time	1.07 seconds
Started	Sep 09 05:15:59 AM UTC 24
Finished	Sep 09 05:16:01 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950523156 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.3950523156
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2961165323
Short name	T550
Test name
Test status
Simulation time	29920619 ps
CPU time	1.31 seconds
Started	Sep 09 05:16:00 AM UTC 24
Finished	Sep 09 05:16:02 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961165323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.2961165323
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.992961839
Short name	T551
Test name
Test status
Simulation time	98868787 ps
CPU time	1.73 seconds
Started	Sep 09 05:16:00 AM UTC 24
Finished	Sep 09 05:16:03 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992961839 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.992961839
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.446286950
Short name	T545
Test name
Test status
Simulation time	61742886 ps
CPU time	1.32 seconds
Started	Sep 09 05:15:58 AM UTC 24
Finished	Sep 09 05:16:00 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446286950 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.446286950
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.3096743799
Short name	T568
Test name
Test status
Simulation time	855765371 ps
CPU time	6.79 seconds
Started	Sep 09 05:16:01 AM UTC 24
Finished	Sep 09 05:16:09 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096743799 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3096743799
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.1427523791
Short name	T543
Test name
Test status
Simulation time	17005791 ps
CPU time	1.27 seconds
Started	Sep 09 05:15:57 AM UTC 24
Finished	Sep 09 05:16:00 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427523791 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.1427523791
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.3114396186
Short name	T658
Test name
Test status
Simulation time	8639601804 ps
CPU time	38.66 seconds
Started	Sep 09 05:16:01 AM UTC 24
Finished	Sep 09 05:16:41 AM UTC 24
Peak memory	210972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114396186 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.3114396186
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.3961449553
Short name	T160
Test name
Test status
Simulation time	1421710902 ps
CPU time	22.86 seconds
Started	Sep 09 05:16:01 AM UTC 24
Finished	Sep 09 05:16:25 AM UTC 24
Peak memory	220360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961449553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.3961449553
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.3205243534
Short name	T546
Test name
Test status
Simulation time	72728237 ps
CPU time	1.5 seconds
Started	Sep 09 05:15:58 AM UTC 24
Finished	Sep 09 05:16:00 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3205243534 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3205243534
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.364945160
Short name	T570
Test name
Test status
Simulation time	14851957 ps
CPU time	1.1 seconds
Started	Sep 09 05:16:09 AM UTC 24
Finished	Sep 09 05:16:11 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364945160 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.364945160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.888394100
Short name	T567
Test name
Test status
Simulation time	84504397 ps
CPU time	1.65 seconds
Started	Sep 09 05:16:06 AM UTC 24
Finished	Sep 09 05:16:09 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888394100 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.888394100
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.1615327221
Short name	T562
Test name
Test status
Simulation time	52837201 ps
CPU time	1.31 seconds
Started	Sep 09 05:16:05 AM UTC 24
Finished	Sep 09 05:16:07 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615327221 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1615327221
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.2974204083
Short name	T566
Test name
Test status
Simulation time	21870145 ps
CPU time	1.35 seconds
Started	Sep 09 05:16:06 AM UTC 24
Finished	Sep 09 05:16:09 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974204083 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.2974204083
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.2433177157
Short name	T556
Test name
Test status
Simulation time	16929713 ps
CPU time	1.23 seconds
Started	Sep 09 05:16:03 AM UTC 24
Finished	Sep 09 05:16:05 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433177157 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2433177157
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.608872741
Short name	T581
Test name
Test status
Simulation time	1034781834 ps
CPU time	10.25 seconds
Started	Sep 09 05:16:04 AM UTC 24
Finished	Sep 09 05:16:15 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608872741 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.608872741
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.2619091420
Short name	T599
Test name
Test status
Simulation time	2521135310 ps
CPU time	17.93 seconds
Started	Sep 09 05:16:04 AM UTC 24
Finished	Sep 09 05:16:23 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619091420 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.2619091420
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.464648322
Short name	T563
Test name
Test status
Simulation time	64049885 ps
CPU time	1.46 seconds
Started	Sep 09 05:16:05 AM UTC 24
Finished	Sep 09 05:16:07 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464648322 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.464648322
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1862206034
Short name	T565
Test name
Test status
Simulation time	115553250 ps
CPU time	1.32 seconds
Started	Sep 09 05:16:06 AM UTC 24
Finished	Sep 09 05:16:08 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862206034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.1862206034
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2129443177
Short name	T564
Test name
Test status
Simulation time	30776363 ps
CPU time	1.44 seconds
Started	Sep 09 05:16:05 AM UTC 24
Finished	Sep 09 05:16:07 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129443177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.2129443177
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.3809441291
Short name	T561
Test name
Test status
Simulation time	27693702 ps
CPU time	1.17 seconds
Started	Sep 09 05:16:05 AM UTC 24
Finished	Sep 09 05:16:07 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809441291 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3809441291
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.3314324320
Short name	T578
Test name
Test status
Simulation time	763479303 ps
CPU time	5.37 seconds
Started	Sep 09 05:16:07 AM UTC 24
Finished	Sep 09 05:16:14 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314324320 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3314324320
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.3842155940
Short name	T557
Test name
Test status
Simulation time	67677825 ps
CPU time	1.58 seconds
Started	Sep 09 05:16:03 AM UTC 24
Finished	Sep 09 05:16:05 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842155940 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3842155940
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.148606380
Short name	T782
Test name
Test status
Simulation time	8061378870 ps
CPU time	68.36 seconds
Started	Sep 09 05:16:07 AM UTC 24
Finished	Sep 09 05:17:17 AM UTC 24
Peak memory	210800 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148606380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.148606380
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.3170572717
Short name	T163
Test name
Test status
Simulation time	21334267523 ps
CPU time	88.14 seconds
Started	Sep 09 05:16:07 AM UTC 24
Finished	Sep 09 05:17:37 AM UTC 24
Peak memory	220268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170572717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3170572717
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.189144436
Short name	T560
Test name
Test status
Simulation time	32802343 ps
CPU time	1.15 seconds
Started	Sep 09 05:16:05 AM UTC 24
Finished	Sep 09 05:16:07 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189144436 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.189144436
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.1311579565
Short name	T586
Test name
Test status
Simulation time	24392895 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:15 AM UTC 24
Finished	Sep 09 05:16:17 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311579565 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.1311579565
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.265611247
Short name	T583
Test name
Test status
Simulation time	51695187 ps
CPU time	1.54 seconds
Started	Sep 09 05:16:13 AM UTC 24
Finished	Sep 09 05:16:16 AM UTC 24
Peak memory	210340 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265611247 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.265611247
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.709667487
Short name	T576
Test name
Test status
Simulation time	18801125 ps
CPU time	1.09 seconds
Started	Sep 09 05:16:11 AM UTC 24
Finished	Sep 09 05:16:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709667487 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.709667487
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.3129664792
Short name	T582
Test name
Test status
Simulation time	19970181 ps
CPU time	1.05 seconds
Started	Sep 09 05:16:13 AM UTC 24
Finished	Sep 09 05:16:15 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129664792 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.3129664792
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.3851995328
Short name	T571
Test name
Test status
Simulation time	31556767 ps
CPU time	1.09 seconds
Started	Sep 09 05:16:09 AM UTC 24
Finished	Sep 09 05:16:11 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851995328 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.3851995328
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.3620075694
Short name	T601
Test name
Test status
Simulation time	1405075093 ps
CPU time	12.55 seconds
Started	Sep 09 05:16:10 AM UTC 24
Finished	Sep 09 05:16:24 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620075694 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3620075694
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.792325270
Short name	T604
Test name
Test status
Simulation time	1715658725 ps
CPU time	13.89 seconds
Started	Sep 09 05:16:10 AM UTC 24
Finished	Sep 09 05:16:25 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=792325270 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.792325270
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.3734223408
Short name	T577
Test name
Test status
Simulation time	25412067 ps
CPU time	1.41 seconds
Started	Sep 09 05:16:11 AM UTC 24
Finished	Sep 09 05:16:13 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734223408 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.3734223408
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1260309208
Short name	T580
Test name
Test status
Simulation time	48073995 ps
CPU time	1.31 seconds
Started	Sep 09 05:16:12 AM UTC 24
Finished	Sep 09 05:16:14 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260309208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.1260309208
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3254860666
Short name	T579
Test name
Test status
Simulation time	22291141 ps
CPU time	1.01 seconds
Started	Sep 09 05:16:12 AM UTC 24
Finished	Sep 09 05:16:14 AM UTC 24
Peak memory	210032 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254860666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.3254860666
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.3345065362
Short name	T573
Test name
Test status
Simulation time	26260034 ps
CPU time	1.15 seconds
Started	Sep 09 05:16:10 AM UTC 24
Finished	Sep 09 05:16:12 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345065362 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.3345065362
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.4097631067
Short name	T598
Test name
Test status
Simulation time	1605765218 ps
CPU time	7.4 seconds
Started	Sep 09 05:16:13 AM UTC 24
Finished	Sep 09 05:16:22 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097631067 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.4097631067
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.3585855755
Short name	T572
Test name
Test status
Simulation time	18616960 ps
CPU time	1.22 seconds
Started	Sep 09 05:16:09 AM UTC 24
Finished	Sep 09 05:16:11 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3585855755 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.3585855755
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.3236859280
Short name	T653
Test name
Test status
Simulation time	3990821445 ps
CPU time	24.18 seconds
Started	Sep 09 05:16:15 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210944 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236859280 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.3236859280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.1855778072
Short name	T846
Test name
Test status
Simulation time	5067315414 ps
CPU time	93.27 seconds
Started	Sep 09 05:16:15 AM UTC 24
Finished	Sep 09 05:17:50 AM UTC 24
Peak memory	220480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855778072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.1855778072
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.3885345362
Short name	T575
Test name
Test status
Simulation time	52053400 ps
CPU time	1.57 seconds
Started	Sep 09 05:16:10 AM UTC 24
Finished	Sep 09 05:16:12 AM UTC 24
Peak memory	208876 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885345362 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3885345362
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.2373059550
Short name	T600
Test name
Test status
Simulation time	19756506 ps
CPU time	1.15 seconds
Started	Sep 09 05:16:21 AM UTC 24
Finished	Sep 09 05:16:23 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373059550 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.2373059550
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.419746037
Short name	T597
Test name
Test status
Simulation time	123299262 ps
CPU time	2.13 seconds
Started	Sep 09 05:16:18 AM UTC 24
Finished	Sep 09 05:16:21 AM UTC 24
Peak memory	210212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419746037 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.419746037
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.3547690830
Short name	T590
Test name
Test status
Simulation time	14172868 ps
CPU time	1.13 seconds
Started	Sep 09 05:16:17 AM UTC 24
Finished	Sep 09 05:16:19 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547690830 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3547690830
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.665159866
Short name	T596
Test name
Test status
Simulation time	61277806 ps
CPU time	1.53 seconds
Started	Sep 09 05:16:18 AM UTC 24
Finished	Sep 09 05:16:21 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665159866 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.665159866
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.3464406111
Short name	T588
Test name
Test status
Simulation time	57145864 ps
CPU time	1.49 seconds
Started	Sep 09 05:16:15 AM UTC 24
Finished	Sep 09 05:16:17 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3464406111 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3464406111
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.2419409367
Short name	T606
Test name
Test status
Simulation time	1225752851 ps
CPU time	8.66 seconds
Started	Sep 09 05:16:16 AM UTC 24
Finished	Sep 09 05:16:26 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2419409367 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2419409367
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.3694882450
Short name	T613
Test name
Test status
Simulation time	1387708370 ps
CPU time	11.14 seconds
Started	Sep 09 05:16:16 AM UTC 24
Finished	Sep 09 05:16:28 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694882450 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.3694882450
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.3502575025
Short name	T594
Test name
Test status
Simulation time	111573753 ps
CPU time	1.93 seconds
Started	Sep 09 05:16:17 AM UTC 24
Finished	Sep 09 05:16:20 AM UTC 24
Peak memory	210572 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502575025 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.3502575025
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2562786487
Short name	T595
Test name
Test status
Simulation time	46483024 ps
CPU time	1.28 seconds
Started	Sep 09 05:16:18 AM UTC 24
Finished	Sep 09 05:16:21 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562786487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.2562786487
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1130505323
Short name	T592
Test name
Test status
Simulation time	17967669 ps
CPU time	1.17 seconds
Started	Sep 09 05:16:17 AM UTC 24
Finished	Sep 09 05:16:19 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130505323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.1130505323
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.2450994734
Short name	T589
Test name
Test status
Simulation time	12468564 ps
CPU time	1.11 seconds
Started	Sep 09 05:16:16 AM UTC 24
Finished	Sep 09 05:16:18 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450994734 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2450994734
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.3673089045
Short name	T587
Test name
Test status
Simulation time	26152238 ps
CPU time	1.25 seconds
Started	Sep 09 05:16:15 AM UTC 24
Finished	Sep 09 05:16:17 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673089045 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3673089045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.2508204951
Short name	T754
Test name
Test status
Simulation time	8034465214 ps
CPU time	47.06 seconds
Started	Sep 09 05:16:21 AM UTC 24
Finished	Sep 09 05:17:09 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508204951 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.2508204951
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.3667703722
Short name	T831
Test name
Test status
Simulation time	10480464356 ps
CPU time	69.06 seconds
Started	Sep 09 05:16:21 AM UTC 24
Finished	Sep 09 05:17:31 AM UTC 24
Peak memory	224352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667703722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3667703722
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.1495255364
Short name	T591
Test name
Test status
Simulation time	27010741 ps
CPU time	1.42 seconds
Started	Sep 09 05:16:17 AM UTC 24
Finished	Sep 09 05:16:19 AM UTC 24
Peak memory	210088 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495255364 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1495255364
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.1239421153
Short name	T616
Test name
Test status
Simulation time	42389313 ps
CPU time	1.01 seconds
Started	Sep 09 05:16:27 AM UTC 24
Finished	Sep 09 05:16:29 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239421153 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.1239421153
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3057959200
Short name	T612
Test name
Test status
Simulation time	27509055 ps
CPU time	1.24 seconds
Started	Sep 09 05:16:26 AM UTC 24
Finished	Sep 09 05:16:28 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057959200 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.3057959200
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.9200939
Short name	T608
Test name
Test status
Simulation time	20422341 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:24 AM UTC 24
Finished	Sep 09 05:16:27 AM UTC 24
Peak memory	207604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9200939 -assert nopostproc +UVM_TESTNAME=clkmg r_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.9200939
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.465036576
Short name	T611
Test name
Test status
Simulation time	24755194 ps
CPU time	1.14 seconds
Started	Sep 09 05:16:26 AM UTC 24
Finished	Sep 09 05:16:28 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465036576 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.465036576
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.1971281449
Short name	T602
Test name
Test status
Simulation time	20597446 ps
CPU time	1.23 seconds
Started	Sep 09 05:16:22 AM UTC 24
Finished	Sep 09 05:16:24 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971281449 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1971281449
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.1523694284
Short name	T615
Test name
Test status
Simulation time	1052602827 ps
CPU time	5.74 seconds
Started	Sep 09 05:16:22 AM UTC 24
Finished	Sep 09 05:16:29 AM UTC 24
Peak memory	210624 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523694284 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.1523694284
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.2361479194
Short name	T622
Test name
Test status
Simulation time	1827300111 ps
CPU time	8.85 seconds
Started	Sep 09 05:16:22 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	210648 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361479194 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.2361479194
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.162125931
Short name	T609
Test name
Test status
Simulation time	29837068 ps
CPU time	1.44 seconds
Started	Sep 09 05:16:24 AM UTC 24
Finished	Sep 09 05:16:27 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162125931 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.162125931
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3798777011
Short name	T614
Test name
Test status
Simulation time	78978672 ps
CPU time	1.56 seconds
Started	Sep 09 05:16:26 AM UTC 24
Finished	Sep 09 05:16:28 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798777011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.3798777011
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3097087777
Short name	T610
Test name
Test status
Simulation time	71096745 ps
CPU time	1.61 seconds
Started	Sep 09 05:16:24 AM UTC 24
Finished	Sep 09 05:16:27 AM UTC 24
Peak memory	208972 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097087777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.3097087777
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.2498265578
Short name	T605
Test name
Test status
Simulation time	46016063 ps
CPU time	1.33 seconds
Started	Sep 09 05:16:23 AM UTC 24
Finished	Sep 09 05:16:26 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498265578 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2498265578
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.2592544682
Short name	T629
Test name
Test status
Simulation time	934137535 ps
CPU time	5.64 seconds
Started	Sep 09 05:16:27 AM UTC 24
Finished	Sep 09 05:16:34 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592544682 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2592544682
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.452931647
Short name	T603
Test name
Test status
Simulation time	61070744 ps
CPU time	1.44 seconds
Started	Sep 09 05:16:22 AM UTC 24
Finished	Sep 09 05:16:24 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452931647 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.452931647
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.3534632973
Short name	T645
Test name
Test status
Simulation time	1542048631 ps
CPU time	9.78 seconds
Started	Sep 09 05:16:27 AM UTC 24
Finished	Sep 09 05:16:38 AM UTC 24
Peak memory	210672 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534632973 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.3534632973
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.3783594239
Short name	T674
Test name
Test status
Simulation time	1064659705 ps
CPU time	16.86 seconds
Started	Sep 09 05:16:27 AM UTC 24
Finished	Sep 09 05:16:45 AM UTC 24
Peak memory	222352 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783594239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.3783594239
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.3989397257
Short name	T607
Test name
Test status
Simulation time	73070667 ps
CPU time	1.69 seconds
Started	Sep 09 05:16:23 AM UTC 24
Finished	Sep 09 05:16:26 AM UTC 24
Peak memory	209968 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989397257 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3989397257
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_alert_test.1414456184
Short name	T631
Test name
Test status
Simulation time	29189467 ps
CPU time	0.83 seconds
Started	Sep 09 05:16:32 AM UTC 24
Finished	Sep 09 05:16:34 AM UTC 24
Peak memory	210140 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414456184 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_alert_test.1414456184
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3648251128
Short name	T625
Test name
Test status
Simulation time	30351046 ps
CPU time	1.34 seconds
Started	Sep 09 05:16:30 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648251128 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_handshake_intersig_mubi.3648251128
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_clk_status.1548884665
Short name	T620
Test name
Test status
Simulation time	16659478 ps
CPU time	1.08 seconds
Started	Sep 09 05:16:29 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548884665 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1548884665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_div_intersig_mubi.395665574
Short name	T632
Test name
Test status
Simulation time	28468590 ps
CPU time	1.38 seconds
Started	Sep 09 05:16:32 AM UTC 24
Finished	Sep 09 05:16:34 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395665574 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_div_intersig_mubi.395665574
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.3629414008
Short name	T619
Test name
Test status
Simulation time	65981298 ps
CPU time	1.51 seconds
Started	Sep 09 05:16:28 AM UTC 24
Finished	Sep 09 05:16:31 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629414008 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3629414008
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.2107745158
Short name	T654
Test name
Test status
Simulation time	1155662455 ps
CPU time	10.72 seconds
Started	Sep 09 05:16:28 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107745158 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.2107745158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.908410254
Short name	T630
Test name
Test status
Simulation time	763861036 ps
CPU time	4.72 seconds
Started	Sep 09 05:16:28 AM UTC 24
Finished	Sep 09 05:16:34 AM UTC 24
Peak memory	210588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908410254 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.908410254
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_idle_intersig_mubi.2037012090
Short name	T621
Test name
Test status
Simulation time	14440513 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:30 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037012090 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_idle_intersig_mubi.2037012090
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3724066968
Short name	T626
Test name
Test status
Simulation time	115082874 ps
CPU time	1.48 seconds
Started	Sep 09 05:16:30 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724066968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.3724066968
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1981459743
Short name	T623
Test name
Test status
Simulation time	25373939 ps
CPU time	1.29 seconds
Started	Sep 09 05:16:30 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981459743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_ctrl_intersig_mubi.1981459743
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.1415467502
Short name	T618
Test name
Test status
Simulation time	15451188 ps
CPU time	1.17 seconds
Started	Sep 09 05:16:28 AM UTC 24
Finished	Sep 09 05:16:31 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415467502 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1415467502
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_regwen.282609931
Short name	T9
Test name
Test status
Simulation time	300261008 ps
CPU time	3.71 seconds
Started	Sep 09 05:16:32 AM UTC 24
Finished	Sep 09 05:16:37 AM UTC 24
Peak memory	210284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282609931 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.282609931
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.3542573927
Short name	T617
Test name
Test status
Simulation time	17074836 ps
CPU time	1.31 seconds
Started	Sep 09 05:16:28 AM UTC 24
Finished	Sep 09 05:16:31 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542573927 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3542573927
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all.3390381911
Short name	T750
Test name
Test status
Simulation time	6400055698 ps
CPU time	34.24 seconds
Started	Sep 09 05:16:32 AM UTC 24
Finished	Sep 09 05:17:08 AM UTC 24
Peak memory	210936 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390381911 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all.3390381911
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_stress_all_with_rand_reset.692148643
Short name	T842
Test name
Test status
Simulation time	7727231766 ps
CPU time	68.45 seconds
Started	Sep 09 05:16:32 AM UTC 24
Finished	Sep 09 05:17:42 AM UTC 24
Peak memory	220396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692148643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.692148643
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.1098495007
Short name	T593
Test name
Test status
Simulation time	15469494 ps
CPU time	1.22 seconds
Started	Sep 09 05:16:29 AM UTC 24
Finished	Sep 09 05:16:32 AM UTC 24
Peak memory	210204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098495007 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1098495007
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.3333264280
Short name	T647
Test name
Test status
Simulation time	14400830 ps
CPU time	1.14 seconds
Started	Sep 09 05:16:36 AM UTC 24
Finished	Sep 09 05:16:38 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333264280 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.3333264280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1147467639
Short name	T643
Test name
Test status
Simulation time	35262082 ps
CPU time	1.08 seconds
Started	Sep 09 05:16:35 AM UTC 24
Finished	Sep 09 05:16:37 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147467639 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.1147467639
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.3308418233
Short name	T638
Test name
Test status
Simulation time	42934754 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308418233 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3308418233
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.494395201
Short name	T644
Test name
Test status
Simulation time	82871630 ps
CPU time	1.56 seconds
Started	Sep 09 05:16:35 AM UTC 24
Finished	Sep 09 05:16:38 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494395201 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.494395201
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.3960854441
Short name	T634
Test name
Test status
Simulation time	14687312 ps
CPU time	1.15 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960854441 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3960854441
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.4220412758
Short name	T681
Test name
Test status
Simulation time	1278614908 ps
CPU time	13.16 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210688 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220412758 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.4220412758
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.3577457482
Short name	T676
Test name
Test status
Simulation time	2304317689 ps
CPU time	11.29 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:46 AM UTC 24
Peak memory	210836 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577457482 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.3577457482
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.3007022475
Short name	T642
Test name
Test status
Simulation time	89595883 ps
CPU time	1.83 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:37 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007022475 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.3007022475
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.116721009
Short name	T639
Test name
Test status
Simulation time	19957117 ps
CPU time	1.24 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116721009 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.116721009
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2553836131
Short name	T635
Test name
Test status
Simulation time	12844958 ps
CPU time	0.98 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553836131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.2553836131
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.3799610413
Short name	T636
Test name
Test status
Simulation time	19810460 ps
CPU time	1.21 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799610413 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3799610413
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.3741140423
Short name	T667
Test name
Test status
Simulation time	1200461708 ps
CPU time	7.13 seconds
Started	Sep 09 05:16:35 AM UTC 24
Finished	Sep 09 05:16:43 AM UTC 24
Peak memory	210832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741140423 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.3741140423
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.4290067870
Short name	T637
Test name
Test status
Simulation time	31338021 ps
CPU time	1.4 seconds
Started	Sep 09 05:16:33 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290067870 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.4290067870
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.3823568656
Short name	T839
Test name
Test status
Simulation time	7828823215 ps
CPU time	60.75 seconds
Started	Sep 09 05:16:36 AM UTC 24
Finished	Sep 09 05:17:39 AM UTC 24
Peak memory	211096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823568656 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.3823568656
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.1899084640
Short name	T770
Test name
Test status
Simulation time	3229052084 ps
CPU time	37.29 seconds
Started	Sep 09 05:16:35 AM UTC 24
Finished	Sep 09 05:17:14 AM UTC 24
Peak memory	220552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899084640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1899084640
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.168693785
Short name	T640
Test name
Test status
Simulation time	32638509 ps
CPU time	1.55 seconds
Started	Sep 09 05:16:34 AM UTC 24
Finished	Sep 09 05:16:36 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168693785 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.168693785
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.1665287928
Short name	T665
Test name
Test status
Simulation time	123227992 ps
CPU time	1.47 seconds
Started	Sep 09 05:16:40 AM UTC 24
Finished	Sep 09 05:16:43 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665287928 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.1665287928
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.268042307
Short name	T660
Test name
Test status
Simulation time	83727025 ps
CPU time	1.37 seconds
Started	Sep 09 05:16:39 AM UTC 24
Finished	Sep 09 05:16:42 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268042307 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.268042307
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.3705966882
Short name	T651
Test name
Test status
Simulation time	14853845 ps
CPU time	1.02 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705966882 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3705966882
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.2065637243
Short name	T661
Test name
Test status
Simulation time	47205182 ps
CPU time	1.5 seconds
Started	Sep 09 05:16:39 AM UTC 24
Finished	Sep 09 05:16:42 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065637243 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.2065637243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.3576792398
Short name	T649
Test name
Test status
Simulation time	26797823 ps
CPU time	1.21 seconds
Started	Sep 09 05:16:36 AM UTC 24
Finished	Sep 09 05:16:39 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576792398 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3576792398
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.336271597
Short name	T693
Test name
Test status
Simulation time	1685316790 ps
CPU time	10.86 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:50 AM UTC 24
Peak memory	210432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336271597 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.336271597
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.4022342230
Short name	T682
Test name
Test status
Simulation time	1233096165 ps
CPU time	9.2 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210652 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022342230 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.4022342230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.3500434271
Short name	T657
Test name
Test status
Simulation time	69331284 ps
CPU time	1.58 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500434271 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3500434271
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.4235978224
Short name	T659
Test name
Test status
Simulation time	85170383 ps
CPU time	1.32 seconds
Started	Sep 09 05:16:39 AM UTC 24
Finished	Sep 09 05:16:42 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235978224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_clk_byp_req_intersig_mubi.4235978224
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3344917933
Short name	T655
Test name
Test status
Simulation time	22225456 ps
CPU time	1.25 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344917933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.3344917933
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.1839035558
Short name	T652
Test name
Test status
Simulation time	23569908 ps
CPU time	1.14 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839035558 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1839035558
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.2315196522
Short name	T673
Test name
Test status
Simulation time	475317656 ps
CPU time	4.22 seconds
Started	Sep 09 05:16:39 AM UTC 24
Finished	Sep 09 05:16:44 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315196522 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2315196522
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.593814903
Short name	T648
Test name
Test status
Simulation time	41879814 ps
CPU time	1.11 seconds
Started	Sep 09 05:16:36 AM UTC 24
Finished	Sep 09 05:16:38 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593814903 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.593814903
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.3935008277
Short name	T696
Test name
Test status
Simulation time	1147865653 ps
CPU time	9.56 seconds
Started	Sep 09 05:16:39 AM UTC 24
Finished	Sep 09 05:16:50 AM UTC 24
Peak memory	210676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935008277 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.3935008277
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.271196502
Short name	T832
Test name
Test status
Simulation time	3253748293 ps
CPU time	51.26 seconds
Started	Sep 09 05:16:39 AM UTC 24
Finished	Sep 09 05:17:32 AM UTC 24
Peak memory	220292 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271196502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.271196502
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.4179950971
Short name	T656
Test name
Test status
Simulation time	67061112 ps
CPU time	1.57 seconds
Started	Sep 09 05:16:38 AM UTC 24
Finished	Sep 09 05:16:40 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179950971 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.4179950971
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_alert_test.1544051533
Short name	T680
Test name
Test status
Simulation time	48359790 ps
CPU time	1.38 seconds
Started	Sep 09 05:16:44 AM UTC 24
Finished	Sep 09 05:16:47 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544051533 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_alert_test.1544051533
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.4002560449
Short name	T672
Test name
Test status
Simulation time	37186139 ps
CPU time	1.29 seconds
Started	Sep 09 05:16:42 AM UTC 24
Finished	Sep 09 05:16:44 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002560449 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_handshake_intersig_mubi.4002560449
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.4075819036
Short name	T668
Test name
Test status
Simulation time	23196727 ps
CPU time	1.09 seconds
Started	Sep 09 05:16:42 AM UTC 24
Finished	Sep 09 05:16:44 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075819036 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.4075819036
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_div_intersig_mubi.1880461089
Short name	T675
Test name
Test status
Simulation time	49916954 ps
CPU time	1.3 seconds
Started	Sep 09 05:16:43 AM UTC 24
Finished	Sep 09 05:16:45 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880461089 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_div_intersig_mubi.1880461089
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.4246822399
Short name	T662
Test name
Test status
Simulation time	96767123 ps
CPU time	1.23 seconds
Started	Sep 09 05:16:41 AM UTC 24
Finished	Sep 09 05:16:43 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246822399 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.4246822399
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.3761463027
Short name	T677
Test name
Test status
Simulation time	691515805 ps
CPU time	4.75 seconds
Started	Sep 09 05:16:41 AM UTC 24
Finished	Sep 09 05:16:46 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761463027 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3761463027
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.3586177356
Short name	T691
Test name
Test status
Simulation time	755903124 ps
CPU time	6.98 seconds
Started	Sep 09 05:16:41 AM UTC 24
Finished	Sep 09 05:16:49 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586177356 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.3586177356
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.4293359497
Short name	T670
Test name
Test status
Simulation time	22573826 ps
CPU time	1.26 seconds
Started	Sep 09 05:16:42 AM UTC 24
Finished	Sep 09 05:16:44 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293359497 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.4293359497
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2756000612
Short name	T671
Test name
Test status
Simulation time	17958108 ps
CPU time	1.24 seconds
Started	Sep 09 05:16:42 AM UTC 24
Finished	Sep 09 05:16:44 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756000612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_clk_byp_req_intersig_mubi.2756000612
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.4268407832
Short name	T669
Test name
Test status
Simulation time	26184595 ps
CPU time	1.09 seconds
Started	Sep 09 05:16:42 AM UTC 24
Finished	Sep 09 05:16:44 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268407832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_lc_ctrl_intersig_mubi.4268407832
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.3281756953
Short name	T664
Test name
Test status
Simulation time	39559348 ps
CPU time	1.3 seconds
Started	Sep 09 05:16:41 AM UTC 24
Finished	Sep 09 05:16:43 AM UTC 24
Peak memory	210204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281756953 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3281756953
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_regwen.2375796749
Short name	T688
Test name
Test status
Simulation time	725525832 ps
CPU time	4.09 seconds
Started	Sep 09 05:16:43 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375796749 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.2375796749
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.1926471191
Short name	T663
Test name
Test status
Simulation time	44900846 ps
CPU time	1.4 seconds
Started	Sep 09 05:16:41 AM UTC 24
Finished	Sep 09 05:16:43 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926471191 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1926471191
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all.3955450543
Short name	T836
Test name
Test status
Simulation time	6413506913 ps
CPU time	51.94 seconds
Started	Sep 09 05:16:44 AM UTC 24
Finished	Sep 09 05:17:38 AM UTC 24
Peak memory	210872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955450543 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all.3955450543
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_stress_all_with_rand_reset.3991240138
Short name	T795
Test name
Test status
Simulation time	1990234396 ps
CPU time	35.95 seconds
Started	Sep 09 05:16:44 AM UTC 24
Finished	Sep 09 05:17:22 AM UTC 24
Peak memory	220196 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991240138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3991240138
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/39.clkmgr_trans.1643044326
Short name	T666
Test name
Test status
Simulation time	27696447 ps
CPU time	1.3 seconds
Started	Sep 09 05:16:41 AM UTC 24
Finished	Sep 09 05:16:43 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643044326 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1643044326
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/39.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.3036937021
Short name	T199
Test name
Test status
Simulation time	114095598 ps
CPU time	1.84 seconds
Started	Sep 09 05:13:40 AM UTC 24
Finished	Sep 09 05:13:43 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036937021 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.3036937021
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.4173068153
Short name	T196
Test name
Test status
Simulation time	68692302 ps
CPU time	1.6 seconds
Started	Sep 09 05:13:39 AM UTC 24
Finished	Sep 09 05:13:41 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173068153 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.4173068153
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.1923077706
Short name	T171
Test name
Test status
Simulation time	49311148 ps
CPU time	1.27 seconds
Started	Sep 09 05:13:37 AM UTC 24
Finished	Sep 09 05:13:39 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923077706 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1923077706
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.2098229280
Short name	T197
Test name
Test status
Simulation time	24405257 ps
CPU time	1.38 seconds
Started	Sep 09 05:13:40 AM UTC 24
Finished	Sep 09 05:13:42 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098229280 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.2098229280
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.2512718908
Short name	T166
Test name
Test status
Simulation time	18729497 ps
CPU time	1.26 seconds
Started	Sep 09 05:13:36 AM UTC 24
Finished	Sep 09 05:13:38 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512718908 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.2512718908
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.2177630545
Short name	T38
Test name
Test status
Simulation time	446232749 ps
CPU time	5.98 seconds
Started	Sep 09 05:13:36 AM UTC 24
Finished	Sep 09 05:13:43 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177630545 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2177630545
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.1103406989
Short name	T187
Test name
Test status
Simulation time	1943239887 ps
CPU time	11.86 seconds
Started	Sep 09 05:13:37 AM UTC 24
Finished	Sep 09 05:13:50 AM UTC 24
Peak memory	210400 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103406989 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.1103406989
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.1749936403
Short name	T195
Test name
Test status
Simulation time	37893824 ps
CPU time	1.27 seconds
Started	Sep 09 05:13:38 AM UTC 24
Finished	Sep 09 05:13:41 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749936403 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.1749936403
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2103198682
Short name	T194
Test name
Test status
Simulation time	17501097 ps
CPU time	1.22 seconds
Started	Sep 09 05:13:38 AM UTC 24
Finished	Sep 09 05:13:41 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103198682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.2103198682
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3664545200
Short name	T193
Test name
Test status
Simulation time	23467810 ps
CPU time	1.16 seconds
Started	Sep 09 05:13:38 AM UTC 24
Finished	Sep 09 05:13:41 AM UTC 24
Peak memory	210512 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664545200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.3664545200
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.2307421749
Short name	T168
Test name
Test status
Simulation time	44501287 ps
CPU time	1.02 seconds
Started	Sep 09 05:13:37 AM UTC 24
Finished	Sep 09 05:13:39 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307421749 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.2307421749
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.599217720
Short name	T206
Test name
Test status
Simulation time	1208689445 ps
CPU time	6.38 seconds
Started	Sep 09 05:13:40 AM UTC 24
Finished	Sep 09 05:13:47 AM UTC 24
Peak memory	210460 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599217720 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.599217720
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.321704211
Short name	T64
Test name
Test status
Simulation time	153544334 ps
CPU time	3.42 seconds
Started	Sep 09 05:13:40 AM UTC 24
Finished	Sep 09 05:13:44 AM UTC 24
Peak memory	242604 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321704211 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.321704211
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.634005243
Short name	T167
Test name
Test status
Simulation time	17408046 ps
CPU time	1.29 seconds
Started	Sep 09 05:13:36 AM UTC 24
Finished	Sep 09 05:13:38 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634005243 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.634005243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.2903518849
Short name	T41
Test name
Test status
Simulation time	9362516764 ps
CPU time	47.19 seconds
Started	Sep 09 05:13:40 AM UTC 24
Finished	Sep 09 05:14:28 AM UTC 24
Peak memory	210928 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903518849 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.2903518849
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.257563415
Short name	T77
Test name
Test status
Simulation time	9660480069 ps
CPU time	59.58 seconds
Started	Sep 09 05:13:40 AM UTC 24
Finished	Sep 09 05:14:41 AM UTC 24
Peak memory	220492 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257563415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.257563415
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.2201866451
Short name	T169
Test name
Test status
Simulation time	13216517 ps
CPU time	1.09 seconds
Started	Sep 09 05:13:37 AM UTC 24
Finished	Sep 09 05:13:39 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201866451 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2201866451
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.2569333766
Short name	T697
Test name
Test status
Simulation time	15802738 ps
CPU time	0.83 seconds
Started	Sep 09 05:16:48 AM UTC 24
Finished	Sep 09 05:16:50 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569333766 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.2569333766
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4023367939
Short name	T694
Test name
Test status
Simulation time	30982075 ps
CPU time	1.37 seconds
Started	Sep 09 05:16:47 AM UTC 24
Finished	Sep 09 05:16:50 AM UTC 24
Peak memory	209864 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023367939 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_handshake_intersig_mubi.4023367939
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_clk_status.1715844302
Short name	T683
Test name
Test status
Simulation time	27081279 ps
CPU time	1.15 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	209012 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715844302 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1715844302
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_div_intersig_mubi.462371992
Short name	T695
Test name
Test status
Simulation time	82923675 ps
CPU time	1.65 seconds
Started	Sep 09 05:16:47 AM UTC 24
Finished	Sep 09 05:16:50 AM UTC 24
Peak memory	210068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462371992 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_div_intersig_mubi.462371992
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_extclk.245456880
Short name	T679
Test name
Test status
Simulation time	19602706 ps
CPU time	1.18 seconds
Started	Sep 09 05:16:44 AM UTC 24
Finished	Sep 09 05:16:47 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245456880 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.245456880
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency.2589925907
Short name	T741
Test name
Test status
Simulation time	2121312264 ps
CPU time	19.31 seconds
Started	Sep 09 05:16:45 AM UTC 24
Finished	Sep 09 05:17:05 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589925907 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.2589925907
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_frequency_timeout.2088360633
Short name	T707
Test name
Test status
Simulation time	1414452710 ps
CPU time	6.27 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:53 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088360633 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_timeout.2088360633
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_idle_intersig_mubi.3492392232
Short name	T684
Test name
Test status
Simulation time	21693201 ps
CPU time	1.17 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3492392232 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_idle_intersig_mubi.3492392232
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.4079981446
Short name	T687
Test name
Test status
Simulation time	39302570 ps
CPU time	1.25 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079981446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_clk_byp_req_intersig_mubi.4079981446
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.1421943247
Short name	T689
Test name
Test status
Simulation time	42732174 ps
CPU time	1.41 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1421943247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_lc_ctrl_intersig_mubi.1421943247
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_peri.2691817582
Short name	T686
Test name
Test status
Simulation time	88295689 ps
CPU time	1.47 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691817582 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2691817582
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.2000460343
Short name	T692
Test name
Test status
Simulation time	93975620 ps
CPU time	1.28 seconds
Started	Sep 09 05:16:47 AM UTC 24
Finished	Sep 09 05:16:50 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000460343 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2000460343
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_smoke.3081748120
Short name	T678
Test name
Test status
Simulation time	50348712 ps
CPU time	1.1 seconds
Started	Sep 09 05:16:44 AM UTC 24
Finished	Sep 09 05:16:47 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081748120 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.3081748120
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.2455725055
Short name	T734
Test name
Test status
Simulation time	1549399826 ps
CPU time	13.13 seconds
Started	Sep 09 05:16:47 AM UTC 24
Finished	Sep 09 05:17:02 AM UTC 24
Peak memory	210676 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2455725055 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.2455725055
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all_with_rand_reset.3928305084
Short name	T850
Test name
Test status
Simulation time	8231285249 ps
CPU time	88.53 seconds
Started	Sep 09 05:16:47 AM UTC 24
Finished	Sep 09 05:18:18 AM UTC 24
Peak memory	224432 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928305084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3928305084
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/40.clkmgr_trans.430359878
Short name	T685
Test name
Test status
Simulation time	30496058 ps
CPU time	1.35 seconds
Started	Sep 09 05:16:46 AM UTC 24
Finished	Sep 09 05:16:48 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430359878 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.430359878
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/40.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.799087996
Short name	T712
Test name
Test status
Simulation time	66643982 ps
CPU time	1.55 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:16:54 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799087996 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.799087996
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1096310568
Short name	T702
Test name
Test status
Simulation time	27244845 ps
CPU time	1.09 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096310568 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.1096310568
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.809237013
Short name	T699
Test name
Test status
Simulation time	22214881 ps
CPU time	0.96 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:52 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809237013 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.809237013
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.2860837817
Short name	T708
Test name
Test status
Simulation time	41366549 ps
CPU time	0.95 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:16:53 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860837817 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.2860837817
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.695473221
Short name	T641
Test name
Test status
Simulation time	37715207 ps
CPU time	1.25 seconds
Started	Sep 09 05:16:49 AM UTC 24
Finished	Sep 09 05:16:51 AM UTC 24
Peak memory	210508 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695473221 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.695473221
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency.2533240038
Short name	T701
Test name
Test status
Simulation time	357205862 ps
CPU time	2.41 seconds
Started	Sep 09 05:16:49 AM UTC 24
Finished	Sep 09 05:16:52 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2533240038 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2533240038
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_frequency_timeout.2210474441
Short name	T709
Test name
Test status
Simulation time	261968173 ps
CPU time	3.58 seconds
Started	Sep 09 05:16:49 AM UTC 24
Finished	Sep 09 05:16:53 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210474441 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_timeout.2210474441
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.3711690037
Short name	T705
Test name
Test status
Simulation time	47160444 ps
CPU time	1.63 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711690037 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.3711690037
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2371009890
Short name	T704
Test name
Test status
Simulation time	45740981 ps
CPU time	1.37 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:52 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371009890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.2371009890
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2155096045
Short name	T703
Test name
Test status
Simulation time	58060048 ps
CPU time	1.18 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:52 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155096045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.2155096045
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.3210864248
Short name	T700
Test name
Test status
Simulation time	16966209 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:52 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210864248 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3210864248
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.2561873845
Short name	T728
Test name
Test status
Simulation time	1184892439 ps
CPU time	7.83 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:17:00 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561873845 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.2561873845
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.1642933913
Short name	T698
Test name
Test status
Simulation time	45158265 ps
CPU time	1.35 seconds
Started	Sep 09 05:16:48 AM UTC 24
Finished	Sep 09 05:16:51 AM UTC 24
Peak memory	210204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642933913 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1642933913
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.144722339
Short name	T830
Test name
Test status
Simulation time	4906847237 ps
CPU time	38.57 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:17:31 AM UTC 24
Peak memory	210992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144722339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.144722339
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.2304366386
Short name	T706
Test name
Test status
Simulation time	128392676 ps
CPU time	2.05 seconds
Started	Sep 09 05:16:50 AM UTC 24
Finished	Sep 09 05:16:53 AM UTC 24
Peak memory	210428 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304366386 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2304366386
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.2134018224
Short name	T722
Test name
Test status
Simulation time	44298832 ps
CPU time	1.25 seconds
Started	Sep 09 05:16:55 AM UTC 24
Finished	Sep 09 05:16:58 AM UTC 24
Peak memory	209992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134018224 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.2134018224
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.4226704878
Short name	T720
Test name
Test status
Simulation time	21793987 ps
CPU time	1.34 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:16:56 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226704878 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.4226704878
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.4239609058
Short name	T713
Test name
Test status
Simulation time	16677755 ps
CPU time	1.11 seconds
Started	Sep 09 05:16:53 AM UTC 24
Finished	Sep 09 05:16:55 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239609058 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.4239609058
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.823956910
Short name	T718
Test name
Test status
Simulation time	18048428 ps
CPU time	1.18 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:16:56 AM UTC 24
Peak memory	210220 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823956910 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.823956910
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.2436999023
Short name	T711
Test name
Test status
Simulation time	21360993 ps
CPU time	1.13 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:16:54 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436999023 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2436999023
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.1340115936
Short name	T716
Test name
Test status
Simulation time	222142796 ps
CPU time	1.62 seconds
Started	Sep 09 05:16:53 AM UTC 24
Finished	Sep 09 05:16:55 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340115936 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1340115936
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.2255091247
Short name	T757
Test name
Test status
Simulation time	1820048980 ps
CPU time	15.61 seconds
Started	Sep 09 05:16:53 AM UTC 24
Finished	Sep 09 05:17:10 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255091247 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.2255091247
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.917567604
Short name	T721
Test name
Test status
Simulation time	175514718 ps
CPU time	1.7 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:16:57 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917567604 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.917567604
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.2534739824
Short name	T719
Test name
Test status
Simulation time	15030359 ps
CPU time	1.19 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:16:56 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534739824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.2534739824
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.1550435993
Short name	T717
Test name
Test status
Simulation time	27082246 ps
CPU time	1.01 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:16:56 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550435993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.1550435993
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.3886593363
Short name	T714
Test name
Test status
Simulation time	19126363 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:53 AM UTC 24
Finished	Sep 09 05:16:55 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886593363 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3886593363
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.910466731
Short name	T730
Test name
Test status
Simulation time	766311203 ps
CPU time	5.38 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:17:01 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910466731 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.910466731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.4114445895
Short name	T710
Test name
Test status
Simulation time	81932096 ps
CPU time	1.25 seconds
Started	Sep 09 05:16:51 AM UTC 24
Finished	Sep 09 05:16:54 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114445895 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.4114445895
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.761262107
Short name	T843
Test name
Test status
Simulation time	6293686558 ps
CPU time	46.54 seconds
Started	Sep 09 05:16:55 AM UTC 24
Finished	Sep 09 05:17:44 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761262107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.761262107
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.2613859056
Short name	T817
Test name
Test status
Simulation time	3128466561 ps
CPU time	32.64 seconds
Started	Sep 09 05:16:54 AM UTC 24
Finished	Sep 09 05:17:28 AM UTC 24
Peak memory	227280 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613859056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2613859056
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.1595904080
Short name	T715
Test name
Test status
Simulation time	31153750 ps
CPU time	1.2 seconds
Started	Sep 09 05:16:53 AM UTC 24
Finished	Sep 09 05:16:55 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595904080 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1595904080
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.2835837492
Short name	T738
Test name
Test status
Simulation time	22246645 ps
CPU time	1.18 seconds
Started	Sep 09 05:17:02 AM UTC 24
Finished	Sep 09 05:17:04 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835837492 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.2835837492
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.931728833
Short name	T735
Test name
Test status
Simulation time	27350913 ps
CPU time	1.38 seconds
Started	Sep 09 05:16:59 AM UTC 24
Finished	Sep 09 05:17:02 AM UTC 24
Peak memory	210520 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931728833 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.931728833
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.1171414239
Short name	T726
Test name
Test status
Simulation time	20036315 ps
CPU time	1.12 seconds
Started	Sep 09 05:16:57 AM UTC 24
Finished	Sep 09 05:16:59 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171414239 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1171414239
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.520147115
Short name	T736
Test name
Test status
Simulation time	62455609 ps
CPU time	1.47 seconds
Started	Sep 09 05:16:59 AM UTC 24
Finished	Sep 09 05:17:02 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520147115 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.520147115
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.667229665
Short name	T724
Test name
Test status
Simulation time	23884367 ps
CPU time	1.38 seconds
Started	Sep 09 05:16:56 AM UTC 24
Finished	Sep 09 05:16:58 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667229665 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.667229665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.1203184814
Short name	T764
Test name
Test status
Simulation time	1998422234 ps
CPU time	15.56 seconds
Started	Sep 09 05:16:56 AM UTC 24
Finished	Sep 09 05:17:13 AM UTC 24
Peak memory	210832 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1203184814 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.1203184814
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.3420277737
Short name	T732
Test name
Test status
Simulation time	257204673 ps
CPU time	3.34 seconds
Started	Sep 09 05:16:57 AM UTC 24
Finished	Sep 09 05:17:01 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420277737 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.3420277737
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.1725403242
Short name	T729
Test name
Test status
Simulation time	48447591 ps
CPU time	1.3 seconds
Started	Sep 09 05:16:58 AM UTC 24
Finished	Sep 09 05:17:01 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725403242 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.1725403242
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.718896200
Short name	T733
Test name
Test status
Simulation time	31469235 ps
CPU time	1.34 seconds
Started	Sep 09 05:16:59 AM UTC 24
Finished	Sep 09 05:17:02 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718896200 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.718896200
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.1171111750
Short name	T731
Test name
Test status
Simulation time	19895710 ps
CPU time	1.32 seconds
Started	Sep 09 05:16:58 AM UTC 24
Finished	Sep 09 05:17:01 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171111750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.1171111750
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.3013390565
Short name	T725
Test name
Test status
Simulation time	15300503 ps
CPU time	1.13 seconds
Started	Sep 09 05:16:57 AM UTC 24
Finished	Sep 09 05:16:59 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013390565 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3013390565
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.3856572492
Short name	T760
Test name
Test status
Simulation time	1517792272 ps
CPU time	9.02 seconds
Started	Sep 09 05:17:00 AM UTC 24
Finished	Sep 09 05:17:11 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856572492 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3856572492
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.1117387365
Short name	T723
Test name
Test status
Simulation time	20840808 ps
CPU time	1.35 seconds
Started	Sep 09 05:16:55 AM UTC 24
Finished	Sep 09 05:16:58 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117387365 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.1117387365
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.3533432446
Short name	T834
Test name
Test status
Simulation time	4410225666 ps
CPU time	33.15 seconds
Started	Sep 09 05:17:00 AM UTC 24
Finished	Sep 09 05:17:35 AM UTC 24
Peak memory	210744 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533432446 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.3533432446
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.2660068117
Short name	T847
Test name
Test status
Simulation time	7760250927 ps
CPU time	54.4 seconds
Started	Sep 09 05:17:00 AM UTC 24
Finished	Sep 09 05:17:57 AM UTC 24
Peak memory	227284 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660068117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.2660068117
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.2632511195
Short name	T727
Test name
Test status
Simulation time	30987895 ps
CPU time	1.48 seconds
Started	Sep 09 05:16:57 AM UTC 24
Finished	Sep 09 05:17:00 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632511195 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2632511195
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.3867080285
Short name	T752
Test name
Test status
Simulation time	22815122 ps
CPU time	1.19 seconds
Started	Sep 09 05:17:07 AM UTC 24
Finished	Sep 09 05:17:09 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867080285 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.3867080285
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.672225656
Short name	T749
Test name
Test status
Simulation time	23212873 ps
CPU time	1.37 seconds
Started	Sep 09 05:17:05 AM UTC 24
Finished	Sep 09 05:17:08 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672225656 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.672225656
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.2126273887
Short name	T744
Test name
Test status
Simulation time	12219292 ps
CPU time	1.09 seconds
Started	Sep 09 05:17:03 AM UTC 24
Finished	Sep 09 05:17:05 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126273887 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2126273887
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.4181538053
Short name	T748
Test name
Test status
Simulation time	32238718 ps
CPU time	1.25 seconds
Started	Sep 09 05:17:05 AM UTC 24
Finished	Sep 09 05:17:08 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181538053 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.4181538053
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.2604210881
Short name	T740
Test name
Test status
Simulation time	26033064 ps
CPU time	1.29 seconds
Started	Sep 09 05:17:02 AM UTC 24
Finished	Sep 09 05:17:04 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604210881 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.2604210881
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.4285999892
Short name	T751
Test name
Test status
Simulation time	322124503 ps
CPU time	5.97 seconds
Started	Sep 09 05:17:02 AM UTC 24
Finished	Sep 09 05:17:09 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285999892 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.4285999892
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.2030646497
Short name	T812
Test name
Test status
Simulation time	2427895602 ps
CPU time	23 seconds
Started	Sep 09 05:17:02 AM UTC 24
Finished	Sep 09 05:17:26 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030646497 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.2030646497
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.3571142472
Short name	T745
Test name
Test status
Simulation time	20856813 ps
CPU time	1.24 seconds
Started	Sep 09 05:17:03 AM UTC 24
Finished	Sep 09 05:17:05 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571142472 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.3571142472
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.2927399135
Short name	T747
Test name
Test status
Simulation time	49953185 ps
CPU time	1.44 seconds
Started	Sep 09 05:17:04 AM UTC 24
Finished	Sep 09 05:17:07 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927399135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.2927399135
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1268417857
Short name	T746
Test name
Test status
Simulation time	79854496 ps
CPU time	1.76 seconds
Started	Sep 09 05:17:03 AM UTC 24
Finished	Sep 09 05:17:06 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268417857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.1268417857
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.4175880782
Short name	T743
Test name
Test status
Simulation time	32999596 ps
CPU time	1.19 seconds
Started	Sep 09 05:17:03 AM UTC 24
Finished	Sep 09 05:17:05 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175880782 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.4175880782
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.4054042729
Short name	T756
Test name
Test status
Simulation time	275340709 ps
CPU time	3.08 seconds
Started	Sep 09 05:17:05 AM UTC 24
Finished	Sep 09 05:17:10 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054042729 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.4054042729
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.2583567360
Short name	T739
Test name
Test status
Simulation time	56648164 ps
CPU time	1.32 seconds
Started	Sep 09 05:17:02 AM UTC 24
Finished	Sep 09 05:17:04 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583567360 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.2583567360
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.376344158
Short name	T61
Test name
Test status
Simulation time	8192868246 ps
CPU time	35.89 seconds
Started	Sep 09 05:17:06 AM UTC 24
Finished	Sep 09 05:17:43 AM UTC 24
Peak memory	211028 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376344158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.376344158
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.3609800702
Short name	T841
Test name
Test status
Simulation time	2313401379 ps
CPU time	33.24 seconds
Started	Sep 09 05:17:06 AM UTC 24
Finished	Sep 09 05:17:40 AM UTC 24
Peak memory	220332 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609800702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.3609800702
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.3298532141
Short name	T742
Test name
Test status
Simulation time	31133715 ps
CPU time	1.17 seconds
Started	Sep 09 05:17:03 AM UTC 24
Finished	Sep 09 05:17:05 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298532141 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.3298532141
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.23567708
Short name	T766
Test name
Test status
Simulation time	15388131 ps
CPU time	1.1 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:17:13 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23567708 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.23567708
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1492200756
Short name	T767
Test name
Test status
Simulation time	44946593 ps
CPU time	1.35 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:17:13 AM UTC 24
Peak memory	210056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492200756 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.1492200756
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.25510634
Short name	T759
Test name
Test status
Simulation time	18696610 ps
CPU time	0.9 seconds
Started	Sep 09 05:17:08 AM UTC 24
Finished	Sep 09 05:17:10 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25510634 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.25510634
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.3734037028
Short name	T768
Test name
Test status
Simulation time	24684509 ps
CPU time	1.33 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:17:13 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734037028 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.3734037028
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.2081747665
Short name	T755
Test name
Test status
Simulation time	90041905 ps
CPU time	1.77 seconds
Started	Sep 09 05:17:07 AM UTC 24
Finished	Sep 09 05:17:10 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081747665 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2081747665
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.340623328
Short name	T822
Test name
Test status
Simulation time	2359430152 ps
CPU time	20.97 seconds
Started	Sep 09 05:17:07 AM UTC 24
Finished	Sep 09 05:17:29 AM UTC 24
Peak memory	210964 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340623328 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.340623328
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.2798395688
Short name	T786
Test name
Test status
Simulation time	1221260540 ps
CPU time	9.39 seconds
Started	Sep 09 05:17:08 AM UTC 24
Finished	Sep 09 05:17:18 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798395688 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.2798395688
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.3008997637
Short name	T762
Test name
Test status
Simulation time	14796951 ps
CPU time	1 seconds
Started	Sep 09 05:17:09 AM UTC 24
Finished	Sep 09 05:17:12 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008997637 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.3008997637
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.2301712001
Short name	T765
Test name
Test status
Simulation time	18658854 ps
CPU time	1.06 seconds
Started	Sep 09 05:17:10 AM UTC 24
Finished	Sep 09 05:17:13 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301712001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.2301712001
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1661517130
Short name	T763
Test name
Test status
Simulation time	87537762 ps
CPU time	1.22 seconds
Started	Sep 09 05:17:09 AM UTC 24
Finished	Sep 09 05:17:12 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661517130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.1661517130
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.3725432370
Short name	T758
Test name
Test status
Simulation time	15193519 ps
CPU time	1.08 seconds
Started	Sep 09 05:17:08 AM UTC 24
Finished	Sep 09 05:17:10 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725432370 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.3725432370
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.3221763683
Short name	T769
Test name
Test status
Simulation time	348550406 ps
CPU time	1.91 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:17:14 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3221763683 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.3221763683
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.2439454015
Short name	T753
Test name
Test status
Simulation time	24930997 ps
CPU time	1.34 seconds
Started	Sep 09 05:17:07 AM UTC 24
Finished	Sep 09 05:17:09 AM UTC 24
Peak memory	210084 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439454015 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2439454015
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.4063159626
Short name	T844
Test name
Test status
Simulation time	6171011480 ps
CPU time	34.98 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:17:47 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063159626 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.4063159626
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.3895446224
Short name	T851
Test name
Test status
Simulation time	5122429122 ps
CPU time	73.31 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:18:26 AM UTC 24
Peak memory	220268 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895446224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.3895446224
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.761514151
Short name	T761
Test name
Test status
Simulation time	127724840 ps
CPU time	1.74 seconds
Started	Sep 09 05:17:08 AM UTC 24
Finished	Sep 09 05:17:11 AM UTC 24
Peak memory	209004 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761514151 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.761514151
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.2590379456
Short name	T783
Test name
Test status
Simulation time	13715219 ps
CPU time	1.12 seconds
Started	Sep 09 05:17:16 AM UTC 24
Finished	Sep 09 05:17:18 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590379456 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.2590379456
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1093573000
Short name	T780
Test name
Test status
Simulation time	20732741 ps
CPU time	1.33 seconds
Started	Sep 09 05:17:15 AM UTC 24
Finished	Sep 09 05:17:17 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093573000 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.1093573000
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.1814405854
Short name	T774
Test name
Test status
Simulation time	11899016 ps
CPU time	1.04 seconds
Started	Sep 09 05:17:13 AM UTC 24
Finished	Sep 09 05:17:15 AM UTC 24
Peak memory	208872 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814405854 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1814405854
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.4102133133
Short name	T781
Test name
Test status
Simulation time	61978848 ps
CPU time	1.43 seconds
Started	Sep 09 05:17:15 AM UTC 24
Finished	Sep 09 05:17:17 AM UTC 24
Peak memory	210576 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102133133 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.4102133133
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.1588789292
Short name	T773
Test name
Test status
Simulation time	71639809 ps
CPU time	1.65 seconds
Started	Sep 09 05:17:12 AM UTC 24
Finished	Sep 09 05:17:15 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588789292 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1588789292
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.892636950
Short name	T775
Test name
Test status
Simulation time	381782945 ps
CPU time	2.16 seconds
Started	Sep 09 05:17:12 AM UTC 24
Finished	Sep 09 05:17:15 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892636950 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.892636950
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.3951902304
Short name	T813
Test name
Test status
Simulation time	1461900580 ps
CPU time	13.51 seconds
Started	Sep 09 05:17:12 AM UTC 24
Finished	Sep 09 05:17:27 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951902304 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.3951902304
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.3878829193
Short name	T778
Test name
Test status
Simulation time	117379610 ps
CPU time	2.2 seconds
Started	Sep 09 05:17:13 AM UTC 24
Finished	Sep 09 05:17:17 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878829193 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.3878829193
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3478306921
Short name	T779
Test name
Test status
Simulation time	24251400 ps
CPU time	1.18 seconds
Started	Sep 09 05:17:14 AM UTC 24
Finished	Sep 09 05:17:17 AM UTC 24
Peak memory	209788 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478306921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.3478306921
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1950857309
Short name	T776
Test name
Test status
Simulation time	72289282 ps
CPU time	1.29 seconds
Started	Sep 09 05:17:13 AM UTC 24
Finished	Sep 09 05:17:16 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950857309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.1950857309
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.3863709766
Short name	T772
Test name
Test status
Simulation time	13517977 ps
CPU time	0.92 seconds
Started	Sep 09 05:17:12 AM UTC 24
Finished	Sep 09 05:17:14 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863709766 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3863709766
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.2698850453
Short name	T794
Test name
Test status
Simulation time	1383378043 ps
CPU time	5.05 seconds
Started	Sep 09 05:17:15 AM UTC 24
Finished	Sep 09 05:17:21 AM UTC 24
Peak memory	210708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698850453 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2698850453
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.2745859224
Short name	T771
Test name
Test status
Simulation time	175631929 ps
CPU time	2.19 seconds
Started	Sep 09 05:17:11 AM UTC 24
Finished	Sep 09 05:17:14 AM UTC 24
Peak memory	210480 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745859224 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2745859224
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1750657297
Short name	T848
Test name
Test status
Simulation time	9700032015 ps
CPU time	41.4 seconds
Started	Sep 09 05:17:16 AM UTC 24
Finished	Sep 09 05:17:59 AM UTC 24
Peak memory	210720 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750657297 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1750657297
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.850822390
Short name	T845
Test name
Test status
Simulation time	2043277800 ps
CPU time	31.53 seconds
Started	Sep 09 05:17:15 AM UTC 24
Finished	Sep 09 05:17:48 AM UTC 24
Peak memory	224236 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850822390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.850822390
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.423193448
Short name	T777
Test name
Test status
Simulation time	78211889 ps
CPU time	1.48 seconds
Started	Sep 09 05:17:13 AM UTC 24
Finished	Sep 09 05:17:16 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423193448 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.423193448
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.865826897
Short name	T798
Test name
Test status
Simulation time	18131338 ps
CPU time	1.18 seconds
Started	Sep 09 05:17:20 AM UTC 24
Finished	Sep 09 05:17:22 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865826897 -assert no postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.865826897
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.84209850
Short name	T797
Test name
Test status
Simulation time	41879803 ps
CPU time	1.31 seconds
Started	Sep 09 05:17:20 AM UTC 24
Finished	Sep 09 05:17:22 AM UTC 24
Peak memory	209060 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84209850 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.84209850
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.315417662
Short name	T791
Test name
Test status
Simulation time	25515005 ps
CPU time	1.18 seconds
Started	Sep 09 05:17:18 AM UTC 24
Finished	Sep 09 05:17:20 AM UTC 24
Peak memory	208664 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315417662 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.315417662
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.3560465869
Short name	T796
Test name
Test status
Simulation time	39846596 ps
CPU time	1.29 seconds
Started	Sep 09 05:17:20 AM UTC 24
Finished	Sep 09 05:17:22 AM UTC 24
Peak memory	210136 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560465869 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.3560465869
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.3559584951
Short name	T785
Test name
Test status
Simulation time	37737160 ps
CPU time	1.33 seconds
Started	Sep 09 05:17:16 AM UTC 24
Finished	Sep 09 05:17:18 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559584951 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3559584951
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.879808824
Short name	T810
Test name
Test status
Simulation time	1735164724 ps
CPU time	7.89 seconds
Started	Sep 09 05:17:16 AM UTC 24
Finished	Sep 09 05:17:25 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879808824 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.879808824
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.2498515449
Short name	T837
Test name
Test status
Simulation time	2417221172 ps
CPU time	19.73 seconds
Started	Sep 09 05:17:17 AM UTC 24
Finished	Sep 09 05:17:38 AM UTC 24
Peak memory	210772 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498515449 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.2498515449
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.1679474316
Short name	T792
Test name
Test status
Simulation time	55503117 ps
CPU time	1.31 seconds
Started	Sep 09 05:17:18 AM UTC 24
Finished	Sep 09 05:17:21 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679474316 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.1679474316
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.1891284004
Short name	T790
Test name
Test status
Simulation time	23290389 ps
CPU time	1.05 seconds
Started	Sep 09 05:17:18 AM UTC 24
Finished	Sep 09 05:17:20 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891284004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.1891284004
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.4289834596
Short name	T793
Test name
Test status
Simulation time	26783928 ps
CPU time	1.27 seconds
Started	Sep 09 05:17:18 AM UTC 24
Finished	Sep 09 05:17:21 AM UTC 24
Peak memory	209064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4289834596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.4289834596
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.850312359
Short name	T787
Test name
Test status
Simulation time	18449648 ps
CPU time	1.19 seconds
Started	Sep 09 05:17:17 AM UTC 24
Finished	Sep 09 05:17:19 AM UTC 24
Peak memory	210148 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850312359 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.850312359
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.875583421
Short name	T804
Test name
Test status
Simulation time	874725224 ps
CPU time	3.49 seconds
Started	Sep 09 05:17:20 AM UTC 24
Finished	Sep 09 05:17:24 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875583421 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.875583421
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.2300547124
Short name	T784
Test name
Test status
Simulation time	20643243 ps
CPU time	1.31 seconds
Started	Sep 09 05:17:16 AM UTC 24
Finished	Sep 09 05:17:18 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300547124 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2300547124
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3834141747
Short name	T801
Test name
Test status
Simulation time	187509814 ps
CPU time	2.54 seconds
Started	Sep 09 05:17:20 AM UTC 24
Finished	Sep 09 05:17:23 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834141747 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.3834141747
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.2857962917
Short name	T856
Test name
Test status
Simulation time	14460380034 ps
CPU time	91.92 seconds
Started	Sep 09 05:17:20 AM UTC 24
Finished	Sep 09 05:18:54 AM UTC 24
Peak memory	224388 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857962917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.2857962917
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.1720436461
Short name	T789
Test name
Test status
Simulation time	68672524 ps
CPU time	1.6 seconds
Started	Sep 09 05:17:17 AM UTC 24
Finished	Sep 09 05:17:20 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720436461 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1720436461
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.1032148326
Short name	T814
Test name
Test status
Simulation time	14572325 ps
CPU time	1.19 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:17:27 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032148326 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.1032148326
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2490833144
Short name	T807
Test name
Test status
Simulation time	39671623 ps
CPU time	1.01 seconds
Started	Sep 09 05:17:23 AM UTC 24
Finished	Sep 09 05:17:25 AM UTC 24
Peak memory	210104 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490833144 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.2490833144
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.2262866174
Short name	T805
Test name
Test status
Simulation time	41493474 ps
CPU time	1.07 seconds
Started	Sep 09 05:17:22 AM UTC 24
Finished	Sep 09 05:17:24 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262866174 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2262866174
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.538597842
Short name	T811
Test name
Test status
Simulation time	69023081 ps
CPU time	1.12 seconds
Started	Sep 09 05:17:24 AM UTC 24
Finished	Sep 09 05:17:26 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538597842 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.538597842
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.2491403260
Short name	T800
Test name
Test status
Simulation time	24202312 ps
CPU time	1.27 seconds
Started	Sep 09 05:17:21 AM UTC 24
Finished	Sep 09 05:17:23 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491403260 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2491403260
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.2732765121
Short name	T828
Test name
Test status
Simulation time	1346112308 ps
CPU time	7.95 seconds
Started	Sep 09 05:17:21 AM UTC 24
Finished	Sep 09 05:17:30 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2732765121 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.2732765121
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.1672690890
Short name	T823
Test name
Test status
Simulation time	1594838270 ps
CPU time	7.05 seconds
Started	Sep 09 05:17:21 AM UTC 24
Finished	Sep 09 05:17:29 AM UTC 24
Peak memory	210584 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672690890 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.1672690890
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.400931501
Short name	T809
Test name
Test status
Simulation time	80611169 ps
CPU time	1.65 seconds
Started	Sep 09 05:17:22 AM UTC 24
Finished	Sep 09 05:17:25 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400931501 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.400931501
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.2918671346
Short name	T808
Test name
Test status
Simulation time	40703880 ps
CPU time	1.23 seconds
Started	Sep 09 05:17:22 AM UTC 24
Finished	Sep 09 05:17:25 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918671346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.2918671346
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.3702411715
Short name	T806
Test name
Test status
Simulation time	22943881 ps
CPU time	0.98 seconds
Started	Sep 09 05:17:22 AM UTC 24
Finished	Sep 09 05:17:24 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702411715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.3702411715
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.2874171206
Short name	T802
Test name
Test status
Simulation time	108197163 ps
CPU time	1.31 seconds
Started	Sep 09 05:17:21 AM UTC 24
Finished	Sep 09 05:17:24 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874171206 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2874171206
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.3110734684
Short name	T833
Test name
Test status
Simulation time	1149501861 ps
CPU time	6.82 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:17:33 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110734684 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.3110734684
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.3929221162
Short name	T799
Test name
Test status
Simulation time	16168498 ps
CPU time	1.09 seconds
Started	Sep 09 05:17:21 AM UTC 24
Finished	Sep 09 05:17:23 AM UTC 24
Peak memory	210204 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3929221162 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3929221162
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3646886137
Short name	T849
Test name
Test status
Simulation time	5860416934 ps
CPU time	35.95 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:18:02 AM UTC 24
Peak memory	211000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646886137 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3646886137
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.650682702
Short name	T857
Test name
Test status
Simulation time	20288037527 ps
CPU time	92.24 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:18:59 AM UTC 24
Peak memory	226412 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650682702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.650682702
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.4264073945
Short name	T803
Test name
Test status
Simulation time	30974074 ps
CPU time	1.34 seconds
Started	Sep 09 05:17:21 AM UTC 24
Finished	Sep 09 05:17:24 AM UTC 24
Peak memory	210144 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264073945 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.4264073945
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.4174706040
Short name	T829
Test name
Test status
Simulation time	48719554 ps
CPU time	1.13 seconds
Started	Sep 09 05:17:29 AM UTC 24
Finished	Sep 09 05:17:31 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174706040 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.4174706040
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.3094464846
Short name	T827
Test name
Test status
Simulation time	52043233 ps
CPU time	1.39 seconds
Started	Sep 09 05:17:28 AM UTC 24
Finished	Sep 09 05:17:30 AM UTC 24
Peak memory	210224 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3094464846 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.3094464846
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.4145921779
Short name	T818
Test name
Test status
Simulation time	24669937 ps
CPU time	1.14 seconds
Started	Sep 09 05:17:26 AM UTC 24
Finished	Sep 09 05:17:28 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145921779 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.4145921779
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.2435748010
Short name	T825
Test name
Test status
Simulation time	19468440 ps
CPU time	1.26 seconds
Started	Sep 09 05:17:28 AM UTC 24
Finished	Sep 09 05:17:30 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435748010 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.2435748010
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.2207257505
Short name	T815
Test name
Test status
Simulation time	37919002 ps
CPU time	1.21 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:17:27 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207257505 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2207257505
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.145634084
Short name	T835
Test name
Test status
Simulation time	2229469565 ps
CPU time	11.51 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:17:38 AM UTC 24
Peak memory	210904 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145634084 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.145634084
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.2680778697
Short name	T840
Test name
Test status
Simulation time	2095719421 ps
CPU time	11.53 seconds
Started	Sep 09 05:17:26 AM UTC 24
Finished	Sep 09 05:17:39 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680778697 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.2680778697
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.3875265611
Short name	T820
Test name
Test status
Simulation time	14187573 ps
CPU time	1.14 seconds
Started	Sep 09 05:17:26 AM UTC 24
Finished	Sep 09 05:17:28 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875265611 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.3875265611
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3540932357
Short name	T826
Test name
Test status
Simulation time	29002936 ps
CPU time	1.35 seconds
Started	Sep 09 05:17:28 AM UTC 24
Finished	Sep 09 05:17:30 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540932357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.3540932357
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.2246190034
Short name	T824
Test name
Test status
Simulation time	44237772 ps
CPU time	1.1 seconds
Started	Sep 09 05:17:27 AM UTC 24
Finished	Sep 09 05:17:30 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246190034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.2246190034
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.3229156434
Short name	T819
Test name
Test status
Simulation time	48503801 ps
CPU time	1.18 seconds
Started	Sep 09 05:17:26 AM UTC 24
Finished	Sep 09 05:17:28 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229156434 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3229156434
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.334167572
Short name	T838
Test name
Test status
Simulation time	797203295 ps
CPU time	8.15 seconds
Started	Sep 09 05:17:29 AM UTC 24
Finished	Sep 09 05:17:38 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334167572 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.334167572
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.3850200446
Short name	T816
Test name
Test status
Simulation time	76741676 ps
CPU time	1.35 seconds
Started	Sep 09 05:17:25 AM UTC 24
Finished	Sep 09 05:17:27 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850200446 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3850200446
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.4050940320
Short name	T853
Test name
Test status
Simulation time	8162852045 ps
CPU time	61.77 seconds
Started	Sep 09 05:17:29 AM UTC 24
Finished	Sep 09 05:18:32 AM UTC 24
Peak memory	211056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050940320 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.4050940320
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.1248120714
Short name	T854
Test name
Test status
Simulation time	5060375173 ps
CPU time	70.23 seconds
Started	Sep 09 05:17:29 AM UTC 24
Finished	Sep 09 05:18:41 AM UTC 24
Peak memory	224384 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248120714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.1248120714
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.3688225915
Short name	T821
Test name
Test status
Simulation time	32624099 ps
CPU time	1.5 seconds
Started	Sep 09 05:17:26 AM UTC 24
Finished	Sep 09 05:17:29 AM UTC 24
Peak memory	208992 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688225915 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3688225915
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.45281835
Short name	T204
Test name
Test status
Simulation time	16085710 ps
CPU time	1.11 seconds
Started	Sep 09 05:13:45 AM UTC 24
Finished	Sep 09 05:13:47 AM UTC 24
Peak memory	210212 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45281835 -assert nop ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.45281835
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.3038056612
Short name	T99
Test name
Test status
Simulation time	54368544 ps
CPU time	1.51 seconds
Started	Sep 09 05:13:45 AM UTC 24
Finished	Sep 09 05:13:47 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038056612 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.3038056612
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.1639843065
Short name	T172
Test name
Test status
Simulation time	45824680 ps
CPU time	1.16 seconds
Started	Sep 09 05:13:42 AM UTC 24
Finished	Sep 09 05:13:44 AM UTC 24
Peak memory	209128 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639843065 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1639843065
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.2593822905
Short name	T205
Test name
Test status
Simulation time	38426023 ps
CPU time	1.41 seconds
Started	Sep 09 05:13:45 AM UTC 24
Finished	Sep 09 05:13:47 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593822905 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.2593822905
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.479994202
Short name	T200
Test name
Test status
Simulation time	45420374 ps
CPU time	1.31 seconds
Started	Sep 09 05:13:41 AM UTC 24
Finished	Sep 09 05:13:43 AM UTC 24
Peak memory	210024 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479994202 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.479994202
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.2970996557
Short name	T12
Test name
Test status
Simulation time	933095154 ps
CPU time	8.61 seconds
Started	Sep 09 05:13:41 AM UTC 24
Finished	Sep 09 05:13:51 AM UTC 24
Peak memory	210276 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970996557 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2970996557
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.1985992764
Short name	T226
Test name
Test status
Simulation time	1935244933 ps
CPU time	15.55 seconds
Started	Sep 09 05:13:41 AM UTC 24
Finished	Sep 09 05:13:58 AM UTC 24
Peak memory	210392 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985992764 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.1985992764
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.960726715
Short name	T203
Test name
Test status
Simulation time	81018234 ps
CPU time	1.26 seconds
Started	Sep 09 05:13:43 AM UTC 24
Finished	Sep 09 05:13:46 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960726715 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.960726715
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.546060898
Short name	T182
Test name
Test status
Simulation time	19959740 ps
CPU time	1.05 seconds
Started	Sep 09 05:13:44 AM UTC 24
Finished	Sep 09 05:13:46 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546060898 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.546060898
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1885936469
Short name	T202
Test name
Test status
Simulation time	14658400 ps
CPU time	0.95 seconds
Started	Sep 09 05:13:43 AM UTC 24
Finished	Sep 09 05:13:45 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885936469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.1885936469
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.2018455470
Short name	T154
Test name
Test status
Simulation time	37357362 ps
CPU time	1.08 seconds
Started	Sep 09 05:13:42 AM UTC 24
Finished	Sep 09 05:13:44 AM UTC 24
Peak memory	210064 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018455470 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.2018455470
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.3256818117
Short name	T214
Test name
Test status
Simulation time	781320220 ps
CPU time	6.16 seconds
Started	Sep 09 05:13:45 AM UTC 24
Finished	Sep 09 05:13:52 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256818117 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3256818117
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.441403536
Short name	T201
Test name
Test status
Simulation time	69099380 ps
CPU time	1.58 seconds
Started	Sep 09 05:13:41 AM UTC 24
Finished	Sep 09 05:13:44 AM UTC 24
Peak memory	209736 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441403536 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.441403536
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.2565683613
Short name	T17
Test name
Test status
Simulation time	2669004140 ps
CPU time	17.04 seconds
Started	Sep 09 05:13:45 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	210708 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565683613 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.2565683613
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.1782980055
Short name	T81
Test name
Test status
Simulation time	5401366361 ps
CPU time	95.26 seconds
Started	Sep 09 05:13:45 AM UTC 24
Finished	Sep 09 05:15:22 AM UTC 24
Peak memory	220484 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782980055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1782980055
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.3972782295
Short name	T198
Test name
Test status
Simulation time	31693663 ps
CPU time	1.33 seconds
Started	Sep 09 05:13:42 AM UTC 24
Finished	Sep 09 05:13:44 AM UTC 24
Peak memory	208700 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972782295 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3972782295
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.3692713182
Short name	T216
Test name
Test status
Simulation time	55654160 ps
CPU time	1.43 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:13:53 AM UTC 24
Peak memory	209980 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692713182 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.3692713182
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3228590230
Short name	T100
Test name
Test status
Simulation time	24106836 ps
CPU time	1.34 seconds
Started	Sep 09 05:13:50 AM UTC 24
Finished	Sep 09 05:13:52 AM UTC 24
Peak memory	209072 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228590230 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_handshake_intersig_mubi.3228590230
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_clk_status.2259879540
Short name	T173
Test name
Test status
Simulation time	56430327 ps
CPU time	1.01 seconds
Started	Sep 09 05:13:48 AM UTC 24
Finished	Sep 09 05:13:50 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259879540 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2259879540
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_div_intersig_mubi.621115569
Short name	T213
Test name
Test status
Simulation time	64815646 ps
CPU time	1.09 seconds
Started	Sep 09 05:13:50 AM UTC 24
Finished	Sep 09 05:13:52 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621115569 -ass ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_div_intersig_mubi.621115569
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.2209784781
Short name	T209
Test name
Test status
Simulation time	64077184 ps
CPU time	1.54 seconds
Started	Sep 09 05:13:46 AM UTC 24
Finished	Sep 09 05:13:49 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209784781 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2209784781
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.3152975069
Short name	T15
Test name
Test status
Simulation time	1516025603 ps
CPU time	13.92 seconds
Started	Sep 09 05:13:46 AM UTC 24
Finished	Sep 09 05:14:01 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152975069 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3152975069
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.3903012873
Short name	T232
Test name
Test status
Simulation time	1703979155 ps
CPU time	12.52 seconds
Started	Sep 09 05:13:46 AM UTC 24
Finished	Sep 09 05:14:00 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903012873 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.3903012873
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_idle_intersig_mubi.2666186132
Short name	T211
Test name
Test status
Simulation time	25868987 ps
CPU time	1.16 seconds
Started	Sep 09 05:13:48 AM UTC 24
Finished	Sep 09 05:13:50 AM UTC 24
Peak memory	208888 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666186132 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.2666186132
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2608655275
Short name	T212
Test name
Test status
Simulation time	77015812 ps
CPU time	1.24 seconds
Started	Sep 09 05:13:48 AM UTC 24
Finished	Sep 09 05:13:51 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608655275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_clk_byp_req_intersig_mubi.2608655275
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.157744506
Short name	T215
Test name
Test status
Simulation time	257835508 ps
CPU time	2.55 seconds
Started	Sep 09 05:13:48 AM UTC 24
Finished	Sep 09 05:13:52 AM UTC 24
Peak memory	210440 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157744506 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_lc_ctrl_intersig_mubi.157744506
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.2469354475
Short name	T208
Test name
Test status
Simulation time	45952881 ps
CPU time	1.24 seconds
Started	Sep 09 05:13:46 AM UTC 24
Finished	Sep 09 05:13:48 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2469354475 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2469354475
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.1198971953
Short name	T119
Test name
Test status
Simulation time	944078097 ps
CPU time	3.93 seconds
Started	Sep 09 05:13:50 AM UTC 24
Finished	Sep 09 05:13:54 AM UTC 24
Peak memory	210612 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198971953 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.1198971953
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.3639162958
Short name	T207
Test name
Test status
Simulation time	36530692 ps
CPU time	1.31 seconds
Started	Sep 09 05:13:46 AM UTC 24
Finished	Sep 09 05:13:48 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639162958 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.3639162958
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.3922286087
Short name	T219
Test name
Test status
Simulation time	71180537 ps
CPU time	2.21 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:13:54 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922286087 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.3922286087
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.3407866817
Short name	T82
Test name
Test status
Simulation time	7617132282 ps
CPU time	90.54 seconds
Started	Sep 09 05:13:50 AM UTC 24
Finished	Sep 09 05:15:22 AM UTC 24
Peak memory	220588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407866817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.3407866817
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.3188829038
Short name	T210
Test name
Test status
Simulation time	27690037 ps
CPU time	1.19 seconds
Started	Sep 09 05:13:47 AM UTC 24
Finished	Sep 09 05:13:49 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188829038 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3188829038
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_alert_test.1104656036
Short name	T227
Test name
Test status
Simulation time	31721857 ps
CPU time	1.04 seconds
Started	Sep 09 05:13:56 AM UTC 24
Finished	Sep 09 05:13:58 AM UTC 24
Peak memory	209908 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104656036 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.1104656036
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3441563296
Short name	T101
Test name
Test status
Simulation time	28325097 ps
CPU time	1.13 seconds
Started	Sep 09 05:13:53 AM UTC 24
Finished	Sep 09 05:13:56 AM UTC 24
Peak memory	210044 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441563296 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.3441563296
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.436638604
Short name	T174
Test name
Test status
Simulation time	62305253 ps
CPU time	1.34 seconds
Started	Sep 09 05:13:52 AM UTC 24
Finished	Sep 09 05:13:55 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436638604 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.436638604
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.3251314882
Short name	T224
Test name
Test status
Simulation time	15281455 ps
CPU time	1.13 seconds
Started	Sep 09 05:13:55 AM UTC 24
Finished	Sep 09 05:13:57 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251314882 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.3251314882
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.3662183510
Short name	T218
Test name
Test status
Simulation time	75062492 ps
CPU time	1.65 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:13:54 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662183510 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3662183510
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.846871833
Short name	T14
Test name
Test status
Simulation time	1286632334 ps
CPU time	8.09 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:14:00 AM UTC 24
Peak memory	210368 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846871833 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.846871833
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.1596379140
Short name	T225
Test name
Test status
Simulation time	534588654 ps
CPU time	4.75 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:13:57 AM UTC 24
Peak memory	210588 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596379140 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.1596379140
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.1532427661
Short name	T221
Test name
Test status
Simulation time	98699427 ps
CPU time	1.88 seconds
Started	Sep 09 05:13:52 AM UTC 24
Finished	Sep 09 05:13:55 AM UTC 24
Peak memory	210100 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532427661 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.1532427661
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1579632089
Short name	T223
Test name
Test status
Simulation time	112726120 ps
CPU time	1.89 seconds
Started	Sep 09 05:13:53 AM UTC 24
Finished	Sep 09 05:13:57 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579632089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.1579632089
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3790531731
Short name	T222
Test name
Test status
Simulation time	22769041 ps
CPU time	1.14 seconds
Started	Sep 09 05:13:53 AM UTC 24
Finished	Sep 09 05:13:56 AM UTC 24
Peak memory	209916 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790531731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.3790531731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.3469391728
Short name	T217
Test name
Test status
Simulation time	19161230 ps
CPU time	1.18 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:13:53 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469391728 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3469391728
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.3646706828
Short name	T243
Test name
Test status
Simulation time	962287218 ps
CPU time	8.75 seconds
Started	Sep 09 05:13:55 AM UTC 24
Finished	Sep 09 05:14:04 AM UTC 24
Peak memory	210804 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646706828 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3646706828
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.2067348387
Short name	T147
Test name
Test status
Simulation time	283030654 ps
CPU time	2.75 seconds
Started	Sep 09 05:13:51 AM UTC 24
Finished	Sep 09 05:13:55 AM UTC 24
Peak memory	210300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067348387 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2067348387
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.1515030024
Short name	T341
Test name
Test status
Simulation time	6781358174 ps
CPU time	49.58 seconds
Started	Sep 09 05:13:55 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	210796 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515030024 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1515030024
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.654444568
Short name	T185
Test name
Test status
Simulation time	34464692818 ps
CPU time	136.46 seconds
Started	Sep 09 05:13:55 AM UTC 24
Finished	Sep 09 05:16:13 AM UTC 24
Peak memory	220300 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654444568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log / dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.654444568
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.1896206183
Short name	T220
Test name
Test status
Simulation time	117925898 ps
CPU time	1.75 seconds
Started	Sep 09 05:13:52 AM UTC 24
Finished	Sep 09 05:13:55 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896206183 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1896206183
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.3889325787
Short name	T237
Test name
Test status
Simulation time	24815966 ps
CPU time	0.92 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	210056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889325787 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.3889325787
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2397978458
Short name	T102
Test name
Test status
Simulation time	15941155 ps
CPU time	0.68 seconds
Started	Sep 09 05:13:58 AM UTC 24
Finished	Sep 09 05:14:00 AM UTC 24
Peak memory	210164 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397978458 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.2397978458
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.867532058
Short name	T175
Test name
Test status
Simulation time	16825879 ps
CPU time	0.98 seconds
Started	Sep 09 05:13:57 AM UTC 24
Finished	Sep 09 05:13:59 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867532058 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.867532058
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.3514868315
Short name	T236
Test name
Test status
Simulation time	55761360 ps
CPU time	1.05 seconds
Started	Sep 09 05:13:59 AM UTC 24
Finished	Sep 09 05:14:02 AM UTC 24
Peak memory	210152 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514868315 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.3514868315
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_extclk.1682917433
Short name	T183
Test name
Test status
Simulation time	23955930 ps
CPU time	0.92 seconds
Started	Sep 09 05:13:56 AM UTC 24
Finished	Sep 09 05:13:58 AM UTC 24
Peak memory	210156 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682917433 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1682917433
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.40852731
Short name	T16
Test name
Test status
Simulation time	1254467503 ps
CPU time	4.99 seconds
Started	Sep 09 05:13:56 AM UTC 24
Finished	Sep 09 05:14:02 AM UTC 24
Peak memory	210552 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40852731 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.40852731
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.1798072160
Short name	T229
Test name
Test status
Simulation time	294831652 ps
CPU time	2.08 seconds
Started	Sep 09 05:13:56 AM UTC 24
Finished	Sep 09 05:13:59 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798072160 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.1798072160
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.4142622967
Short name	T233
Test name
Test status
Simulation time	34777100 ps
CPU time	1.61 seconds
Started	Sep 09 05:13:57 AM UTC 24
Finished	Sep 09 05:14:00 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142622967 -a ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.4142622967
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1309350147
Short name	T234
Test name
Test status
Simulation time	16635345 ps
CPU time	1.19 seconds
Started	Sep 09 05:13:58 AM UTC 24
Finished	Sep 09 05:14:01 AM UTC 24
Peak memory	210160 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309350147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.1309350147
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3795641243
Short name	T235
Test name
Test status
Simulation time	39084269 ps
CPU time	1.28 seconds
Started	Sep 09 05:13:58 AM UTC 24
Finished	Sep 09 05:14:01 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795641243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.3795641243
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.1943481678
Short name	T230
Test name
Test status
Simulation time	26047673 ps
CPU time	1.14 seconds
Started	Sep 09 05:13:57 AM UTC 24
Finished	Sep 09 05:14:00 AM UTC 24
Peak memory	210208 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943481678 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1943481678
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.1016123265
Short name	T247
Test name
Test status
Simulation time	885267439 ps
CPU time	4.83 seconds
Started	Sep 09 05:13:59 AM UTC 24
Finished	Sep 09 05:14:06 AM UTC 24
Peak memory	210516 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016123265 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1016123265
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_smoke.837993582
Short name	T228
Test name
Test status
Simulation time	34992004 ps
CPU time	1.18 seconds
Started	Sep 09 05:13:56 AM UTC 24
Finished	Sep 09 05:13:58 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837993582 -assert nopostproc +UVM_TESTNAME=clk mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.837993582
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.547916947
Short name	T342
Test name
Test status
Simulation time	4988507436 ps
CPU time	43.59 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:46 AM UTC 24
Peak memory	210740 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547916947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.547916947
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.5920200
Short name	T79
Test name
Test status
Simulation time	10231238850 ps
CPU time	64.26 seconds
Started	Sep 09 05:13:59 AM UTC 24
Finished	Sep 09 05:15:06 AM UTC 24
Peak memory	220524 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5920200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.clkmgr_stress_all_with_rand_reset.5920200
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.3600058356
Short name	T231
Test name
Test status
Simulation time	32682167 ps
CPU time	1.26 seconds
Started	Sep 09 05:13:57 AM UTC 24
Finished	Sep 09 05:14:00 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600058356 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3600058356
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.3608139799
Short name	T250
Test name
Test status
Simulation time	48648385 ps
CPU time	1.25 seconds
Started	Sep 09 05:14:04 AM UTC 24
Finished	Sep 09 05:14:07 AM UTC 24
Peak memory	210040 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608139799 -assert n opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.3608139799
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.916580756
Short name	T246
Test name
Test status
Simulation time	29196250 ps
CPU time	1.15 seconds
Started	Sep 09 05:14:03 AM UTC 24
Finished	Sep 09 05:14:05 AM UTC 24
Peak memory	209068 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916580756 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.916580756
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.76873557
Short name	T176
Test name
Test status
Simulation time	14957128 ps
CPU time	0.88 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	209188 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76873557 -assert nopostproc +UVM_TESTNAME=clkm gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.76873557
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.1268730553
Short name	T248
Test name
Test status
Simulation time	66521269 ps
CPU time	1.57 seconds
Started	Sep 09 05:14:03 AM UTC 24
Finished	Sep 09 05:14:06 AM UTC 24
Peak memory	210092 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268730553 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.1268730553
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_extclk.3231771032
Short name	T238
Test name
Test status
Simulation time	24871288 ps
CPU time	1.14 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	209000 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231771032 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.3231771032
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_extclk/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2169562316
Short name	T18
Test name
Test status
Simulation time	922777762 ps
CPU time	8.78 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:11 AM UTC 24
Peak memory	210360 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169562316 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2169562316
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency_timeout.2517066519
Short name	T251
Test name
Test status
Simulation time	260937330 ps
CPU time	4.7 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:07 AM UTC 24
Peak memory	210396 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517066519 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.2517066519
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.115859599
Short name	T242
Test name
Test status
Simulation time	52429515 ps
CPU time	1.32 seconds
Started	Sep 09 05:14:02 AM UTC 24
Finished	Sep 09 05:14:04 AM UTC 24
Peak memory	209008 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115859599 -as sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.115859599
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.478304394
Short name	T245
Test name
Test status
Simulation time	50479554 ps
CPU time	1.28 seconds
Started	Sep 09 05:14:02 AM UTC 24
Finished	Sep 09 05:14:05 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478304394 - assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.478304394
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.2958661978
Short name	T244
Test name
Test status
Simulation time	16451535 ps
CPU time	1.2 seconds
Started	Sep 09 05:14:02 AM UTC 24
Finished	Sep 09 05:14:05 AM UTC 24
Peak memory	210036 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958661978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.2958661978
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.3775508584
Short name	T240
Test name
Test status
Simulation time	66888875 ps
CPU time	1.2 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	210216 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775508584 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3775508584
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.1177725970
Short name	T260
Test name
Test status
Simulation time	397845205 ps
CPU time	4.14 seconds
Started	Sep 09 05:14:04 AM UTC 24
Finished	Sep 09 05:14:09 AM UTC 24
Peak memory	210364 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177725970 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1177725970
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_smoke.3818018083
Short name	T239
Test name
Test status
Simulation time	21301539 ps
CPU time	1.28 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	209976 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818018083 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3818018083
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_smoke/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.2168521851
Short name	T371
Test name
Test status
Simulation time	12176831683 ps
CPU time	50.18 seconds
Started	Sep 09 05:14:04 AM UTC 24
Finished	Sep 09 05:14:56 AM UTC 24
Peak memory	211056 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168521851 -asser t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.2168521851
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.3182568147
Short name	T60
Test name
Test status
Simulation time	15813200922 ps
CPU time	140.77 seconds
Started	Sep 09 05:14:04 AM UTC 24
Finished	Sep 09 05:16:28 AM UTC 24
Peak memory	220288 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182568147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3182568147
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest

Test location	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/coverage/default/9.clkmgr_trans.1200311779
Short name	T241
Test name
Test status
Simulation time	30678978 ps
CPU time	1.21 seconds
Started	Sep 09 05:14:01 AM UTC 24
Finished	Sep 09 05:14:03 AM UTC 24
Peak memory	210096 kb
Host	riverbear.c.edafarm-workstations-prod.internal
User	miguelosorio
Command	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200311779 -assert nopostproc +UVM_TESTNAME=cl kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_08/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1200311779
Directory	/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/9.clkmgr_trans/latest

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