Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	212967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

495578

1

T4

12

T5

22

T6

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	199881	1			T4	13		T5	42		T27	8
values[0x0]	241504	1			T4	12		T5	17		T6	7
values[0x1]	267160	1			T4	15		T5	22		T6	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	146827	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

561718

1

T4

15

T5

31

T6

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2934	1			T4	1		T11	5		T122	4
valid_sources[0x01]	2777	1			T5	2		T6	1		T56	1
valid_sources[0x02]	2656	1			T32	2		T46	1		T58	1
valid_sources[0x03]	3007	1			T59	1		T2	1		T122	2
valid_sources[0x04]	2881	1			T58	1		T59	1		T11	4
valid_sources[0x05]	2718	1			T5	1		T87	3		T2	1
valid_sources[0x06]	2525	1			T44	1		T2	2		T11	3
valid_sources[0x07]	2203	1			T5	1		T6	1		T59	1
valid_sources[0x08]	2554	1			T59	1		T2	6		T24	3
valid_sources[0x09]	2609	1			T4	1		T105	1		T2	1
valid_sources[0x0a]	4688	1			T49	2		T56	1		T59	1
valid_sources[0x0b]	2840	1			T59	1		T2	1		T182	2
valid_sources[0x0c]	2543	1			T87	1		T2	1		T24	1
valid_sources[0x0d]	3147	1			T5	1		T2	3		T122	1
valid_sources[0x0e]	2184	1			T5	1		T59	1		T44	1
valid_sources[0x0f]	2232	1			T4	1		T2	3		T153	1
valid_sources[0x10]	2952	1			T4	2		T5	1		T2	2
valid_sources[0x11]	2822	1			T56	1		T58	1		T59	1
valid_sources[0x12]	2906	1			T5	1		T59	1		T2	3
valid_sources[0x13]	2729	1			T46	1		T2	1		T10	1
valid_sources[0x14]	2884	1			T5	2		T46	2		T43	1
valid_sources[0x15]	2544	1			T2	6		T19	4		T55	1
valid_sources[0x16]	2958	1			T87	1		T58	1		T59	2
valid_sources[0x17]	2464	1			T5	1		T49	9		T59	1
valid_sources[0x18]	3407	1			T44	1		T2	4		T9	3
valid_sources[0x19]	2880	1			T58	1		T2	2		T23	11
valid_sources[0x1a]	2865	1			T5	1		T49	5		T59	1
valid_sources[0x1b]	4609	1			T27	3		T105	1		T56	1
valid_sources[0x1c]	2823	1			T105	1		T59	3		T2	1
valid_sources[0x1d]	3774	1			T58	2		T44	1		T2	3
valid_sources[0x1e]	2337	1			T4	1		T58	1		T2	1
valid_sources[0x1f]	2538	1			T31	1		T49	3		T87	1
valid_sources[0x20]	2332	1			T87	1		T55	1		T11	13
valid_sources[0x21]	2867	1			T31	1		T87	1		T59	1
valid_sources[0x22]	2515	1			T2	2		T182	1		T10	1
valid_sources[0x23]	2559	1			T4	1		T43	1		T44	1
valid_sources[0x24]	3467	1			T56	1		T2	2		T24	1
valid_sources[0x25]	3167	1			T4	1		T5	1		T87	6
valid_sources[0x26]	2253	1			T5	1		T2	4		T122	1
valid_sources[0x27]	3218	1			T4	2		T5	1		T59	1
valid_sources[0x28]	2536	1			T6	1		T31	1		T2	2
valid_sources[0x29]	2934	1			T46	9		T43	1		T2	3
valid_sources[0x2a]	2235	1			T44	1		T2	1		T11	3
valid_sources[0x2b]	1966	1			T44	1		T2	4		T55	1
valid_sources[0x2c]	2896	1			T27	1		T44	1		T2	3
valid_sources[0x2d]	2923	1			T87	1		T43	1		T2	5
valid_sources[0x2e]	2336	1			T20	2		T50	1		T9	1
valid_sources[0x2f]	2192	1			T33	1		T58	1		T59	2
valid_sources[0x30]	3025	1			T5	1		T59	1		T2	2
valid_sources[0x31]	2570	1			T2	2		T11	4		T122	3
valid_sources[0x32]	2412	1			T49	5		T59	1		T2	2
valid_sources[0x33]	2845	1			T2	5		T55	1		T38	1
valid_sources[0x34]	2545	1			T5	1		T31	1		T59	1
valid_sources[0x35]	2246	1			T2	1		T11	1		T122	1
valid_sources[0x36]	2425	1			T5	1		T49	6		T2	1
valid_sources[0x37]	2300	1			T6	1		T105	1		T59	1
valid_sources[0x38]	2547	1			T4	1		T59	1		T2	3
valid_sources[0x39]	2803	1			T46	7		T2	2		T23	4
valid_sources[0x3a]	2274	1			T10	3		T38	1		T124	1
valid_sources[0x3b]	2444	1			T59	3		T55	1		T37	2
valid_sources[0x3c]	2575	1			T5	1		T59	1		T2	6
valid_sources[0x3d]	2492	1			T49	5		T59	1		T44	1
valid_sources[0x3e]	2548	1			T87	2		T2	2		T10	1
valid_sources[0x3f]	2545	1			T33	1		T87	2		T44	1
valid_sources[0x40]	2402	1			T6	1		T59	1		T2	1
valid_sources[0x41]	2535	1			T56	1		T2	1		T11	3
valid_sources[0x42]	3092	1			T6	1		T59	1		T2	3
valid_sources[0x43]	2936	1			T59	1		T2	1		T10	2
valid_sources[0x44]	3070	1			T58	1		T59	1		T44	1
valid_sources[0x45]	3381	1			T59	1		T2	1		T11	2
valid_sources[0x46]	3401	1			T59	1		T2	4		T11	6
valid_sources[0x47]	2891	1			T2	2		T50	1		T9	2
valid_sources[0x48]	2301	1			T2	4		T11	2		T9	1
valid_sources[0x49]	2620	1			T33	1		T44	2		T2	1
valid_sources[0x4a]	2944	1			T32	1		T43	1		T37	1
valid_sources[0x4b]	2627	1			T59	1		T2	3		T11	4
valid_sources[0x4c]	3159	1			T182	3		T38	1		T155	2
valid_sources[0x4d]	2907	1			T58	1		T59	1		T11	6
valid_sources[0x4e]	3265	1			T4	1		T59	1		T2	1
valid_sources[0x4f]	2218	1			T105	1		T59	3		T2	2
valid_sources[0x50]	2331	1			T5	1		T2	8		T11	2
valid_sources[0x51]	2848	1			T5	1		T32	1		T49	13
valid_sources[0x52]	2535	1			T58	1		T44	3		T2	2
valid_sources[0x53]	3438	1			T59	1		T43	2		T2	8
valid_sources[0x54]	2400	1			T2	3		T24	2		T10	2
valid_sources[0x55]	2503	1			T5	1		T59	1		T24	1
valid_sources[0x56]	3472	1			T2	1		T55	1		T9	6
valid_sources[0x57]	2737	1			T2	2		T153	1		T182	1
valid_sources[0x58]	2917	1			T58	1		T44	4		T2	2
valid_sources[0x59]	3656	1			T4	3		T59	3		T44	1
valid_sources[0x5a]	2245	1			T44	3		T2	2		T122	1
valid_sources[0x5b]	2591	1			T2	3		T55	1		T9	1
valid_sources[0x5c]	2881	1			T5	1		T56	1		T2	1
valid_sources[0x5d]	3006	1			T6	1		T43	1		T2	1
valid_sources[0x5e]	3110	1			T61	17		T44	1		T2	1
valid_sources[0x5f]	2851	1			T43	1		T44	4		T2	4
valid_sources[0x60]	2045	1			T59	1		T37	1		T123	1
valid_sources[0x61]	3038	1			T58	1		T24	1		T55	1
valid_sources[0x62]	2736	1			T59	1		T2	1		T9	1
valid_sources[0x63]	3164	1			T33	1		T2	1		T11	1
valid_sources[0x64]	2675	1			T5	2		T2	2		T11	11
valid_sources[0x65]	2813	1			T59	1		T2	2		T11	2
valid_sources[0x66]	2082	1			T32	2		T56	1		T2	3
valid_sources[0x67]	2968	1			T105	1		T2	1		T55	1
valid_sources[0x68]	2356	1			T4	1		T58	1		T2	1
valid_sources[0x69]	2420	1			T4	1		T5	2		T43	1
valid_sources[0x6a]	3574	1			T87	2		T2	1		T9	3
valid_sources[0x6b]	2340	1			T43	1		T2	3		T55	1
valid_sources[0x6c]	3324	1			T5	3		T49	4		T87	2
valid_sources[0x6d]	2527	1			T4	1		T59	2		T2	1
valid_sources[0x6e]	2210	1			T5	1		T44	1		T2	1
valid_sources[0x6f]	2156	1			T87	1		T59	1		T44	1
valid_sources[0x70]	3630	1			T2	1		T11	8		T182	1
valid_sources[0x71]	3556	1			T56	2		T24	1		T11	6
valid_sources[0x72]	3176	1			T56	1		T59	1		T2	2
valid_sources[0x73]	2833	1			T5	1		T59	2		T2	2
valid_sources[0x74]	2648	1			T5	1		T33	1		T105	1
valid_sources[0x75]	2905	1			T5	1		T56	1		T57	7
valid_sources[0x76]	2148	1			T4	1		T58	1		T11	4
valid_sources[0x77]	2505	1			T59	1		T2	1		T37	5
valid_sources[0x78]	2379	1			T49	1		T46	1		T2	1
valid_sources[0x79]	2591	1			T87	1		T58	1		T2	3
valid_sources[0x7a]	2902	1			T49	1		T59	1		T2	5
valid_sources[0x7b]	2282	1			T44	1		T2	1		T11	13
valid_sources[0x7c]	2571	1			T58	2		T2	2		T25	1
valid_sources[0x7d]	2283	1			T2	4		T10	4		T123	8
valid_sources[0x7e]	2762	1			T44	1		T2	1		T55	1
valid_sources[0x7f]	2820	1			T105	1		T2	1		T55	1
valid_sources[0x80]	2759	1			T2	2		T11	1		T9	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

136030

1

T4

8

T5

15

T27

5

values[0x0]

all_enables

biggest_size

193517

1

T4

1

T5

4

T6

1

values[0x1]

all_enables

biggest_size

166031

1

T4

3

T5

3

T6

2