Unified Coverage Report :: Module :: prim_subreg_shadow

Module : prim_subreg_shadow

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi	99.04	100.00	96.15			100.00	100.00
tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo	99.04	100.00	96.15			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.04	100.00	96.15			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.55	100.00	98.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_subreg_shadow

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T63,T64
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T63,T64
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T63,T64
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T63,T64

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Module : prim_subreg_shadow

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_subreg_shadow

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	10080	10080	0	0
MubiIsNotYetSupported_A	612394676	585687834	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10080	10080	0	0
T4	10	10	0	0
T5	10	10	0	0
T6	10	10	0	0
T27	10	10	0	0
T28	10	10	0	0
T29	10	10	0	0
T30	10	10	0	0
T31	10	10	0	0
T32	10	10	0	0
T33	10	10	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	612394676	585687834	0	0
T4	16866	16028	0	0
T5	11794	10942	0	0
T6	9642	8266	0	0
T27	22882	22206	0	0
T28	17688	16710	0	0
T29	40916	40608	0	0
T30	125684	124604	0	0
T31	11850	10562	0	0
T32	10254	9236	0	0
T33	9966	8514	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T64,T65,T66
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T64,T65,T66
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T63,T64,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T63,T64,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	90664409	86142713	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90664409	86142713	0	0
T4	2516	2367	0	0
T5	1797	1662	0	0
T6	1486	1256	0	0
T27	3494	3373	0	0
T28	2762	2586	0	0
T29	6220	6168	0	0
T30	18588	18412	0	0
T31	1796	1579	0	0
T32	1567	1391	0	0
T33	1538	1293	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T64,T65
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T63,T64,T65
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T63,T67,T66
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T63,T67,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	90664409	86142713	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	90664409	86142713	0	0
T4	2516	2367	0	0
T5	1797	1662	0	0
T6	1486	1256	0	0
T27	3494	3373	0	0
T28	2762	2586	0	0
T29	6220	6168	0	0
T30	18588	18412	0	0
T31	1796	1579	0	0
T32	1567	1391	0	0
T33	1538	1293	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T63,T67,T68
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T63,T67,T68
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T64,T68
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T68

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	44445125	43321724	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44445125	43321724	0	0
T4	1360	1332	0	0
T5	886	831	0	0
T6	697	628	0	0
T27	1707	1686	0	0
T28	1321	1293	0	0
T29	3098	3084	0	0
T30	10398	10336	0	0
T31	909	847	0	0
T32	763	722	0	0
T33	716	647	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T67,T68
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T67,T68
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T63,T64
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T63,T64

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	44445125	43321724	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	44445125	43321724	0	0
T4	1360	1332	0	0
T5	886	831	0	0
T6	697	628	0	0
T27	1707	1686	0	0
T28	1321	1293	0	0
T29	3098	3084	0	0
T30	10398	10336	0	0
T31	909	847	0	0
T32	763	722	0	0
T33	716	647	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T68,T69
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T65
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T68,T69
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T63,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T63,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T65

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	22222096	21660525	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22222096	21660525	0	0
T4	679	665	0	0
T5	443	415	0	0
T6	348	314	0	0
T27	854	844	0	0
T28	660	646	0	0
T29	1549	1542	0	0
T30	5198	5167	0	0
T31	453	422	0	0
T32	382	361	0	0
T33	358	323	0	0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T63,T69
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T70
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T63,T69
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T63,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T63,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T70

---

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	22222096	21660525	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22222096	21660525	0	0
T4	679	665	0	0
T5	443	415	0	0
T6	348	314	0	0
T27	854	844	0	0
T28	660	646	0	0
T29	1549	1542	0	0
T30	5198	5167	0	0
T31	453	422	0	0
T32	382	361	0	0
T33	358	323	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T63,T67
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T63,T67
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T64,T65
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T65

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	100614428	95784210	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100614428	95784210	0	0
T4	2620	2466	0	0
T5	1872	1732	0	0
T6	1547	1307	0	0
T27	3639	3513	0	0
T28	2783	2600	0	0
T29	6480	6425	0	0
T30	19364	19180	0	0
T31	1870	1644	0	0
T32	1632	1449	0	0
T33	1602	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T63,T67
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T63,T64
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T63,T67
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T64,T65,T70
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T64,T65,T70

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T63,T64

---

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	100614428	95784210	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	100614428	95784210	0	0
T4	2620	2466	0	0
T5	1872	1732	0	0
T6	1547	1307	0	0
T27	3639	3513	0	0
T28	2783	2600	0	0
T29	6480	6425	0	0
T30	19364	19180	0	0
T31	1870	1644	0	0
T32	1632	1449	0	0
T33	1602	1347	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T64,T67
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T64,T67
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T64,T67
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T67,T68
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T67,T68

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T64,T67

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	48251280	45934745	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48251280	45934745	0	0
T4	1258	1184	0	0
T5	899	831	0	0
T6	743	628	0	0
T27	1747	1687	0	0
T28	1318	1230	0	0
T29	3111	3085	0	0
T30	9294	9207	0	0
T31	897	789	0	0
T32	783	695	0	0
T33	769	647	0	0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T1 T11 T38 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
101        1/1                phase_q <= 1'b0;
           Tests:       T4 T5 T6 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T4 T5 T6 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T4 T5 T6 
105        1/1                phase_q <= 1'b0;
           Tests:       T1 T11 T38 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Total	Covered	Percent
Conditions	26	25	96.15
Logical	26	25	96.15
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T62,T64,T67
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Covered	T62,T64,T67
1	0	Covered	T1,T11,T38

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T62,T64,T67
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T6
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T62,T64,T66
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T62,T64,T66

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T62,T64,T67

---

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T6
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T11,T38
0	0	0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	1008	1008	0	0
MubiIsNotYetSupported_A	48251280	45934745	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1008	1008	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	48251280	45934745	0	0
T4	1258	1184	0	0
T5	899	831	0	0
T6	743	628	0	0
T27	1747	1687	0	0
T28	1318	1230	0	0
T29	3111	3085	0	0
T30	9294	9207	0	0
T31	897	789	0	0
T32	783	695	0	0
T33	769	647	0	0