Unified Coverage Report :: Module :: prim_clock_timeout

Module : prim_clock_timeout

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	100.00			75.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_prim_measure_0/rtl/prim_clock_timeout.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00
tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

---

Module Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00	100.00			100.00	50.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.33	100.00	100.00		100.00	100.00	66.67	u_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_out	100.00	100.00				100.00
u_ref_timeout	87.50	100.00	100.00			100.00	50.00

Line Coverage for Module : prim_clock_timeout

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
33         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T4 T5 T6 
35         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
36         1/1              end else if (timeout) begin
           Tests:       T2 T3 T36 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T2 T3 T36 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T2 T3 T36 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Module : prim_clock_timeout

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T36

---

Branch Coverage for Module : prim_clock_timeout

	Line No.	Total	Covered	Percent
Branches		4	3	75.00
IF	32	4	3	75.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Unreachable	T3,T36,T37
0	0	0	1	Covered	T2,T3,T36
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
33         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T4 T5 T6 
35         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
36         1/1              end else if (timeout) begin
           Tests:       T2 T3 T36 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T2 T3 T36 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T2 T3 T36 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T36

---

Branch Coverage for Instance : tb.dut.u_io_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Unreachable	T3,T36,T37
0	0	0	1	Covered	T2,T3,T36
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
33         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T4 T5 T6 
35         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
36         1/1              end else if (timeout) begin
           Tests:       T2 T3 T36 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T2 T3 T36 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T2 T3 T36 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T36

---

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Unreachable	T3,T36,T37
0	0	0	1	Covered	T2,T3,T36
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
33         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T4 T5 T6 
35         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
36         1/1              end else if (timeout) begin
           Tests:       T2 T3 T36 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T2 T3 T36 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T2 T3 T36 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T36

---

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Unreachable	T3,T36,T37
0	0	0	1	Covered	T2,T3,T36
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
33         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T4 T5 T6 
35         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
36         1/1              end else if (timeout) begin
           Tests:       T2 T3 T36 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T2 T3 T36 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T2 T3 T36 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T36

---

Branch Coverage for Instance : tb.dut.u_main_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Unreachable	T3,T36,T37
0	0	0	1	Covered	T2,T3,T36
0	0	0	0	Excluded		VC_COV_UNR

Line Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	30	0	0
ALWAYS	32	7	7	100.00

29                        logic timeout;
30         unreachable    assign timeout = int'(cnt) >= TimeOutCnt;
31                        always_ff @(posedge clk_i or negedge rst_ni) begin
32         1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
33         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
34         1/1              end else if (ack || !en_i) begin
           Tests:       T4 T5 T6 
35         1/1                cnt <= '0;
           Tests:       T4 T5 T6 
36         1/1              end else if (timeout) begin
           Tests:       T2 T3 T36 
37         unreachable        cnt <= '{default: '1};
38         1/1              end else if (en_i) begin
           Tests:       T2 T3 T36 
39         1/1                cnt <= cnt + 1'b1;
           Tests:       T2 T3 T36 
40                          end
                   ==>  MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (ack || ((!en_i)))
             -1-    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T36
0	1	Covered	T4,T5,T6
1	0	Covered	T2,T3,T36

---

Branch Coverage for Instance : tb.dut.u_usb_meas.u_meas.gen_clk_timeout_chk.u_timeout_ref_to_clk

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	32	3	3	100.00

32             if (!rst_ni) begin
               -1-  
33               cnt <= '0;
                 ==>
34             end else if (ack || !en_i) begin
                        -2-  
35               cnt <= '0;
                 ==>
36             end else if (timeout) begin
                        -3-  
37               cnt <= '{default: '1};
                 ==> (Unreachable)
38             end else if (en_i) begin
                        -4-  
39               cnt <= cnt + 1'b1;
                 ==>
40             end
               MISSING_ELSE
               ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
1	-	-	-	Covered	T4,T5,T6
0	1	-	-	Covered	T4,T5,T6
0	0	1	-	Unreachable	T3,T41,T13
0	0	0	1	Covered	T2,T3,T36
0	0	0	0	Excluded		VC_COV_UNR