Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	201594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

482838

1

T4

21

T5

8

T29

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	200032	1			T4	42		T5	12		T29	4
values[0x0]	228673	1			T4	18		T5	15		T6	2
values[0x1]	255727	1			T4	21		T5	10		T6	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	139145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

545287

1

T4

36

T5

13

T6

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2616	1			T30	1		T1	1		T88	2
valid_sources[0x01]	2611	1			T70	1		T1	1		T54	1
valid_sources[0x02]	2343	1			T5	1		T70	1		T54	1
valid_sources[0x03]	2469	1			T20	3		T22	1		T203	2
valid_sources[0x04]	2571	1			T1	2		T130	1		T20	3
valid_sources[0x05]	2863	1			T20	3		T26	1		T64	1
valid_sources[0x06]	2712	1			T60	1		T87	1		T176	1
valid_sources[0x07]	2729	1			T1	1		T94	1		T20	6
valid_sources[0x08]	4796	1			T34	1		T56	4		T89	1
valid_sources[0x09]	2729	1			T56	4		T88	11		T24	1
valid_sources[0x0a]	5317	1			T56	2		T130	1		T20	1
valid_sources[0x0b]	2342	1			T58	1		T130	2		T26	2
valid_sources[0x0c]	2538	1			T54	2		T56	2		T88	17
valid_sources[0x0d]	2731	1			T5	1		T1	2		T87	2
valid_sources[0x0e]	2629	1			T30	1		T1	1		T20	2
valid_sources[0x0f]	2471	1			T54	2		T55	1		T58	1
valid_sources[0x10]	2462	1			T5	1		T2	4		T130	1
valid_sources[0x11]	3308	1			T87	1		T94	2		T25	1
valid_sources[0x12]	2306	1			T54	3		T58	1		T20	2
valid_sources[0x13]	2725	1			T34	1		T70	1		T1	2
valid_sources[0x14]	2634	1			T52	1		T55	1		T56	7
valid_sources[0x15]	2455	1			T30	1		T1	1		T54	5
valid_sources[0x16]	2526	1			T20	1		T63	1		T28	1
valid_sources[0x17]	2603	1			T57	4		T91	29		T24	1
valid_sources[0x18]	3710	1			T55	1		T87	1		T88	6
valid_sources[0x19]	2338	1			T30	1		T89	1		T20	1
valid_sources[0x1a]	2418	1			T20	3		T40	13		T10	14
valid_sources[0x1b]	2526	1			T20	3		T27	4		T62	1
valid_sources[0x1c]	2199	1			T55	1		T56	6		T3	1
valid_sources[0x1d]	2932	1			T56	6		T130	1		T20	2
valid_sources[0x1e]	2982	1			T55	2		T176	1		T20	2
valid_sources[0x1f]	2976	1			T30	1		T1	2		T54	1
valid_sources[0x20]	2114	1			T20	2		T25	1		T28	8
valid_sources[0x21]	2623	1			T30	1		T1	1		T54	2
valid_sources[0x22]	2451	1			T20	3		T41	2		T66	1
valid_sources[0x23]	2517	1			T54	1		T60	2		T87	1
valid_sources[0x24]	3178	1			T5	1		T55	2		T130	2
valid_sources[0x25]	2691	1			T87	1		T3	1		T20	5
valid_sources[0x26]	2021	1			T60	1		T176	1		T130	2
valid_sources[0x27]	2030	1			T30	1		T1	1		T203	1
valid_sources[0x28]	3248	1			T1	2		T60	1		T119	5
valid_sources[0x29]	2319	1			T5	1		T1	2		T57	1
valid_sources[0x2a]	2757	1			T20	2		T28	4		T204	1
valid_sources[0x2b]	2305	1			T130	1		T20	1		T24	1
valid_sources[0x2c]	2736	1			T119	5		T3	3		T89	2
valid_sources[0x2d]	2429	1			T55	1		T56	2		T87	1
valid_sources[0x2e]	2404	1			T30	1		T20	1		T25	2
valid_sources[0x2f]	2397	1			T30	2		T3	4		T130	1
valid_sources[0x30]	2875	1			T30	1		T55	1		T20	3
valid_sources[0x31]	2456	1			T130	1		T24	1		T26	1
valid_sources[0x32]	2654	1			T30	1		T1	2		T54	1
valid_sources[0x33]	2452	1			T30	1		T1	1		T54	3
valid_sources[0x34]	3298	1			T1	1		T176	1		T24	2
valid_sources[0x35]	2864	1			T5	1		T34	1		T54	1
valid_sources[0x36]	2752	1			T55	1		T130	2		T20	7
valid_sources[0x37]	2683	1			T71	49		T130	2		T20	2
valid_sources[0x38]	3052	1			T176	1		T20	6		T24	1
valid_sources[0x39]	2006	1			T55	2		T56	2		T3	1
valid_sources[0x3a]	3024	1			T30	2		T176	1		T130	3
valid_sources[0x3b]	2437	1			T30	1		T89	1		T176	2
valid_sources[0x3c]	2464	1			T130	1		T62	1		T28	3
valid_sources[0x3d]	3377	1			T70	3		T20	4		T25	3
valid_sources[0x3e]	2533	1			T30	3		T87	2		T3	1
valid_sources[0x3f]	1879	1			T87	1		T51	4		T28	2
valid_sources[0x40]	2485	1			T24	1		T26	2		T28	1
valid_sources[0x41]	2585	1			T87	1		T130	1		T20	3
valid_sources[0x42]	1838	1			T55	1		T56	2		T87	1
valid_sources[0x43]	2894	1			T55	1		T57	8		T130	2
valid_sources[0x44]	2574	1			T5	1		T2	1		T3	1
valid_sources[0x45]	2718	1			T130	1		T63	3		T28	5
valid_sources[0x46]	2701	1			T5	1		T60	1		T20	12
valid_sources[0x47]	2345	1			T30	1		T130	1		T28	1
valid_sources[0x48]	4294	1			T1	2		T176	2		T130	1
valid_sources[0x49]	2394	1			T87	1		T176	1		T20	1
valid_sources[0x4a]	2132	1			T54	1		T3	1		T130	1
valid_sources[0x4b]	2218	1			T1	2		T176	1		T20	2
valid_sources[0x4c]	2750	1			T5	1		T30	1		T1	3
valid_sources[0x4d]	2714	1			T55	1		T87	2		T66	4
valid_sources[0x4e]	3176	1			T5	1		T55	1		T20	3
valid_sources[0x4f]	2718	1			T60	1		T3	1		T176	1
valid_sources[0x50]	2366	1			T20	1		T67	8		T28	2
valid_sources[0x51]	3169	1			T54	3		T55	1		T3	3
valid_sources[0x52]	2458	1			T20	3		T24	1		T28	6
valid_sources[0x53]	2462	1			T89	1		T20	3		T25	1
valid_sources[0x54]	2675	1			T5	1		T176	1		T130	1
valid_sources[0x55]	2726	1			T1	1		T28	2		T105	5
valid_sources[0x56]	2766	1			T130	1		T20	1		T25	1
valid_sources[0x57]	2974	1			T130	1		T20	1		T24	1
valid_sources[0x58]	2635	1			T57	5		T89	1		T20	1
valid_sources[0x59]	2841	1			T5	1		T1	1		T176	1
valid_sources[0x5a]	2525	1			T89	1		T130	1		T24	3
valid_sources[0x5b]	2597	1			T30	2		T1	2		T2	1
valid_sources[0x5c]	2185	1			T55	2		T130	2		T10	8
valid_sources[0x5d]	2557	1			T55	1		T20	1		T25	1
valid_sources[0x5e]	2498	1			T5	1		T34	2		T55	1
valid_sources[0x5f]	2840	1			T130	1		T20	3		T25	1
valid_sources[0x60]	2677	1			T55	2		T19	8		T20	6
valid_sources[0x61]	2413	1			T57	3		T26	2		T169	1
valid_sources[0x62]	2604	1			T87	1		T3	3		T20	5
valid_sources[0x63]	2480	1			T87	1		T130	2		T20	6
valid_sources[0x64]	2502	1			T70	1		T55	1		T60	1
valid_sources[0x65]	2299	1			T30	3		T176	2		T130	1
valid_sources[0x66]	3795	1			T1	2		T60	2		T87	3
valid_sources[0x67]	2221	1			T70	3		T1	7		T10	12
valid_sources[0x68]	2502	1			T130	1		T63	3		T51	2
valid_sources[0x69]	2877	1			T3	1		T20	4		T24	1
valid_sources[0x6a]	3328	1			T5	1		T30	1		T34	2
valid_sources[0x6b]	2837	1			T5	1		T94	5		T20	1
valid_sources[0x6c]	2404	1			T55	1		T60	1		T20	2
valid_sources[0x6d]	2374	1			T1	1		T58	1		T3	2
valid_sources[0x6e]	1929	1			T60	3		T176	1		T20	8
valid_sources[0x6f]	2198	1			T130	1		T20	3		T24	1
valid_sources[0x70]	3041	1			T5	1		T55	1		T89	2
valid_sources[0x71]	2493	1			T176	1		T130	2		T20	1
valid_sources[0x72]	2323	1			T2	1		T90	3		T10	3
valid_sources[0x73]	2122	1			T87	1		T130	1		T20	1
valid_sources[0x74]	1920	1			T3	1		T20	7		T26	1
valid_sources[0x75]	4928	1			T176	1		T130	2		T22	1
valid_sources[0x76]	2967	1			T55	1		T57	5		T176	1
valid_sources[0x77]	3146	1			T70	2		T176	1		T130	1
valid_sources[0x78]	2973	1			T5	1		T89	2		T63	1
valid_sources[0x79]	3138	1			T5	1		T1	4		T55	1
valid_sources[0x7a]	2305	1			T1	2		T54	3		T87	1
valid_sources[0x7b]	2586	1			T34	2		T54	1		T56	3
valid_sources[0x7c]	3034	1			T30	1		T1	1		T88	4
valid_sources[0x7d]	2867	1			T54	1		T20	4		T22	1
valid_sources[0x7e]	4527	1			T130	1		T20	7		T10	9
valid_sources[0x7f]	2664	1			T1	1		T54	4		T60	1
valid_sources[0x80]	2430	1			T5	1		T58	1		T130	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

135530

1

T4

13

T5

4

T29

2

values[0x0]

all_enables

biggest_size

185339

1

T4

6

T5

3

T30

4

values[0x1]

all_enables

biggest_size

161969

1

T4

2

T5

1

T30

2