Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T6,T91,T27
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T52
1	0	Covered	T31,T35,T92
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	160025372	8094	0	0
GateOpen_A	160025372	14109	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160025372	8094	0	0
T4	14803	4	0	0
T5	11073	0	0	0
T6	4978	7	0	0
T24	0	4	0	0
T29	6124	0	0	0
T30	17073	0	0	0
T31	4142	4	0	0
T32	3970	0	0	0
T33	5169	0	0	0
T34	15659	0	0	0
T35	3406	6	0	0
T52	0	4	0	0
T55	0	4	0	0
T88	0	4	0	0
T91	0	21	0	0
T92	0	8	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160025372	14109	0	0
T4	14803	4	0	0
T5	11073	4	0	0
T6	4978	11	0	0
T29	6124	4	0	0
T30	17073	0	0	0
T31	4142	8	0	0
T32	3970	0	0	0
T33	5169	4	0	0
T34	15659	4	0	0
T35	3406	10	0	0
T52	0	4	0	0
T70	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T91,T27,T66
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T52
1	0	Covered	T31,T35,T92
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	17240803	1927	0	0
GateOpen_A	17240803	3426	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240803	1927	0	0
T4	1641	1	0	0
T5	1346	0	0	0
T6	549	2	0	0
T24	0	1	0	0
T29	677	0	0	0
T30	1893	0	0	0
T31	445	1	0	0
T32	440	0	0	0
T33	568	0	0	0
T34	1834	0	0	0
T35	371	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	5	0	0
T92	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	17240803	3426	0	0
T4	1641	1	0	0
T5	1346	1	0	0
T6	549	3	0	0
T29	677	1	0	0
T30	1893	0	0	0
T31	445	2	0	0
T32	440	0	0	0
T33	568	1	0	0
T34	1834	1	0	0
T35	371	2	0	0
T52	0	1	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T6,T91,T27
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T52
1	0	Covered	T31,T35,T92
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	34482014	2048	0	0
GateOpen_A	34482014	3547	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34482014	2048	0	0
T4	3281	1	0	0
T5	2695	0	0	0
T6	1098	1	0	0
T24	0	1	0	0
T29	1353	0	0	0
T30	3786	0	0	0
T31	889	1	0	0
T32	880	0	0	0
T33	1136	0	0	0
T34	3667	0	0	0
T35	741	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	5	0	0
T92	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34482014	3547	0	0
T4	3281	1	0	0
T5	2695	1	0	0
T6	1098	2	0	0
T29	1353	1	0	0
T30	3786	0	0	0
T31	889	2	0	0
T32	880	0	0	0
T33	1136	1	0	0
T34	3667	1	0	0
T35	741	2	0	0
T52	0	1	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T6,T91,T27
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T52
1	0	Covered	T31,T35,T92
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	70722923	2062	0	0
GateOpen_A	70722923	3569	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722923	2062	0	0
T4	6587	1	0	0
T5	4688	0	0	0
T6	2220	2	0	0
T24	0	1	0	0
T29	2729	0	0	0
T30	7596	0	0	0
T31	1858	1	0	0
T32	1767	0	0	0
T33	2310	0	0	0
T34	6772	0	0	0
T35	1534	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	5	0	0
T92	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	70722923	3569	0	0
T4	6587	1	0	0
T5	4688	1	0	0
T6	2220	3	0	0
T29	2729	1	0	0
T30	7596	0	0	0
T31	1858	2	0	0
T32	1767	0	0	0
T33	2310	1	0	0
T34	6772	1	0	0
T35	1534	2	0	0
T52	0	1	0	0
T70	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

17                        logic clk_enabled;
18         1/1            always_comb clk_enabled = sw_clk_en && ip_clk_en || scanmode;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T31
0	1	Covered	T6,T91,T27
1	0	Covered	T4,T5,T6

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T52
1	0	Covered	T31,T35,T92
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	37579632	2057	0	0
GateOpen_A	37579632	3567	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579632	2057	0	0
T4	3294	1	0	0
T5	2344	0	0	0
T6	1111	2	0	0
T24	0	1	0	0
T29	1365	0	0	0
T30	3798	0	0	0
T31	950	1	0	0
T32	883	0	0	0
T33	1155	0	0	0
T34	3386	0	0	0
T35	760	3	0	0
T52	0	1	0	0
T55	0	1	0	0
T88	0	1	0	0
T91	0	6	0	0
T92	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	37579632	3567	0	0
T4	3294	1	0	0
T5	2344	1	0	0
T6	1111	3	0	0
T29	1365	1	0	0
T30	3798	0	0	0
T31	950	2	0	0
T32	883	0	0	0
T33	1155	1	0	0
T34	3386	1	0	0
T35	760	4	0	0
T52	0	1	0	0
T70	0	1	0	0