Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	173612005	30759	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	173612005	30759	0	0
T9	110710	84	0	0
T10	0	74	0	0
T11	0	314	0	0
T12	0	534	0	0
T13	0	377	0	0
T14	0	207	0	0
T15	0	136	0	0
T16	0	154	0	0
T17	0	258	0	0
T18	0	344	0	0
T19	34295	0	0	0
T20	365620	0	0	0
T21	14190	0	0	0
T22	10575	0	0	0
T23	5015	0	0	0
T24	9085	0	0	0
T25	10290	0	0	0
T26	10660	0	0	0
T27	7145	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	34722401	4526	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	4526	0	0
T9	22142	13	0	0
T10	0	11	0	0
T11	0	42	0	0
T12	0	70	0	0
T13	0	49	0	0
T14	0	33	0	0
T15	0	20	0	0
T16	0	25	0	0
T17	0	42	0	0
T18	0	54	0	0
T19	6859	0	0	0
T20	73124	0	0	0
T21	2838	0	0	0
T22	2115	0	0	0
T23	1003	0	0	0
T24	1817	0	0	0
T25	2058	0	0	0
T26	2132	0	0	0
T27	1429	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	34722401	4533	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	4533	0	0
T9	22142	13	0	0
T10	0	11	0	0
T11	0	41	0	0
T12	0	67	0	0
T13	0	48	0	0
T14	0	34	0	0
T15	0	20	0	0
T16	0	25	0	0
T17	0	42	0	0
T18	0	53	0	0
T19	6859	0	0	0
T20	73124	0	0	0
T21	2838	0	0	0
T22	2115	0	0	0
T23	1003	0	0	0
T24	1817	0	0	0
T25	2058	0	0	0
T26	2132	0	0	0
T27	1429	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	34722401	6218	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	6218	0	0
T9	22142	17	0	0
T10	0	15	0	0
T11	0	63	0	0
T12	0	108	0	0
T13	0	79	0	0
T14	0	42	0	0
T15	0	30	0	0
T16	0	32	0	0
T17	0	53	0	0
T18	0	70	0	0
T19	6859	0	0	0
T20	73124	0	0	0
T21	2838	0	0	0
T22	2115	0	0	0
T23	1003	0	0	0
T24	1817	0	0	0
T25	2058	0	0	0
T26	2132	0	0	0
T27	1429	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	34722401	6145	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	6145	0	0
T9	22142	17	0	0
T10	0	15	0	0
T11	0	63	0	0
T12	0	107	0	0
T13	0	78	0	0
T14	0	41	0	0
T15	0	26	0	0
T16	0	31	0	0
T17	0	51	0	0
T18	0	70	0	0
T19	6859	0	0	0
T20	73124	0	0	0
T21	2838	0	0	0
T22	2115	0	0	0
T23	1003	0	0	0
T24	1817	0	0	0
T25	2058	0	0	0
T26	2132	0	0	0
T27	1429	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	34722401	9337	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	9337	0	0
T9	22142	24	0	0
T10	0	22	0	0
T11	0	105	0	0
T12	0	182	0	0
T13	0	123	0	0
T14	0	57	0	0
T15	0	40	0	0
T16	0	41	0	0
T17	0	70	0	0
T18	0	97	0	0
T19	6859	0	0	0
T20	73124	0	0	0
T21	2838	0	0	0
T22	2115	0	0	0
T23	1003	0	0	0
T24	1817	0	0	0
T25	2058	0	0	0
T26	2132	0	0	0
T27	1429	0	0	0