Unified Coverage Report :: Module

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	21224	21224	0	0
OutputsKnown_A	1421734068	1342054336	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	208334406	193569798	0	13644
gen_flops.gen_stable_chks.OutputDelay_A	453444705	426438502	0	15918
gen_flops.gen_stable_chks.OutputIfUnstable_A	453444705	124390	0	0
gen_no_flops.OutputDelay_A	759954957	721959147	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	21224	21224
T4	28	28
T5	28	28
T6	28	28
T29	28	28
T30	28	28
T31	28	28
T32	28	28
T33	28	28
T34	28	28
T35	28	28

OutputsKnown_A

Name	Attempts	Real Successes
Total	1421734068	1342054336
T4	107154	105696
T5	88405	86611
T6	43890	41374
T29	44769	42590
T30	122445	121540
T31	36775	34811
T32	47017	42108
T33	45636	43932
T34	100706	98074
T35	41410	38762

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	208334406	193569798	13644
T4	10290	10104	18
T5	12300	12000	18
T6	6804	6330	18
T29	4428	4152	18
T30	11388	11274	18
T31	5754	5412	18
T32	10596	9360	18
T33	7074	6774	18
T34	6342	6138	18
T35	9468	8802	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	453444705	426438502	15918
T4	37464	36832	21
T5	28319	27649	21
T6	13740	12799	21
T29	15577	14632	21
T30	43039	42644	21
T31	11487	10802	21
T32	12658	11180	21
T33	14292	13691	21
T34	37098	35968	21
T35	11081	10289	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	453444705	124390
T4	27448	12
T5	28319	149
T6	13740	10
T29	15577	16
T30	43039	68
T31	11487	20
T32	12658	69
T33	14292	19
T34	37098	71
T35	11081	38
T53	0	33
T58	0	25
T59	0	79
T70	4658	0
T71	0	156
T87	0	168
T119	0	162

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	759954957	721959147
T4	59400	58721
T5	47786	46923
T6	23346	22206
T29	24764	23767
T30	68018	67583
T31	19534	18558
T32	23763	21529
T33	24270	23428
T34	57266	55929
T35	20861	19632

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	70722507	66560729	0	0
gen_flops.gen_stable_chks.OutputDelay_A	70722507	66554228	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	70722507	17715	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	70722507	66560729
T4	6586	6479
T5	4687	4580
T6	2220	2072
T29	2729	2567
T30	7595	7529
T31	1857	1749
T32	1766	1563
T33	2310	2216
T34	6772	6569
T35	1533	1426

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	70722507	66554228	2274
T4	6586	6476	3
T5	4687	4577	3
T6	2220	2069	3
T29	2729	2564	3
T30	7595	7526	3
T31	1857	1746	3
T32	1766	1560	3
T33	2310	2213	3
T34	6772	6566	3
T35	1533	1423	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	70722507	17715
T5	4687	38
T6	2220	0
T29	2729	0
T30	7595	0
T31	1857	0
T32	1766	18
T33	2310	3
T34	6772	15
T35	1533	0
T53	0	13
T58	0	12
T59	0	38
T70	1542	0
T71	0	83
T87	0	51
T119	0	78

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_no_flops.OutputDelay_A	34722401	32268377	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_no_flops.OutputDelay_A	34722401	32268377	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_stable_chks.OutputDelay_A	34722401	32261633	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	34722401	10740	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	34722401	10740
T5	2050	24
T6	1134	0
T29	738	0
T30	1898	0
T31	959	0
T32	1766	6
T33	1179	4
T34	1057	18
T35	1578	0
T53	0	12
T58	0	7
T59	0	2
T70	1558	0
T71	0	32
T87	0	67
T119	0	50

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T32 T33  | T5 T32 T33  | T5 T32 T33  | T5 T32 T33 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T32 T33

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T32,T33

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T32,T33
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_stable_chks.OutputDelay_A	34722401	32261633	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	34722401	12336	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	34722401	12336
T5	2050	36
T6	1134	0
T29	738	0
T30	1898	0
T31	959	0
T32	1766	19
T33	1179	2
T34	1057	16
T35	1578	0
T53	0	8
T58	0	6
T59	0	39
T70	1558	0
T71	0	41
T87	0	50
T119	0	34

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	76090055	0	0
gen_no_flops.OutputDelay_A	78319349	76090055	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	76090055
T4	6862	6836
T5	4883	4828
T6	2313	2286
T29	2843	2817
T30	7912	7886
T31	1928	1844
T32	1840	1771
T33	2406	2337
T34	7053	6927
T35	1598	1543

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	78319349	76090055
T4	6862	6836
T5	4883	4828
T6	2313	2286
T29	2843	2817
T30	7912	7886
T31	1928	1844
T32	1840	1771
T33	2406	2337
T34	7053	6927
T35	1598	1543

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	70722507	68647888	0	0
gen_no_flops.OutputDelay_A	70722507	68647888	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	70722507	68647888
T4	6586	6561
T5	4687	4635
T6	2220	2195
T29	2729	2704
T30	7595	7570
T31	1857	1777
T32	1766	1700
T33	2310	2244
T34	6772	6651
T35	1533	1481

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	70722507	68647888
T4	6586	6561
T5	4687	4635
T6	2220	2195
T29	2729	2704
T30	7595	7570
T31	1857	1777
T32	1766	1700
T33	2310	2244
T34	6772	6651
T35	1533	1481

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34481633	34481633	0	0
gen_no_flops.OutputDelay_A	34481633	34481633	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34481633	34481633
T4	3281	3281
T5	2695	2695
T6	1098	1098
T29	1352	1352
T30	3785	3785
T31	889	889
T32	879	879
T33	1135	1135
T34	3667	3667
T35	741	741

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34481633	34481633
T4	3281	3281
T5	2695	2695
T6	1098	1098
T29	1352	1352
T30	3785	3785
T31	889	889
T32	879	879
T33	1135	1135
T34	3667	3667
T35	741	741

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	17240419	17240419	0	0
gen_no_flops.OutputDelay_A	17240419	17240419	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	17240419	17240419
T4	1640	1640
T5	1345	1345
T6	549	549
T29	676	676
T30	1893	1893
T31	444	444
T32	439	439
T33	567	567
T34	1834	1834
T35	370	370

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	17240419	17240419
T4	1640	1640
T5	1345	1345
T6	549	549
T29	676	676
T30	1893	1893
T31	444	444
T32	439	439
T33	567	567
T34	1834	1834
T35	370	370

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	37579247	36501446	0	0
gen_no_flops.OutputDelay_A	37579247	36501446	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37579247	36501446
T4	3293	3281
T5	2344	2318
T6	1110	1098
T29	1364	1352
T30	3797	3785
T31	950	910
T32	883	850
T33	1154	1121
T34	3386	3326
T35	759	733

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37579247	36501446
T4	3293	3281
T5	2344	2318
T6	1110	1098
T29	1364	1352
T30	3797	3785
T31	950	910
T32	883	850
T33	1154	1121
T34	3386	3326
T35	759	733

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	34722401	32261633	0	2274

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	34722401	32261633	0	2274

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	34722401	32261633	0	2274

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	34722401	32261633	0	2274

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	34722401	32261633	0	2274

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	34722401	32261633	0	2274

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	34722401	32261633	2274
T4	1715	1684	3
T5	2050	2000	3
T6	1134	1055	3
T29	738	692	3
T30	1898	1879	3
T31	959	902	3
T32	1766	1560	3
T33	1179	1129	3
T34	1057	1023	3
T35	1578	1467	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_no_flops.OutputDelay_A	34722401	32268377	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_no_flops.OutputDelay_A	34722401	32268377	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_no_flops.OutputDelay_A	34722401	32268377	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	34722401	32268377	0	0
gen_no_flops.OutputDelay_A	34722401	32268377	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	34722401	32268377
T4	1715	1687
T5	2050	2003
T6	1134	1058
T29	738	695
T30	1898	1882
T31	959	905
T32	1766	1563
T33	1179	1132
T34	1057	1026
T35	1578	1470

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_flops.gen_stable_chks.OutputDelay_A	78319349	73840252	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	78319349	20866	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	78319349	73840252	2274
T4	6862	6747	3
T5	4883	4768	3
T6	2313	2155	3
T29	2843	2671	3
T30	7912	7840	3
T31	1928	1813	3
T32	1840	1625	3
T33	2406	2305	3
T34	7053	6839	3
T35	1598	1483	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	78319349	20866
T4	6862	3
T5	4883	12
T6	2313	3
T29	2843	5
T30	7912	13
T31	1928	5
T32	1840	9
T33	2406	3
T34	7053	5
T35	1598	12

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_no_flops.OutputDelay_A	78319349	73846861	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_flops.gen_stable_chks.OutputDelay_A	78319349	73840252	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	78319349	20953	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	78319349	73840252	2274
T4	6862	6747	3
T5	4883	4768	3
T6	2313	2155	3
T29	2843	2671	3
T30	7912	7840	3
T31	1928	1813	3
T32	1840	1625	3
T33	2406	2305	3
T34	7053	6839	3
T35	1598	1483	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	78319349	20953
T4	6862	3
T5	4883	10
T6	2313	1
T29	2843	3
T30	7912	23
T31	1928	5
T32	1840	5
T33	2406	3
T34	7053	5
T35	1598	9

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_no_flops.OutputDelay_A	78319349	73846861	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_flops.gen_stable_chks.OutputDelay_A	78319349	73840252	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	78319349	20765	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	78319349	73840252	2274
T4	6862	6747	3
T5	4883	4768	3
T6	2313	2155	3
T29	2843	2671	3
T30	7912	7840	3
T31	1928	1813	3
T32	1840	1625	3
T33	2406	2305	3
T34	7053	6839	3
T35	1598	1483	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	78319349	20765
T4	6862	3
T5	4883	12
T6	2313	5
T29	2843	5
T30	7912	13
T31	1928	5
T32	1840	5
T33	2406	3
T34	7053	5
T35	1598	5

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_no_flops.OutputDelay_A	78319349	73846861	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_flops.gen_stable_chks.OutputDelay_A	78319349	73840252	0	2274
gen_flops.gen_stable_chks.OutputIfUnstable_A	78319349	21015	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	78319349	73840252	2274
T4	6862	6747	3
T5	4883	4768	3
T6	2313	2155	3
T29	2843	2671	3
T30	7912	7840	3
T31	1928	1813	3
T32	1840	1625	3
T33	2406	2305	3
T34	7053	6839	3
T35	1598	1483	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	78319349	21015
T4	6862	3
T5	4883	17
T6	2313	1
T29	2843	3
T30	7912	19
T31	1928	5
T32	1840	7
T33	2406	1
T34	7053	7
T35	1598	12

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	758	758	0	0
OutputsKnown_A	78319349	73846861	0	0
gen_no_flops.OutputDelay_A	78319349	73846861	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	758	758
T4	1	1
T5	1	1
T6	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1
T34	1	1
T35	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	78319349	73846861
T4	6862	6750
T5	4883	4771
T6	2313	2158
T29	2843	2674
T30	7912	7843
T31	1928	1816
T32	1840	1628
T33	2406	2308
T34	7053	6842
T35	1598	1486

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl