Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

22                      
23         1/1            always_comb reset_or_disable = !rst_ni || disable_sva;
           Tests:       T4 T5 T6 

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T57,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	34722401	32187172	0	0
AllClkBypReqTrue_A	34722401	79038	0	0
IoClkBypReqFalse_A	34722401	32132392	0	2274
IoClkBypReqTrue_A	34722401	129484	0	0
LcClkBypAckFalse_A	34722401	32190073	0	0
LcClkBypAckTrue_A	34722401	76137	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	32187172	0	0
T4	1715	1686	0	0
T5	2050	1695	0	0
T6	1134	1057	0	0
T29	738	694	0	0
T30	1898	1881	0	0
T31	959	904	0	0
T32	1766	1467	0	0
T33	1179	1131	0	0
T34	1057	929	0	0
T35	1578	1469	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	79038	0	0
T5	2050	307	0	0
T6	1134	0	0	0
T29	738	0	0	0
T30	1898	0	0	0
T31	959	0	0	0
T32	1766	95	0	0
T33	1179	0	0	0
T34	1057	96	0	0
T35	1578	0	0	0
T53	0	51	0	0
T58	0	39	0	0
T59	0	101	0	0
T70	1558	0	0	0
T71	0	361	0	0
T87	0	402	0	0
T90	0	35	0	0
T119	0	116	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	32132392	0	2274
T4	1715	1684	0	3
T5	2050	1580	0	3
T6	1134	1055	0	3
T29	738	692	0	3
T30	1898	1879	0	3
T31	959	902	0	3
T32	1766	1464	0	3
T33	1179	1084	0	3
T34	1057	890	0	3
T35	1578	1467	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	129484	0	0
T5	2050	420	0	0
T6	1134	0	0	0
T29	738	0	0	0
T30	1898	0	0	0
T31	959	0	0	0
T32	1766	96	0	0
T33	1179	45	0	0
T34	1057	133	0	0
T35	1578	0	0	0
T53	0	80	0	0
T58	0	74	0	0
T59	0	30	0	0
T70	1558	0	0	0
T71	0	392	0	0
T87	0	568	0	0
T119	0	588	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	32190073	0	0
T4	1715	1686	0	0
T5	2050	1686	0	0
T6	1134	1057	0	0
T29	738	694	0	0
T30	1898	1881	0	0
T31	959	904	0	0
T32	1766	1506	0	0
T33	1179	1119	0	0
T34	1057	976	0	0
T35	1578	1469	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	34722401	76137	0	0
T5	2050	316	0	0
T6	1134	0	0	0
T29	738	0	0	0
T30	1898	0	0	0
T31	959	0	0	0
T32	1766	56	0	0
T33	1179	12	0	0
T34	1057	49	0	0
T35	1578	0	0	0
T53	0	67	0	0
T58	0	50	0	0
T59	0	26	0	0
T70	1558	0	0	0
T71	0	221	0	0
T87	0	341	0	0
T119	0	240	0	0