Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	313279108	8981	0	0
TransStop_A	313279108	4673	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313279108	8981	0	0
T4	27448	4	0	0
T5	19536	0	0	0
T6	9256	0	0	0
T21	0	28	0	0
T24	0	4	0	0
T29	11372	3	0	0
T30	31652	15	0	0
T31	7716	0	0	0
T32	7364	0	0	0
T33	9628	0	0	0
T34	28216	0	0	0
T35	6396	0	0	0
T54	0	27	0	0
T55	0	4	0	0
T56	0	23	0	0
T88	0	4	0	0
T130	0	29	0	0
T142	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	313279108	4673	0	0
T4	27448	4	0	0
T5	19536	0	0	0
T6	9256	0	0	0
T21	0	14	0	0
T24	0	4	0	0
T29	11372	0	0	0
T30	31652	10	0	0
T31	7716	0	0	0
T32	7364	0	0	0
T33	9628	0	0	0
T34	28216	0	0	0
T35	6396	0	0	0
T54	0	15	0	0
T55	0	4	0	0
T56	0	3	0	0
T63	0	3	0	0
T88	0	4	0	0
T130	0	15	0	0
T142	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	78319777	2217	0	0
TransStop_A	78319777	1156	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	2217	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	8	0	0
T24	0	1	0	0
T29	2843	0	0	0
T30	7913	5	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	6	0	0
T55	0	1	0	0
T56	0	8	0	0
T88	0	1	0	0
T130	0	7	0	0
T142	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	1156	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	4	0	0
T24	0	1	0	0
T29	2843	0	0	0
T30	7913	4	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	4	0	0
T55	0	1	0	0
T56	0	2	0	0
T63	0	1	0	0
T88	0	1	0	0
T130	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	78319777	2256	0	0
TransStop_A	78319777	1157	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	2256	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	6	0	0
T24	0	1	0	0
T29	2843	1	0	0
T30	7913	3	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T130	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	1157	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	2	0	0
T24	0	1	0	0
T29	2843	0	0	0
T30	7913	2	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	1	0	0
T88	0	1	0	0
T130	0	4	0	0
T142	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	78319777	2255	0	0
TransStop_A	78319777	1183	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	2255	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	7	0	0
T24	0	1	0	0
T29	2843	1	0	0
T30	7913	4	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	9	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T130	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	1183	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	3	0	0
T24	0	1	0	0
T29	2843	0	0	0
T30	7913	2	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	5	0	0
T55	0	1	0	0
T63	0	1	0	0
T88	0	1	0	0
T130	0	4	0	0
T142	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	78319777	2253	0	0
TransStop_A	78319777	1177	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	2253	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	7	0	0
T24	0	1	0	0
T29	2843	1	0	0
T30	7913	3	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	5	0	0
T88	0	1	0	0
T130	0	6	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78319777	1177	0	0
T4	6862	1	0	0
T5	4884	0	0	0
T6	2314	0	0	0
T21	0	5	0	0
T24	0	1	0	0
T29	2843	0	0	0
T30	7913	2	0	0
T31	1929	0	0	0
T32	1841	0	0	0
T33	2407	0	0	0
T34	7054	0	0	0
T35	1599	0	0	0
T54	0	3	0	0
T55	0	1	0	0
T63	0	1	0	0
T88	0	1	0	0
T130	0	3	0	0
T142	0	1	0	0